TW350129B - Manufacturing method of semiconductor formation latches the invention relates to a manufacturing method of semiconductor formation latches - Google Patents

Manufacturing method of semiconductor formation latches the invention relates to a manufacturing method of semiconductor formation latches

Info

Publication number
TW350129B
TW350129B TW086108491A TW86108491A TW350129B TW 350129 B TW350129 B TW 350129B TW 086108491 A TW086108491 A TW 086108491A TW 86108491 A TW86108491 A TW 86108491A TW 350129 B TW350129 B TW 350129B
Authority
TW
Taiwan
Prior art keywords
latches
manufacturing
semiconductor formation
metal layer
relates
Prior art date
Application number
TW086108491A
Other languages
Chinese (zh)
Inventor
Kyeong-Keun Choi
Original Assignee
Hyundai Electronics Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Electronics Industries Co Ltd filed Critical Hyundai Electronics Industries Co Ltd
Application granted granted Critical
Publication of TW350129B publication Critical patent/TW350129B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Weting (AREA)

Abstract

A sort of manufacturing method of semiconductor formation latches, including: etching on the silicon substrate the insulation layer for forming of the contact hole; forming by the insulator, including said contact hole the first metal layer, for embedding of the metal into said contact hole; forming in said first metal layer the second metal layer, which has an etch rate lower than the first metal layer, with a poorer step coating capacity; etch by means of carpet etching the first and the second metal layer.
TW086108491A 1996-06-28 1997-06-18 Manufacturing method of semiconductor formation latches the invention relates to a manufacturing method of semiconductor formation latches TW350129B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960024938A KR100221584B1 (en) 1996-06-28 1996-06-28 Forming method for plug of semiconductor device

Publications (1)

Publication Number Publication Date
TW350129B true TW350129B (en) 1999-01-11

Family

ID=19464167

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086108491A TW350129B (en) 1996-06-28 1997-06-18 Manufacturing method of semiconductor formation latches the invention relates to a manufacturing method of semiconductor formation latches

Country Status (3)

Country Link
JP (1) JPH1065005A (en)
KR (1) KR100221584B1 (en)
TW (1) TW350129B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100472722B1 (en) * 1999-06-30 2005-03-07 주식회사 하이닉스반도체 Method for forming line and plug metal wire capable of reducing damage of under layer
KR100671561B1 (en) * 2004-12-27 2007-01-19 동부일렉트로닉스 주식회사 Method of forming interconnection line for semiconductor device

Also Published As

Publication number Publication date
KR980005570A (en) 1998-03-30
KR100221584B1 (en) 1999-09-15
JPH1065005A (en) 1998-03-06

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