KR20140074121A - Liquid crystal display - Google Patents

Abstract

An embodiment of the present invention discloses a liquid crystal display device which includes: a m by n liquid crystal cells disposed in a matrix form by a cross structure of m transverse data lines and n longitudinal gate lines, and TFTs connected to the liquid crystal cells; a data driving circuit for supplying a data voltage to the data lines in response to a polar control signal; and a gate driving circuit for supplying the gate lines, wherein the liquid cells include a first liquid crystal cell disposed on the left side of the first gate line, a second liquid crystal cell disposed on the left side of the first gate line, a third liquid crystal cell disposed on the left side of the second gate line, and a fourth liquid crystal cell disposed on the right side of the second gate line, and the TFTs include a first TFT for charging a data voltage from the first data line in the first liquid crystal cell in response to a first gate pulse supplied to the first gate line, a second TFT for charging a data voltage from the second data line in the second liquid crystal cell in response to a first gate pulse supplied to the first gate line, a third TFT for charging a data voltage from the second data line in the third liquid crystal cell in response to a second gate pulse supplied to the second gate line, and a fourth TFT for charging a data voltage from the first data line in the third liquid crystal cell in response to the second gate pulse supplied to the second gate line.

Description

[0001] LIQUID CRYSTAL DISPLAY [0002]

The present invention relates to a liquid crystal display device compensating for a parasitic capacitance (Cgs) deviation of a TFT.

An active matrix liquid crystal display device uses a TFT as a switching element to turn on / off a signal input to each pixel to display an image.

The TFT includes a source electrode, a drain electrode, and a gate electrode formed of a metal, and turns on / off a signal input to the gate electrode to transmit a signal input to the source electrode to the drain electrode.

The parasitic capacitance (Cgs) exists between the gate electrode and the source electrode of the TFT. When the parasitic capacitance of the TFT disposed in each pixel deviates, the signal input to each pixel may be different.

 Therefore, the liquid crystal display device is provided with a compensating circuit for correcting this parasitic capacitance, or the parasitic capacitance is compensated by making the direction of the TFT in one direction.

Incidentally, in the case of providing a compensation circuit or arranging the TFT so as to be directed to one direction, there arises a problem that the aperture ratio of the pixel decreases as the non-display region is elongated.

For example, in a panel structure in which pixels adjacent to one gate line are concurrently connected to each other, such as a DRD panel, a TFT of a pixel arranged on the left side with respect to the gate line and a TFT disposed on the right side of the pixel are arranged in the gate line Symmetrically. However, if the TFTs are arranged in the same direction in order to solve the parasitic capacitance problem of the TFT described above, the wiring connecting the gate electrodes in the gate lines can only be bypassed.

The present invention has been made in view of this background, and is aimed at reducing parasitic capacitance difference between TFTs.

In an embodiment of the present invention, a liquid crystal layer is formed between an upper substrate and a lower substrate, and m x n rows arranged in a matrix form by an intersection structure of m horizontal data lines and n vertical gate lines A liquid crystal display panel including liquid crystal cells and TFTs connected to the liquid crystal cells, a data driving circuit for supplying a data voltage to the data lines in response to a polarity control signal, a gate driving circuit Wherein the liquid crystal cells include a first liquid crystal cell arranged on the left side of the first gate line, a second liquid crystal cell arranged on the right side of the first gate line, a third liquid crystal cell arranged on the left side of the second gate line, And a fourth liquid crystal cell arranged on the right side of the second gate line, wherein the TFTs are arranged in a first data line in response to a first gate pulse supplied to the first gate line A second TFT which charges a data voltage from the second data line to the second liquid crystal cell in response to a first gate pulse supplied to the first gate line, A third TFT for supplying a data voltage from the second data line to the third liquid crystal cell in response to a second gate pulse supplied to the second gate line, And a fourth TFT for charging a data voltage from the first data line into the fourth liquid crystal cell in response to a gate pulse.

A data voltage of a first polarity is applied to the first data line for one frame and a data voltage that is opposite in phase to the first polarity is applied to the second data line for one frame.

Wherein the first gate pulse occurs during one horizontal period (1H), the first liquid crystal cell and the second liquid crystal cell are charged during the one horizontal period, and the second gate pulse occurs during one horizontal period (1H) And the third liquid crystal cell and the fourth liquid crystal cell are charged during the one horizontal period (1H).

According to an embodiment of the present invention, a liquid crystal display panel in which two columns of liquid crystal cells are connected to one gate line arranged in the vertical direction is referred to as a 1-dot version in the column direction (or gate line direction) (dot inversion) in the line direction (or in the data line direction), the stain generated due to the parasitic capacitance of the TFT is displayed in a 2-dot form, and the stain level is remarkably reduced Can be obtained.

1 is a block diagram showing a liquid crystal display device according to an embodiment of the present invention.
2 is an equivalent circuit diagram showing the pixel array of the liquid crystal display device shown in FIG. 1 in detail.
FIGS. 3 and 4 are circuit diagrams showing the data driving circuit shown in FIG. 1 in detail.
5 is a waveform diagram showing data voltages whose polarity is controlled in accordance with a polarity control signal and gate pulses synchronized with the data voltages.
6 is a view showing data polarity charged in each liquid crystal cell.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

Hereinafter, a liquid crystal display according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2. FIG.

1 and 2, the liquid crystal display device of this embodiment includes a liquid crystal display panel 100, a timing controller 101, a POL logic circuit 102, a data driving circuit 103, and a gate driving circuit 104 do.

The liquid crystal display panel 100 includes an upper glass substrate and a lower glass substrate opposed to each other with a liquid crystal layer interposed therebetween. The liquid crystal display panel 100 includes a pixel array 10 for displaying video data.

The pixel array 10 includes n (n is a positive integer) data lines D1 to Dn arranged in a horizontal direction and m (m is a positive integer) gate lines G1 to Gm The liquid crystal display device of the present invention includes m x n liquid crystal cells Clc arranged in a matrix form by the intersection structure of the liquid crystal cells Clc.

The liquid crystal cells Clc of the pixel array 10 are connected to the electric field generated by the voltage difference between the data voltage supplied to the pixel electrode 1 through the TFT and the common voltage Vcom supplied to the common electrode 2 The data voltage is charged and the data voltage is maintained for a predetermined period by the storage capacitor Cst to display an image.

The pixel array 10 includes m data lines D1 to Dm, n gate lines G1 to Gn, mxn pixel electrodes 1 and mx n TFTs, and m x n storage capacitors connected to the pixel electrodes 1.

TFTs neighboring left and right in the same line in the longitudinal direction are connected to the same gate line. Such a connection structure of the TFT and the gate line is shown in Fig. A gate driving circuit 104 connected directly to the gate lines G1 to Gn may be directly formed on the upper and lower non-display surfaces of the lower glass substrate of the liquid crystal display panel outside the pixel array 10. [ In this case, the pixel array 10 and the gate drive circuit 104 are simultaneously formed on the lower glass substrate of the liquid crystal display panel 100 by the same thin film process.

On the upper glass substrate of the liquid crystal display panel 100, a black matrix, a color filter, and a common electrode are formed. The common electrode is formed on the upper glass substrate in a vertical electric field driving method such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode, and a horizontal electric field such as IPS (In Plane Switching) mode and FFS (Fringe Field Switching) Is formed on the lower glass substrate together with the pixel electrode 1 in the driving method.

On the upper glass substrate and the lower glass substrate of the liquid crystal display panel 100, a polarizing plate is attached and an alignment film for setting a pre-tilt angle of the liquid crystal is formed.

The liquid crystal mode of the liquid crystal display panel 100 applicable to the present invention may be implemented in any liquid crystal mode as well as the TN mode, VA mode, IPS mode, and FFS mode described above. Further, the liquid crystal display device of the present invention can be implemented in any form such as a transmissive liquid crystal display device, a transflective liquid crystal display device, a reflective liquid crystal display device, and the like. In a transmissive liquid crystal display device and a transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as an edge type backlight unit or a direct type backlight unit. The edge type backlight unit has a structure in which a light source is disposed so as to face the side face of the light guide plate and a plurality of optical sheets are disposed between the liquid crystal display panel and the light guide plate. The direct type backlight unit has a structure in which the optical sheets and the diffusion plate are stacked under the liquid crystal display panel 100 and a plurality of light sources are disposed under the diffusion plate. The light source of the backlight unit may include at least one of a hot cathode fluorescent lamp (HCFL), a cold cathode fluorescent lamp (CCFL), an external electro fluorescent lamp (EEFL), and a light emitting diode (LED).

The liquid crystal cell Clc and the TFT disposed on the left side of the odd gate lines G1, G3, ... are hereinafter referred to as the first liquid crystal cell and the first TFT T1 and the odd gate lines G1, G3,. The liquid crystal cell Clc and the TFT disposed on the right side of the outermost gate lines G2, G4, ..., Gm-1 are arranged in the second liquid crystal cell and the second TFT T2, respectively, The liquid crystal cell Clc and the TFT are respectively connected to the third liquid crystal cell and the third TF (T3) and the liquid crystal cell Clc and TFT disposed on the right side of the even gate lines G2, G4, Is defined as a liquid crystal cell and a fourth TFT (T4).

The first TFT T1 is turned on in response to gate pulses (or scan pulses) from the odd gate lines G1, G3 ... to the data voltages (D1, D3, ..., Dm / 2-1) To the pixel electrode (1) of the first liquid crystal cell (Clc). To this end, the gate electrode of the first TFT T1 is connected to the odd gate lines G1, G3,..., And the source electrode thereof is connected to the odd data lines D1, D3,. The drain electrode of the first TFT (T1) is connected to the pixel electrode (1) of the first liquid crystal cell (Clc). The second TFT T2 applies a data voltage from the even data lines D2, D4, ... to the pixels of the second liquid crystal cell Clc in response to gate pulses from the odd gate lines G1, G3, To the electrode (1). To this end, the gate electrode of the second TFT T2 is connected to the odd gate lines G1, G3,..., And the source electrode thereof is connected to the even data lines D2, D4,. The drain electrode of the second TFT T2 is connected to the pixel electrode 1 of the second liquid crystal cell Clc. The third TFT T3 supplies the data voltage from the even data lines D2, D4, ... to the pixels of the third liquid crystal cell Clc in response to the gate pulse from the even gate lines G2, G4, To the electrode (1). To this end, the gate electrode of the third TFT T3 is connected to the even gate lines G2, G4,..., And the source electrode thereof is connected to the even data lines D2, D4,. And the drain electrode of the third TFT T3 is connected to the pixel electrode 1 of the third liquid crystal cell Clc. The fourth TFT T4 supplies the data voltage from the odd data lines D1, D3, ... to the pixels of the fourth liquid crystal cell Clc in response to the gate pulse from the even gate lines G2, G4, To the electrode (1). To this end, the gate electrode of the fourth TFT T4 is connected to the even gate lines G2, G4,..., And the source electrode thereof is connected to the odd data lines D1, D3,. And the drain electrode of the fourth TFT T4 is connected to the pixel electrode 1 of the fourth liquid crystal cell Clc.

In this embodiment, liquid crystal cells of the same color are arranged along the longitudinal direction (or the gate line direction) of the liquid crystal cell, and the red liquid crystal cell R, green A liquid crystal cell G, and a blue liquid crystal cell B are arranged in this order. Thus, the first TFT T1 is connected to the red liquid crystal cell R in the data line direction, the second TFT T2 is connected to the green liquid crystal cell G, and the third TFT T3 is connected to the red Is connected to the blue liquid crystal cell B, and the fourth TFT T4 is connected to the red liquid crystal cell R again.

In this embodiment, the red, green, and blue liquid crystal cells R, G, and B are connected to one data line in accordance with the formation of the pixel array, have. In addition, the first column liquid crystal cells arranged on the left side and the second column liquid crystal cells arranged on the right side can be simultaneously charged with one gate line during one horizontal period (1H) in which the gate pulse is applied.

The timing controller 101 receives vertical and horizontal synchronization signals Vsync and Hsync and data enable signals Data from the system board 105 through an interface such as a Low Voltage Differential Signaling (LVDS) interface and a Transition Minimized Differential Signaling And generates a control signal for controlling the operation timing of the data driving circuit 103, the gate driving circuit 104, and the POL logic circuit 102 in response to a timing signal such as a clock enable signal (CLK). The timing controller 101 transmits the RGB digital video data in series to the source drive ICs of the data driving circuit 103 in a mini LVDS interface manner. The timing controller generates a data timing control signal for controlling the data driving circuit 103 and a gate timing control signal for controlling the gate driving circuits 13 using the timing signal. The timing controller controls the gate timing control signal and the timing control signal so that digital video data input at a frame frequency of 60 Hz can be reproduced in the pixel array 10 of the liquid crystal display panel at a frame frequency of 60 x i (i is a positive integer of 2 or more) The frequency of the data timing control signal can be multiplied by a frame frequency of 60 x i Hz. The control signals output from the timing controller 101 include a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable (GOE), a source start pulse (SSP), a source sampling clock (SSC), a source output enable (SOE) signal, and a reference polarity control signal (POL). The gate start pulse (GSP) indicates a starting horizontal line at which the scanning starts from one vertical period in which one screen is displayed. The gate shift clock signal GSC is input to the shift register in the gate drive circuit and is a timing control signal for sequentially shifting the gate start pulse GSP. The gate shift clock signal GSC is generated with a pulse width corresponding to the ON period of the TFT. The gate output enable signal GOE indicates the output of the gate drive circuit 104. [ The source start pulse SSP indicates a starting pixel in one horizontal line where data is to be displayed. The source sampling clock SSC instructs the latch operation of data in the data driving circuit 103 on the basis of the rising or falling edge. The source output enable signal (SOE) indicates the output of the data driving circuit 103. The reference polarity control signal POL indicates the polarity of the data voltage to be supplied to the liquid crystal cells Clc of the liquid crystal display panel 100. The logic of the reference polarity control signal POL is inverted in one frame period. The source start pulse SSP and the source sampling clock SSC may be omitted if data is transmitted from the timing controller 101 to the data driving circuit 103 through the mini LVDS interface.

The data driving circuit 103 latches the digital video data RGB under the control of the timing controller 101. [ The data driving circuit 103 converts the latched digital video data into an analog positive / negative gamma compensation voltage in response to the polarity control signal POL from the timing controller 101 to generate a positive / negative data voltage do. The data driving circuit 103 supplies the positive polarity / negative polarity data voltages to the data lines D1 to Dm.

The gate driver circuit 104 includes a level shifter for converting the output signal of the shift register and the shift register into a swing width suitable for driving the TFT of the liquid crystal cell, and an output buffer connected between the level shifter and the gate lines G1 to G2n And a plurality of gate drive ICs. The gate drive circuit 104 sequentially outputs gate pulses having a pulse width of one horizontal period synchronized with the positive / negative polarity data voltages.

The system board 105 includes a broadcast signal receiving circuit, an external device interface circuit, a graphic processing circuit, a memory, and the like. The system board 105 extracts video data from a broadcast signal or an image source input from an external device, converts the video data into digital data, To the controller (101). The interlaced broadcast signal received by the system board 105 exists only in the odd line in the odd frame period and exists only in the odd line in the odd frame period. Upon receiving the interlaced broadcast signal, the system board 105 generates the odd line data of the odd frame period and the odd line data of the odd frame by the average value or the black data value of the data stored in the memory. The system board 105 supplies timing signals (Vsync, Hsync, DE, CLK) together with digital video data to the timing controller 101 and supplies power to a module power supply circuit (not shown). The module power supply circuit adjusts a voltage supplied from the system board 105 to generate a voltage required for driving the digital circuits of the module and a driving voltage of the liquid crystal display panel.

3 and 4 are circuit diagrams showing the source drive IC of the data driving circuit 103 in detail.

Referring to FIGS. 3 and 4, each of the source drive ICs supplies a data voltage to k (k is an integer smaller than m) data lines D1 to Dk. Each of the source drive ICs includes a shift register 31, a data register 32, a first latch 33, a second latch 34, a digital / analog converter (hereinafter referred to as DAC) 35, A Charge Share Circuit 36 and an output circuit 37. [ The shift register 31 generates a sampling clock from the timing controller 101 and transfers the carry signal CAR to the shift register 31 of the next source drive IC. The data register 32 temporarily stores the odd digital video data RGBodd and the excellent digital video data RGBeven separated by the timing controller 101 and stores the stored data RGBodd and RGBeven in the first latch 33 Supply. The first latch 33 samples the digital video data RGBeven and RGBodd from the data register 32 in response to a sampling signal sequentially input from the shift register 31 and supplies the data RGBeven and RGBodd ), And then outputs the latched data at the same time. The second latch 34 latches the data input from the first latch 33 and then latches the digital data latched simultaneously with the second latch 34 of the other integrated circuits during the low logic period of the source output enable signal SOE. Simultaneously output video data. The DAC 35 includes a P-decoder (PDEC) 41 to which a positive gamma reference voltage GH is supplied, an N-decoder (NDEC) 42 to which a negative gamma reference voltage GL is supplied, And a multiplexer 43 for selecting the output of the P-decoder 41 and the output of the N-decoder 42 in response to the polarity control signal POL. The P-decoder 41 decodes the digital video data input from the second latch 34 and outputs a positive gamma compensation voltage corresponding to the gray level value of the data, and the N-decoder 42 outputs the positive gamma compensation voltage to the second latch 34, and outputs a negative gamma compensation voltage corresponding to the tone value of the data. The multiplexer 43 alternately selects the positive gamma compensation voltage and the negative gamma compensation voltage in response to the polarity control signal POL and outputs the selected positive / negative gamma compensation voltage as an analog data voltage. The charge share circuit 36 shorts neighboring data output channels during the high logic period of the source output enable signal SOE to output an average value of neighboring data voltages, The common voltage Vcom is supplied to the data output channels during the high logic period to reduce a sharp change in the positive polarity data voltage and the negative polarity data voltage. The output circuit 37 includes a buffer to minimize signal attenuation of the analog data voltage supplied to the data lines D1 to Dk.

FIG. 5 is a waveform diagram showing an example of a data voltage generated according to a polarity control signal POL during a first frame period, and FIG. 6 is a diagram showing data polarity charged in a liquid crystal cell. In this embodiment, the polarity of the data voltage charged in each of the liquid crystal cells is repeated in a set of two lines (k + 1, k + 2th lines), so that the following description is limited to these two lines.

The data driving circuit 103 sequentially supplies the positive polarity data voltage + to the first data line Di and the fourth data line Di + 3 for one frame in response to the polarity control signal POL. The data driving circuit 103 sequentially supplies the data to the second data line Di + 1 and the third data line Di + 2 in response to the polarity control signal POL. The gate driving circuit 104 sequentially generates gate pulses of one horizontal period synchronized with the positive / negative polarity data voltages.

The first TFT T1 applies a data voltage from the first data line Di to the pixel electrode of the first liquid crystal cell in response to the first gate pulse supplied to the odd gate lines Gn, Gn + 2, Supply. Thus, the first liquid crystal cell is charged with the positive polarity data voltage.

The second TFT T2 applies a data voltage from the second data line Di + 1 to the pixels of the second liquid crystal cell in response to the first gate pulse supplied to the odd gate lines Gn, Gn + 2, To the electrode. Whereby the second liquid crystal cell is charged with the negative data voltage.

The third TFT T3 supplies the data voltage from the second data line Di to the pixels of the third liquid crystal cell in response to the second gate pulse supplied to the even gate lines Gn + 1, Gn + 3, To the electrode. As a result, the third liquid crystal cell is charged with the negative data voltage.

The fourth TFT T4 supplies the data voltage from the first data line Di to the pixels of the fourth liquid crystal cell in response to the second gate pulse supplied to the even gate lines Gn + 1, Gn + 3, To the electrode. Thus, the fourth liquid crystal cell is charged with the positive polarity data voltage.

The data voltage supplied to the third data line Di + 2 is opposite to the data voltage supplied to the first data line Di, and the data voltage supplied to the fourth data line Di + 3 is 2 Th data line Di + 1. Accordingly, the liquid crystal cells arranged in the (k + 2) -th line are charged with the data voltages which are opposite in phase to the data voltages of the liquid crystal cells arranged in the (k + 1) th line.

As described above, in this embodiment, the liquid crystal cells are inversion in the column direction (or in the gate line direction) by one dot, and two-dot in the line direction (or data line direction) Inversion.

On the other hand, in the liquid crystal display panel having the pixel array as shown in Fig. 2, the stain due to the parasitic capacitance of the conventional TFT occurs in the form of a line, which is problematic for the eyes of the viewer. However, When the bottom spot is in the form of a 2-dot spot, the level of the spot can be significantly reduced.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (5)

M × n liquid crystal cells arranged in a matrix form by an intersection structure of m data lines in the horizontal direction and n gate lines in the vertical direction and a liquid crystal layer formed between the upper substrate and the lower substrate, A liquid crystal display panel including TFTs connected to cells;
A data driving circuit for supplying a data voltage to the data lines in response to a polarity control signal;
And a gate driving circuit for supplying the gate lines,
The liquid crystal cells,
A first liquid crystal cell disposed on the left side of the first gate line, a second liquid crystal cell disposed on the right side of the first gate line, a third liquid crystal cell disposed on the left side of the second gate line, And a fourth liquid crystal cell disposed on the right side,
The TFTs,
A first TFT for charging a data voltage from a first data line into the first liquid crystal cell in response to a first gate pulse supplied to the first gate line,
A second TFT for charging the second liquid crystal cell with a data voltage from a second data line in response to a first gate pulse supplied to the first gate line,
A third TFT for charging a data voltage from the second data line into the third liquid crystal cell in response to a second gate pulse supplied to the second gate line,
A fourth TFT for charging a data voltage from the first data line to the fourth liquid crystal cell in response to a second gate pulse supplied to the second gate line,
And the liquid crystal display device.
The method according to claim 1,
And a data voltage of a first polarity is applied to the first data line during one frame.
3. The method of claim 2,
And a data voltage having a phase opposite to the first polarity is applied to the second data line during one frame.
The method according to claim 1,
Wherein the first gate pulse occurs during one horizontal period (1H)
Wherein the first liquid crystal cell and the second liquid crystal cell are charged during the one horizontal period.
5. The method of claim 4,
Wherein the second gate pulse occurs during one horizontal period (1H)
And the third liquid crystal cell and the fourth liquid crystal cell are charged during the one horizontal period (1H).

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