KR101604481B1 - Liquid crystal display - Google Patents

Abstract

The present invention relates to a liquid crystal display device, in which a liquid crystal layer is formed between an upper substrate and a lower substrate, and m (m is a positive integer) / 2 data lines and 2n (n is a positive integer) A liquid crystal display panel including mxn liquid crystal cells arranged in a matrix by a cross structure and TFTs connected to the liquid crystal cells; A data driving circuit for supplying a data voltage to the data lines in response to a polarity control signal; A gate driving circuit for supplying the gate lines; A POL control circuit for controlling the phase of the polarity control signal differently for each frame period; And a data modulation circuit for down-modulating the gray level of the digital video data corresponding to the second data voltage among the data voltages of the same polarity to be continuously charged in the liquid crystal cells existing in the neighboring lines of the liquid crystal display panel do.

Description

[0001] LIQUID CRYSTAL DISPLAY [0002]

The present invention relates to a liquid crystal display device capable of reducing the number of data lines and improving display quality.

A liquid crystal display device of an active matrix driving type displays a moving picture by using a thin film transistor (hereinafter referred to as "TFT") as a switching element. This liquid crystal display device can be downsized as compared with a cathode ray tube (CRT), and is applied to a display device in a portable information device, an office machine, a computer, etc., and is also applied to a television, thereby quickly replacing a cathode ray tube.

In order to reduce the DC offset component and reduce the deterioration of the liquid crystal, the liquid crystal display device is driven by an inversion in which the polarity is inverted between neighboring liquid crystal cells and the polarity is inverted every frame period. However, when either polarity of the two polarities of the data voltage is supplied dominantly for a long time, a residual image occurs. This residual image is referred to as "DC Image sticking" because a voltage of the same polarity is repeatedly charged in the liquid crystal cell. One of these examples is when interlaced data voltages are supplied to the liquid crystal display device. The interlace method includes only the data voltage to be displayed in the liquid crystal cells of the odd horizontal line in the odd frame period and only the data voltage to be displayed in the liquid crystal cells of the even horizontal line in the even frame period. As another example of the DC image remnant image, when the same image is moved or scrolled at a constant speed, a voltage of the same polarity is repeatedly accumulated in the liquid crystal cell according to the correlation between the size of the scrolling picture and the scroll speed (moving speed) DC after-image can appear. Korean Patent Application No. 10-2007-035126 (2007.04.10), Korean Patent Application No. 10-2007-0004251 (Jan. 15, 2007), Korean Patent Application No. 10-2007-0004246 (January 15, 2007), Korea Patent Application No. 10-2007-0008895 (2007.01.29), Korean Patent Application No. 10-2007-0037936 (2007.04.18), Korean Patent Application No. 10-2007-0047787 (May 16, 2007), Korean Patent Application No. 10- Korean Patent Application No. 10-2007-0052679 (2007.05.30), Korean Patent Application No. 10-2007-0062238 (2007.06.25), Korean Patent Application No. 10-2006-0064561 (2007.06.01) 28, 2007), US application 12 / 003,585 (2007.12.28), US application 12 / 003,666 (Dec. 28, 2007), US application 12 / 003,746 (Dec. 31, 2007) .

In order to reduce the circuit cost of the liquid crystal display device, a panel structure (hereinafter referred to as " panel structure ") is proposed in which adjacent thin film transistors (TFTs) on the same display line are connected to the same data lines to reduce data lines and reduce the number of output channels , "DRD (Double rate Driving) panel") are being developed. Experiments using the above-described polarity control scheme in such a liquid crystal display device show that 30 Hz flicker, flicker in the line direction, flicker in the column direction, and color distortion in which any one of R, G, and B colors are strongly visible. Therefore, a technique capable of reducing afterglow after-image, flicker, color distortion, and the like is also demanded in a liquid crystal display device to which a DRD panel is applied.

It is an object of the present invention to provide a liquid crystal display device capable of reducing the number of data lines and improving display quality.

In order to achieve the above object, a liquid crystal display device of the present invention includes a liquid crystal layer formed between an upper substrate and a lower substrate, and m (m is a positive integer) / 2 data lines and 2n (n is a positive integer) A liquid crystal display panel including mxn liquid crystal cells arranged in a matrix by a crossing structure of gate lines and TFTs connected to the liquid crystal cells; A data driving circuit for supplying a data voltage to the data lines in response to a polarity control signal; A gate driving circuit for supplying the gate lines; A POL control circuit for controlling the phase of the polarity control signal differently for each frame period; And a data modulation circuit for down-modulating the gray level of the digital video data corresponding to the second data voltage among the data voltages of the same polarity to be continuously charged in the liquid crystal cells existing in the neighboring lines of the liquid crystal display panel do.

The present invention can optimize the pixel array structure of the DRD panel to reduce the number of output channels of the data lines and the data driving circuit to 1/2 or less, minimize DC after-image, flicker, and color distortion, The quality can be improved. Further, when the polarities of the data voltages to be charged in the liquid crystal cells of the neighboring lines in the liquid crystal display panel are the same, the gray level of the digital video data corresponding to the second data voltage is down-modulated by a predetermined modulation width Overcharge can be prevented.

Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS. 1 to 18. FIG.

1 and 2, a liquid crystal display according to an embodiment of the present invention includes a liquid crystal display panel 100, a timing i controller 101, a POL and a data modulation logic circuit 102, a data driving circuit 103, , And a gate driving circuit (104).

The liquid crystal display panel 100 includes an upper glass substrate and a lower glass substrate opposed to each other with a liquid crystal layer interposed therebetween. The liquid crystal display panel 100 includes a pixel array 10 for displaying video data. The pixel array 10 is formed by the intersection structure of m (m is a positive integer) / 2 data lines D1 to Dm / 2 and 2n (n is a positive integer) gate lines G1 to G2n And m x n liquid crystal cells Clc arranged in a matrix form. The m x n liquid crystal cells Clc include m columns (or vertical display lines) in which the liquid crystal cells Clc are arranged in the data line direction and n columns in which the liquid crystal cells Clc are arranged in the gate line direction Lines (or horizontal display lines). The liquid crystal cells Clc of the pixel array 10 are connected to the electric field generated by the voltage difference between the data voltage supplied to the pixel electrode 1 through the TFT and the common voltage Vcom supplied to the common electrode 2 The data voltage is charged and the data voltage is maintained for a predetermined period by the storage capacitor Cst to display an image.

The pixel array 10 includes m / 2 data lines D1 to Dm / 2, 2n gate lines G1 to G2n, mxn pixel electrodes 1, M × n TFTs connected to the pixel electrodes 1, and m × n storage capacitors connected to the pixel electrodes 1. The TFTs adjacent to the left and right in the same line are connected to the same data line. Such a connection structure of the TFT and the data line is shown in Fig. A gate driving circuit 104 connected directly to the gate lines G1 to G2n may be directly formed on the non-display surface outside the pixel array 10 on the lower glass substrate of the liquid crystal display panel 100. [ In this case, the pixel array 10 and the gate drive circuit 104 are simultaneously formed on the lower glass substrate of the liquid crystal display panel 100 by the same thin film process.

On the upper glass substrate of the liquid crystal display panel 100, a black matrix, a color filter, and a common electrode are formed. The common electrode is formed on the upper glass substrate in a vertical electric field driving method such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode, and a horizontal electric field such as IPS (In Plane Switching) mode and FFS (Fringe Field Switching) Is formed on the lower glass substrate together with the pixel electrode 1 in the driving method.

On the upper glass substrate and the lower glass substrate of the liquid crystal display panel 100, a polarizing plate is attached and an alignment film for setting a pre-tilt angle of the liquid crystal is formed.

The liquid crystal mode of the liquid crystal display panel 100 applicable to the present invention may be implemented in any liquid crystal mode as well as the TN mode, VA mode, IPS mode, and FFS mode described above. Further, the liquid crystal display device of the present invention can be implemented in any form such as a transmissive liquid crystal display device, a transflective liquid crystal display device, a reflective liquid crystal display device, and the like. In a transmissive liquid crystal display device and a transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as an edge type backlight unit or a direct type backlight unit. The edge type backlight unit has a structure in which a light source is disposed so as to face the side face of the light guide plate and a plurality of optical sheets are disposed between the liquid crystal display panel and the light guide plate. The direct type backlight unit has a structure in which the optical sheets and the diffusion plate are stacked under the liquid crystal display panel 100 and a plurality of light sources are disposed under the diffusion plate. The light source of the backlight unit may include at least one of a hot cathode fluorescent lamp (HCFL), a cold cathode fluorescent lamp (CCFL), an external electro fluorescent lamp (EEFL), and a light emitting diode (LED).

The liquid crystal cell Clc and the TFT disposed on the left side of the odd data lines D1, D3, ... Dm / 2-1 are respectively connected to the first liquid crystal cell and the first TFT T1 and the odd data lines D1, The liquid crystal cell Clc and the TFT disposed on the right side of the first liquid crystal cell and the second TFT T2 are respectively connected to the even data lines D2, D4, ..., Dm The liquid crystal cell Clc and the TFT disposed on the left side of the odd data lines D2, D4, ..., Dm / 2 are arranged in the third liquid crystal cell and the third TF (T3) The liquid crystal cell Clc and the TFT are defined as a fourth liquid crystal cell and a fourth TFT T4, respectively.

The first TFT T1 is turned off from the odd data lines D1, D3 ... Dm / 2-1 in response to gate pulses (or scan pulses) from the odd gate lines G1, G3 ... G2n- To the pixel electrode (1) of the first liquid crystal cell (Clc). The gate electrode of the first TFT T1 is connected to the odd gate lines G1, G3 ... G2n-1 and the drain electrode is connected to the odd data lines D1, D3 ... Dm / 2-1. Respectively. The source electrode of the first TFT (T1) is connected to the pixel electrode (1) of the first liquid crystal cell (Clc). The second TFT T2 applies a data voltage from the odd data lines D1, D3, ..., Dm / 2-1 in response to the gate pulse from the even gate lines G2, G4, To the pixel electrode (1) of the cell (Clc). The gate electrode of the second TFT T2 is connected to the even gate lines G2, G4 ... G2n and the drain electrode is connected to the odd data lines D1, D3 ... Dm / 2-1 do. And the source electrode of the second TFT T2 is connected to the pixel electrode 1 of the second liquid crystal cell Clc. The third TFT T3 supplies the data voltages from the even-numbered data lines D2, D4, ..., Dm / 2 to the third liquid-crystal cell (the odd-numbered data lines) in response to the gate pulse from the even-numbered gate lines G2, G4, Clc) to the pixel electrode (1). The gate electrode of the third TFT T3 is connected to the even gate lines G2, G4 ... G2n and the drain electrode is connected to the even data lines D2, D4 ... Dm / 2. The source electrode of the third TFT T3 is connected to the pixel electrode 1 of the third liquid crystal cell Clc. The fourth TFT T4 supplies the data voltages from the even-numbered data lines D2, D4, ..., Dm / 2 to the fourth liquid crystal display panel in response to gate pulses from the odd-numbered gate lines G1, G3 ... G2n- To the pixel electrode (1) of the cell (Clc). To this end, the gate electrode of the fourth TFT T4 is connected to the odd gate lines G1, G3 ... G2n-1 and the drain electrode is connected to the even data lines D2, D4 ... Dm / 2 do. The source electrode of the fourth TFT T4 is connected to the pixel electrode 1 of the fourth liquid crystal cell Clc.

The data of the liquid crystal cells connected to the odd data lines D1, D3, ..., Dm / 2-1 in accordance with the connection relationship between the TFTs T1 to T4 and the data lines D1 to Dm / The charging order and the data charging order of the liquid crystal cells connected to the superior data lines D1, D3, ..., Dm / 2-1 are reversed. In other words, the data charging sequence CS1 of the liquid crystal cells connected to the odd data lines D1, D3, ..., Dm / 2-1 and the data charging sequence CS1 of the even data lines D1, The data filling order CS2 of the liquid crystal cells connected to the data lines Dm / 2-1 is symmetrical.

When the data voltages are supplied to the data lines D1 to Dm / 2 and the gate pulses synchronized with the data voltages are sequentially supplied to the gate lines G1 to G2n, the odd data lines D1, D3, ..., The liquid crystal cells of the (4i + 2) -th column and the liquid crystal cells of the column 4i (i is a positive integer) disposed on the left and right of the Dm / 2-1 column have a "Z" And sequentially charges the data voltage along the data line CS1. That is, after the first liquid crystal cell of the (4i + 1) th column existing on the i-th line charges the data voltage, the second liquid crystal cell of the 4i + 2th column located on the right side of the first liquid crystal cell in the i- Charge the data voltage. Next, after the first liquid crystal cell of the (4i + 1) -th column existing in the (i + 1) -th line is charged with the data voltage, the data of the (4i + 2) -th column located on the right side of the first liquid crystal cell in the 2 liquid crystal cell charges the data voltage.

When the data voltages are supplied to the data lines D1 to Dm / 2 and gate pulses synchronized with the data voltages are sequentially supplied to the gate lines G1 to G2n, the data lines D2, D4, ..., The liquid crystal cells of the (4i + 3) -th column and the liquid crystal cells of the (4i + 4) -th column arranged on the left and right of the data line Dm / Charge sequentially. That is, after the fourth liquid crystal cell of the (4i + 4) th column existing on the i-th line charges the data voltage, the third liquid crystal cell of the 4i + 3th column located on the left side of the fourth liquid crystal cell on the i- Charge the data voltage. Next, after the fourth liquid crystal cell of the (4i + 4) th column existing in the (i + 1) th line charges the data voltage, the data of the (4i + 3) th column located on the left of the fourth liquid crystal cell in the 3 liquid crystal cell charges the data voltage.

The timing controller 101 receives timing signals such as a vertical / horizontal synchronizing signal (Vsync, Hsync), a data enable signal and a clock signal (CLK) from the system board 105 and supplies the timing signal to the data driving circuit 103 The gate driving circuit 104, and the POL and the data modulation logic circuit 102. The control signal is used to control the operation timing of the gate driving circuit 104, The timing controller 101 supplies the RGB digital video data to the POL and the data modulation logic circuit 102. The timing controller 101 generates a data timing control signal for controlling the data driving circuit 103 and a gate timing control signal for controlling the gate driving circuits 104 using the timing signal. The timing controller controls the timing controller 14 so that the digital video data input at a frame frequency of 60 Hz can be reproduced in the pixel array 10 of the liquid crystal display panel at a frame frequency of 60 x i (i is a positive integer of 2 or more) And the frequency of the data timing control signal can be multiplied by a frame frequency reference of 60 x i Hz. The control signals output from the timing controller 101 include a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable (GOE), a source start pulse (SSP), a source sampling clock (SSC), a source output enable (SOE) signal, and a reference polarity control signal (POL). The gate start pulse (GSP) indicates a starting horizontal line at which the scanning starts from one vertical period in which one screen is displayed. The gate shift clock signal GSC is input to the shift register in the gate drive circuit and is a timing control signal for sequentially shifting the gate start pulse GSP. The gate shift clock signal GSC is generated with a pulse width corresponding to the ON period of the TFT. The gate output enable signal GOE indicates the output of the gate drive circuit 104. [ The source start pulse SSP indicates a starting pixel in one horizontal line where data is to be displayed. The source sampling clock SSC instructs the latch operation of data in the data driving circuit 103 on the basis of the rising or falling edge. The source output enable signal (SOE) indicates the output of the data driving circuit 103. The reference polarity control signal POL indicates the polarity of the data voltage to be supplied to the liquid crystal cells Clc of the liquid crystal display panel 100. The reference polarity control signal POL is logic inverted to i horizontal period period. The source start pulse SSP and the source sampling clock SSC may be omitted if data is transmitted from the timing controller 101 to the data driving circuit 103 through the mini LVDS interface.

The POL and the data modulation logic circuit 102 receive the gate start pulse GSP, the source output enable signal SOE and the reference polarity control signal POL to prevent the afterimage and the flicker, To the fourth polarity control signals POL1 to POL4 sequentially. The POL and data modulation logic circuit 102 may optionally output the same reference polarity control signal POL every frame. Further, the POL and the data modulation logic circuit 102 modulate the gray level of the digital video data corresponding to the second data voltage among the data voltages of the same polarity to be sequentially charged in the diagonally adjacent liquid crystal cells. The POL and the data modulation logic circuit 102 supply the data driving circuit 103 with the polarity control signals POL1 to POL4 and the modulated digital video data RGB '.

The data driving circuit 103 latches the digital video data RGB 'modulated by the POL and the data modulation logic circuit 102 under the control of the timing controller 101. The data driving circuit 103 converts the latched digital video data into analog positive / negative gamma compensation voltages in response to the polarity control signals POL / POL1 through POL4 from the timing controller 101 to generate positive / negative polarity Thereby generating a data voltage. The data driving circuit 103 supplies the positive polarity / negative polarity data voltages to the data lines D1 to Dm / 2.

The gate driver circuit 104 includes a level shifter for converting the output signal of the shift register and the shift register into a swing width suitable for driving the TFT of the liquid crystal cell, and an output buffer connected between the level shifter and the gate lines G1 to G2n And a plurality of gate drive ICs. The gate drive circuit 104 sequentially outputs gate pulses having a pulse width of about 1/2 horizontal period synchronized with the positive / negative polarity data voltages.

The POL and the data modulation logic circuit 102 may be embedded in the source drive ICs of the timing controller 101 or the data drive circuit 103. [

The system board 105 includes a broadcast signal receiving circuit, an external device interface circuit, a graphic processing circuit, a memory, and the like. The system board 105 extracts video data from a broadcast signal or an image source input from an external device, converts the video data into digital data, To the controller (101). The interlaced broadcast signal received by the system board 105 exists only in the odd line in the odd frame period and exists only in the odd line in the odd frame period. Upon receiving the interlaced broadcast signal, the system board 105 generates the odd line data of the odd frame period and the odd line data of the odd frame by the average value or the black data value of the data stored in the memory. The system board 105 supplies timing signals Vsync, Hsync, DE, and CLK to the timing controller 101 together with digital video data RGB and supplies the power to a module power circuit not shown. The module power supply circuit adjusts a voltage supplied from the system board 105 to generate a voltage required for driving the digital circuits of the module and a driving voltage of the liquid crystal display panel.

3 and 4 are circuit diagrams showing the source drive IC of the data driving circuit 103 in detail.

Referring to FIGS. 3 and 4, each of the source drive ICs supplies a data voltage to k (k is an integer smaller than m / 2) data lines D1 to Dk. Each of the source drive ICs includes a shift register 31, a data register 32, a first latch 33, a second latch 34, a digital / analog converter (hereinafter referred to as DAC) 35, A Charge Share Circuit 36 and an output circuit 37. [ The shift register 31 generates a sampling clock from the timing controller 101 and transfers the carry signal CAR to the shift register 31 of the next source drive IC. The data register 32 temporarily stores the odd digital video data RGBodd and the excellent digital video data RGBeven separated by the timing controller 101 and stores the stored data RGBodd and RGBeven in the first latch 33 Supply. The first latch 33 samples the digital video data RGBeven and RGBodd from the data register 32 in response to a sampling signal sequentially input from the shift register 31 and supplies the data RGBeven and RGBodd ), And then outputs the latched data at the same time. The second latch 34 latches the data input from the first latch 33 and then latches the digital data latched simultaneously with the second latch 34 of the other integrated circuits during the low logic period of the source output enable signal SOE. Simultaneously output video data. The DAC 35 includes a P-decoder (PDEC) 41 to which a positive gamma reference voltage GH is supplied, an N-decoder (NDEC) 42 to which a negative gamma reference voltage GL is supplied, And a multiplexer 43 for selecting the output of the P-decoder 41 and the output of the N-decoder 42 in response to the polarity control signals POL / POL1 to POL4. The P-decoder 41 decodes the digital video data input from the second latch 34 and outputs a positive gamma compensation voltage corresponding to the gray level value of the data, and the N-decoder 42 outputs the positive gamma compensation voltage to the second latch 34, and outputs a negative gamma compensation voltage corresponding to the tone value of the data. The multiplexer 43 alternately selects a positive gamma compensation voltage and a negative polarity gamma compensation voltage in response to the polarity control signals POL / POL1 through POL4, and outputs the selected positive / negative gamma compensation voltage as an analog data voltage do. The charge share circuit 36 shorts neighboring data output channels during the high logic period of the source output enable signal SOE to output an average value of neighboring data voltages, The common voltage Vcom is supplied to the data output channels during the high logic period to reduce a sharp change in the positive polarity data voltage and the negative polarity data voltage. The output circuit 37 includes a buffer to minimize signal attenuation of the analog data voltage supplied to the data lines D1 to Dk.

Figures 5 and 6 are circuit diagrams detailing the POL and data modulation logic circuit 102. 7 is a waveform diagram showing the first to fourth polarity control signals POL1 to POL4 sequentially output from the POL and the data modulation logic circuit 102. In FIG.

5 and 7, the POL and data modulation logic circuit 102 includes a frame counter 51, a line counter 52, a POL generating circuit 53, a multiplexer 54, and a data modulator 55, Respectively.

The frame counter 51 counts gate start pulses (GSP) that are generated once in one frame period and are generated at the same time as the start of one frame period and counts a frame count indicating the number of frames of an image to be displayed on the liquid crystal display panel 100 And outputs information Fcnt. The line counter 52 counts the clocks of the source output enable signal SOE or the gate output enable signal GOE having a period of approximately a 1/2 horizontal period to generate a horizontal line to be displayed on the liquid crystal display panel 100 And outputs the line count information Lcnt to be instructed. It is possible to use a clock generated from the internal oscillator of the timing controller 101 as a timing signal supplied to the frame counter 51 and the line counter 52. However, since this clock has a high frequency, the timing controller 101, The electromagnetic interference (EMI) can be increased between the data modulation logic circuits 102. A gate start pulse GSP and a source output enable signal SOE having a frequency smaller than the clock generated by the internal oscillator of the timing controller 101 are input to the frame counter 51 and the line counter 52 The EMI increase between the timing controller 101 and the POL and the data modulation logic circuit 102 can be reduced.

The POL generating circuit 53 includes a first POL generating circuit 61, a second POL generating circuit 62, first and second inverters 63 and 64, and a multiplexer 65. The first POL generating circuit 61 toggles the output signal in accordance with the line counter information Lcnt so as to control the polarity of the data voltage charged in the liquid crystal cells Clc during the first frame period, And generates the polarity control signal POL1. The first polarity control signal POL1 includes a high logic (+) in a 1/2 horizontal period (1/2 H), a low logic (-) in a 1/2 horizontal period (1/2 H) (+) Of one horizontal period (1/2 H), low logic (-) of one horizontal period (1H), high logic (+) of a 1/2 horizontal period (1/2 H) The logic is inverted in the high logic (+) order of the low logic (-) and the 1/2 horizontal period (1/2 H). The first inverter 63 inverts the first polarity control signal POL1 to generate a third polarity control signal CLK for controlling the polarity of the data voltage charged in the liquid crystal cells Clc during the third frame period as shown in FIG. POL3). The second POL generating circuit 62 toggles the output signal in accordance with the line counter information Lcnt to control the polarity of the data voltage charged in the liquid crystal cells Clc during the second frame period, And generates the polarity control signal POL2. The second polarity control signal POL2 includes a high logic (+) in a 1/2 horizontal period (1/2 H), a low logic (-) in a 1 horizontal period (1H), a 1/2 horizontal period (+) Of one horizontal period (1H), low logic (-) of a half horizontal period (1/2 H), high logic (+) of one horizontal period (1H) The logic is inverted in the order of the low logic (-) of FIG. The second inverter 64 inverts the second polarity control signal POL2 to generate a fourth polarity control signal CLK for controlling the polarity of the data voltage charged in the liquid crystal cells Clc during the fourth frame period as shown in FIG. POL4).

The multiplexer 65 outputs the first polarity control signal POL1 during the (4i + 1) -th frame period in accordance with the frame count information Fcnt, and then outputs the second polarity control signal POL2 during the And then outputs the third polarity control signal POL3 during the (4i + 3) -th frame period. Then, the multiplexer 65 outputs the fourth polarity control signal POL4 during the (4i + 4) -th frame period.

The multiplexer 54 selects the polarity control signals POL1 to POL4 from the POL generating circuit 53 according to the voltage of the control terminal connected to the POL and the option pin of the data modulation logic circuit 102 or the selection control signal SEL, Or selects the reference polarity control signal POL. The POL and optional pins of the data modulation logic circuit 102 are connected to the control terminal of the multiplexer 54. [ The ground voltage (GND) or the power supply voltage (Vcc) may be selectively applied to the option pins of the POL and the data modulation logic circuit 102. When a ground voltage GND is applied to the POL and the option pin of the data modulation logic circuit 102, a logic low voltage is applied to the control terminal of the multiplexer 54 so that the multiplexer 54 outputs the reference polarity control signal POL Output. On the other hand, when the power supply voltage Vcc is applied to the POL and the option pin of the data modulation logic circuit 102, a high logic voltage is applied to the control terminal of the multiplexer 54 so that the multiplexer 54 outputs' 1 And outputs the polarity control signals POL1 to POL4 from the POL generating circuit 53. [ The selection control signal SEL may be automatically generated from the system board 105 or the timing controller 101 in accordance with a user selection signal input through the user interface or an analysis result of the data. Accordingly, the multiplexer 54 can operate according to the data analysis result or the user selection.

The data modulator 55 receives the frame count information Fcnt and the line count information Lcnt and outputs the frame count information Fcnt and the line count information Lcnt to the liquid crystal display And detects digital video data corresponding to a second data voltage among data voltages of the same polarity to be continuously charged in the cells. The data modulator 55 lowers the gradation of the digital video data corresponding to the second data voltage among the data voltages of the same polarity to be filled in the liquid crystal cells of the two neighboring lines by a predetermined modulation width, ').

8 is a circuit diagram showing the data modulator 55 in detail.

8, the data modulating section 55 includes an overcharge timing detecting section 551, a modulating section 552, and a multiplexer 553.

The overcharge timing detecting unit 551 receives the frame count information Fcnt and the line count information Lcnt and outputs the second data among the data voltages of the same polarity to be continuously charged in the i-th line and the (i + And detects digital video data corresponding to the voltage. 10 and 11, the overcharge timing detecting section 551 detects the overcharge timing of the (4i + 3) th and (4i + 3) th data lines among the data voltages of the same polarity to be continuously charged in the liquid crystal cells of the The digital video data of the data voltage to be charged in the liquid crystal cell of the line is detected. The overcharge timing detecting unit 551 detects the data to be charged in the liquid crystal cells of the (4i + 2) th line among the data voltages of the same polarity to be continuously charged in the liquid crystal cells of the 4i + 1 and 4i + Digital video data of the voltage is detected.

The modulation unit 552 modulates the gray level value of the digital video data RGB by using a memory, for example, an EEPROM (Electrically Erasable Programmable Read-Only Memory) storing a lookup table in which the modulation values of the digital video data RGB are set. Down modulation to the set modulation value. The modulation value can be optimized in the following manner. In an experiment in which data voltages of the same polarity continuously supplied through the same data line are sequentially charged into the liquid crystal cells of neighboring lines, an overcharge amount of the second data voltage is detected and then an overcharge amount of the second data voltage The process of lowering the gradation of the digital video data is repeated so that the amount is lowered. The modulation value can be set to a gray level value when the overcharge amount becomes small within an allowable range by such an experiment, the modulation value is a sum of the data voltages to be continuously charged in the liquid crystal cells of the neighboring lines, And may be set differently depending on the value of the data voltage.

The multiplexer 553 selects the second data voltage among the data voltages to be continuously charged in the liquid crystal cells of the neighboring lines in the liquid crystal display panel according to the selection signal SEL2 from the overcharge timing detection unit 551, And selects the data (RGB ') as the output of the modulating unit 552. The multiplexer 553 multiplexes the digital video data RGB corresponding to the data voltages other than the second data voltage among the data voltages to be continuously charged in the liquid crystal cells of the neighboring lines to the modulator 552 (RGB) that has not been passed, that is, unmodulated input data. The digital video data RGB 'generated from the multiplexer 553 is supplied to the data driving circuit 103.

9 is a waveform diagram showing an example of a data voltage generated according to a first polarity control signal POL1 during a first frame period. FIGS. 10 and 11 are diagrams showing polarity changes of the data voltages depending on the first to fourth polarity control signals POL1 to POL4 during the first to fourth frame periods.

9 to 10, the data driving circuit 103 generates positive polarity data voltages (+ R, + G, + B) and negative polarity data voltages (-R, -G, -B), the positive polarity data voltages (+ R, + G, + B), the negative polarity data voltages (-R, ), The positive polarity data voltages (+ R, + G, + B), the negative polarity data voltages (-R, -G, To the odd data lines D1, D3, ..., Dm / 2-1 in sequence. In response to the first polarity control signal POL1, the data driving circuit 103 generates a polarity opposite to the polarity of the data voltage supplied to the odd data lines D1, D3, ..., Dm / 2-1 And supplies the data voltages to the even data lines D2, D4, ..., Dm / 2 in sequence. The gate drive circuit 104 sequentially generates gate pulses of approximately one-half horizontal period synchronized with the positive / negative data voltages.

The first TFT T1 supplies data from the odd data lines D1, D3, ..., Dm / 2-1 in response to the first gate pulse supplied to the odd gate lines G1, G3 ... G2n- Voltage is supplied to the pixel electrode of the first liquid crystal cell. The second TFT T2 applies a data voltage from the odd data lines D1, D3, ..., Dm / 2-1 in response to the second gate pulse supplied to the even gate lines G2, G4 ... G2n To the pixel electrodes of the second liquid crystal cell. The third TFT T3 supplies a data voltage from the even data lines D2, D4, ..., Dm / 2 to the pixel electrodes of the third liquid crystal cell in response to the second gate pulse. The fourth TFT T4 supplies a data voltage from the even data lines D2, D4, ..., Dm / 2 to the pixel electrodes of the fourth liquid crystal cell in response to the first gate pulse.

As shown in FIGS. 10 and 11, the liquid crystal cells are charged with a data voltage whose polarity is controlled according to the first to fourth polarity control signals POL1 to POL4, thereby generating an image having no DC after-image, flicker, Can be displayed. The polarity of the data voltage indicated by circles in Figs. 10 and 11 is the polarity of the second data voltage among the data voltages to be continuously charged in the liquid crystal cells of the neighboring lines in the liquid crystal display panel 100. [ Immediately after the positive polarity data voltage is supplied to the data lines D1 to Dm / 2 in order to supply the liquid crystal cells with data voltages to be continuously charged in the liquid crystal cells of neighboring lines in the liquid crystal display panel 100 Another negative polarity data voltage may be supplied to the second polarity data voltage, or another polarity data voltage may be supplied immediately after the negative polarity data voltage is supplied. When a second data voltage is supplied to the data line, the voltages of the data lines D1 to Dm / 2 are set such that the first data voltage is charged and the second data voltage of the same polarity is charged And is overcharged. Therefore, the luminance of the liquid crystal cell that charges the second data voltage among the liquid crystal cells of the neighboring lines that continuously charge the data voltages of the same polarity is higher than the luminance of the liquid crystal cell that charges the first data voltage due to overcharging. The present invention modulates the tone value of the digital video data corresponding to the second data voltage among the data voltages of the same polarity to be continuously charged in the liquid crystal cells of the neighboring lines by a predetermined modulation width as shown in FIG. The overcharge phenomenon of the voltage can be prevented.

The interlaced afterimage improving effect and flicker improving effect of the present invention will be described with reference to Figs. 14 to 16. Fig.

It is assumed that the interlace data is displayed on the liquid crystal display panel and the polarity of the data voltage charged in all the liquid crystal cells Clc is reversed every frame as in the conventional method. In this case, the positive polarity voltage is supplied to the liquid crystal cell Clc during the odd frame period, and the negative voltage is supplied during the excellent frame period. In the interlaced method, since the positive polarity data voltage is supplied only to the liquid crystal cell Clc during the odd frame period, the positive polarity data voltage charge amount Lc of the liquid crystal cell Clc as the waveform in the box during the first to fourth frame periods Is much larger than the charge amount of the negative polarity data voltage. Therefore, if the polarity of the data voltage charged in all of the liquid crystal cells Clc is inverted every frame and the interlaced data is input to the liquid crystal display device, the afterglow and flicker are generated due to polarity bias of the data voltage charged in the liquid crystal cell.

The present invention can improve DC afterimage, flicker, and color distortion by controlling the polarity of a data voltage in a DRD panel using first to fourth polarity control signals POL1 to POL4 having different phases. The first to fourth polarity control signals POL1 to POL4 shift the polarity inversion periods of the data voltages charged in the arbitrary hatched liquid crystal cell and the neighboring liquid crystal cells from each other as shown in Fig. For example, in FIG. 15, the polarity of the data voltage charged in the shaded liquid crystal cell remains the same for two frame periods, while the polarity of the data voltage charged in the liquid crystal cell shaded and the neighboring liquid crystal cell for the same two- And is inverted in the second frame period. The shaded liquid crystal cell is charged with a data voltage of the same polarity during the two-frame period to prevent a DC after-image, and the polarity of the other liquid crystal cell adjacent to the shaded liquid crystal cell is inverted once for the same two- Thereby preventing a flicker phenomenon. The preventive effect of the DC after-image due to the shaded liquid crystal cell is shown in FIG. When the interlaced data is displayed on the liquid crystal display, the polarity of the data voltage charged in the shaded liquid crystal cell is inverted at a period of two frames. As a result, there is no large difference between the charged amount of the positive polarity data voltage charged in the shaded liquid crystal cell and the charged polarity of the negative polarity data, so that the polarized voltage polarized in the shaded liquid crystal cell is not accumulated. Therefore, even when the liquid crystal display device of the present invention displays interlaced data, since a voltage having a dominant polarity is not charged by the shaded liquid crystal cell, the afterglow after-image disappears.

A shaded liquid crystal cell can prevent a DC after-image, but flicker may appear because data voltages of the same polarity are supplied at a period of two frames. When a data voltage of the same polarity is charged in the shaded liquid crystal cell, the liquid crystal cell with the shaded liquid crystal cell accelerates the spatial frequency by charging the data voltage of the opposite polarity to that of the previous frame. As a result, the observer hardly senses flicker when observing the liquid crystal display of the present invention. This is because the human eye is sensitive to change. Therefore, when the observer sees the liquid crystal cell shaded and another liquid crystal cell adjacent thereto, the image is recognized at the data charging frequency of the liquid crystal cell adjacent to the shaded liquid crystal cell.

On the other hand, the DRD panel can be configured as shown in FIG. 17 or FIG.

Referring to Figure 18, the first TFT Tl is connected to the odd data lines D1, D3 ... Dm / 2-D in response to the first gate pulse from the odd gate lines G1, G3 ... G2n- 1 to the pixel electrodes of the first liquid crystal cell disposed on the left side of the odd data lines D1, D3 ... Dm / 2-1. The gate electrode of the first TFT T1 is connected to the odd gate lines G1, G3 ... G2n-1 and the drain electrode is connected to the odd data lines D1, D3 ... Dm / 2-1 . The source electrode of the first TFT (T1) is connected to the pixel electrode of the first liquid crystal cell. The second TFT T2 applies the data voltage from the odd data lines D1, D3 ... Dm / 2-1 in response to the second gate pulse from the even gate lines G2, G4 ... G2n To the pixel electrodes of the second liquid crystal cell disposed on the right side of the odd data lines D1, D3 ... Dm / 2-1. The gate electrode of the second TFT T2 is connected to the even gate lines G2, G4 ... G2n and the drain electrode thereof is connected to the odd data lines D1, D3 ... Dm / 2-1. The source electrode of the second TFT (T2) is connected to the pixel electrode of the second liquid crystal cell. The third TFT T3 supplies the data voltage from the even data lines D2, D4, ..., Dm / 2 in response to the first gate pulse from the odd gate lines G1, G3 ... G2n- To the pixel electrodes of the third liquid crystal cell arranged on the left side of the excellent data lines D2, D4 ... Dm / 2. The gate electrode of the third TFT T3 is connected to the odd gate lines G1, G3 ... G2n-1 and the drain electrode is connected to the even data lines D2, D4 ... Dm / 2. And the source electrode of the third TFT T3 is connected to the pixel electrode of the third liquid crystal cell. The fourth TFT T4 supplies the data voltage from the even data lines D2, D4, ..., Dm / 2 to the even data lines D2, D4, ..., Dm / 2 in response to the second gate pulse from the even gate lines G2, G4, To the pixel electrodes of the fourth liquid crystal cell arranged on the right side of the lines D2, D4 ... Dm / 2. The gate electrode of the fourth TFT T4 is connected to the even gate lines G2, G4 ... G2n and the drain electrode is connected to the even data lines D2, D4 ... Dm / 2. The source electrode of the fourth TFT T4 is connected to the pixel electrode of the fourth liquid crystal cell. In the DRD panel shown in Fig. 17, the liquid crystal cells sequentially charge the data voltage along the "Z" -shaped charge order CS2 in all column directions.

18, the first TFT T1 is connected to the (4i + 1) th data lines D1, D5, ..., Dm (D1, D5, ..., Dm) in response to the first gate pulse from the odd gate lines G1, G3 ... G2n- / 2-3 are supplied to the pixel electrodes of the first liquid crystal cell disposed on the left side of the (4i + 1) th data lines D1, D3, ..., Dm / 2-1. The gate electrode of the first TFT T1 is connected to the odd gate lines G1, G3 ... G2n-1 and the drain electrode is connected to the (4i + 1) th data lines D1, D5 ... Dm / Respectively. The source electrode of the first TFT (T1) is connected to the pixel electrode of the first liquid crystal cell. The second TFT T2 supplies data from the (4i + 1) th data lines D1, D5, ..., Dm / 2-3 in response to the second gate pulse from the even gate lines G2, G4, Voltage is supplied to the pixel electrode of the second liquid crystal cell disposed on the right side of the (4i + 1) -th data line (D1, D5 ... Dm / 2-3). The gate electrode of the second TFT T2 is connected to the even gate lines G2, G4 ... G2n and the drain electrode is connected to the (4i + 1) th data lines D1, D5 ... Dm / do. The source electrode of the second TFT (T2) is connected to the pixel electrode of the second liquid crystal cell. The third TFT T3 receives data from the (4i + 2) th data lines D2, D6, ..., Dm / 2-2 in response to the second gate pulse from the even gate lines G2, G4 ... G2n Voltage is supplied to the pixel electrodes of the third liquid crystal cell arranged on the left side of the (4i + 2) th data lines (D2, D6 ... Dm / 2-2). The gate electrode of the third TFT T3 is connected to the even gate lines G2, G4 ... G2n and the drain electrode is connected to the (4i + 2) th data lines D2, D6 ... Dm / do. And the source electrode of the third TFT T3 is connected to the pixel electrode of the third liquid crystal cell. The fourth TFT T4 is turned off from the (4i + 2) th data lines D2, D6 ... Dm / 2-2 in response to the first gate pulse from the odd gate lines G1, G3 ... G2n- To the pixel electrodes of the fourth liquid crystal cell arranged on the right side of the 4i + 2th data lines D2, D6 ... Dm / 2-2. The gate electrode of the fourth TFT T4 is connected to the odd gate lines G1, G3 ... G2n-1 and the drain electrode is connected to the (4i + 2) th data lines D2, D6 ... Dm / Respectively. The source electrode of the fourth TFT T4 is connected to the pixel electrode of the fourth liquid crystal cell. The fifth TFT T5 receives data from the (4i + 3) th data lines D3, D7, ..., Dm / 2-1 in response to the second gate pulse from the even gate lines G2, G4 ... G2n And supplies the voltage to the pixel electrode of the fifth liquid crystal cell disposed on the left side of the (4i + 3) th data line (D3, D7 ... Dm / 2-1). The gate electrode of the fifth TFT T5 is connected to the outermost gate lines G2, G4 ... G2n and the drain electrode is connected to the (4i + 3) th data lines D3, D7 ... Dm / 2-1 do. The source electrode of the fifth TFT (T5) is connected to the pixel electrode of the fifth liquid crystal cell. The sixth TFT T6 is turned off from the (4i + 3) th data lines D3, D7 ... Dm / 2-1 in response to the first gate pulse from the odd gate lines G1, G3 ... G2n- To the pixel electrodes of the sixth liquid crystal cell disposed on the right side of the (4i + 3) th data lines D3, D7 ... Dm / 2-1. The gate electrode of the sixth TFT T6 is connected to the odd gate lines G1, G3 ... G2n-1 and the drain electrode thereof is connected to the (4i + 3) th data lines D3, D7 ... Dm / Respectively. And the source electrode of the sixth TFT (T6) is connected to the pixel electrode of the sixth liquid crystal cell. The seventh TFT T7 receives data from the (4i + 4) th data lines D4, D8 ... Dm / 2 in response to the first gate pulse from the odd gate lines G1, G3 ... G2n- Voltage is supplied to the pixel electrodes of the seventh liquid crystal cell disposed on the left side of the 4i + 4th data lines D4, D8 ... Dm / 2. The gate electrode of the seventh TFT T7 is connected to the odd gate lines G1, G3 ... G2n-1 and the drain electrode is connected to the (4i + 4) th data lines D4, D8 ... Dm / do. The source electrode of the seventh TFT (T7) is connected to the pixel electrode of the seventh liquid crystal cell. The eighth TFT T8 supplies the data voltages from the (4i + 4) th data lines D4, D8 ... Dm / 2 in response to the second gate pulse from the even gate lines G2, G4 ... G2n To the pixel electrodes of the eighth liquid crystal cell arranged on the right side of the (4i + 4) th data lines (D4, D8 ... Dm / 2). The gate electrode of the eighth TFT T8 is connected to the even gate lines G2, G4 ... G2n and the drain electrode thereof is connected to the (4i + 4) th data lines D4, D8 ... Dm / 2. The source electrode of the eighth TFT (T8) is connected to the pixel electrode of the eighth liquid crystal cell. In the DRD panel shown in FIG. 18, the liquid crystal cells in the 4i + 1 and 4i + 4th column directions sequentially charge the data voltage along the charging sequence CS2 of the "Z & In the third column direction, the liquid crystal cells sequentially charge the data voltage along the " reverse Z "

The polarity of the data voltage supplied to the liquid crystal cells of the DRD panel shown in Figs. 17 and 18 is the same as that of the first to fourth polarity control signals POL1 to POL4 or the reference polarity control signal POL . In FIGS. 17 and 18, the bold solid arrows indicate the charging sequence of the data voltage.

The inventors of the present invention experimentally confirmed the DC after-image reduction effect when supplying the data voltages whose polarity is controlled by the polarity control signals as shown in FIG. 7 to the DRD panel as shown in FIG. 17 and FIG. 18 through experiments. In the same DRD panel, color distortions of 30 Hz flicker, line flicker, column flicker, and redish were observed. Therefore, the DRD panel can be applied to any one of the pixel arrays of FIGS. 2, 13 and 14, but when the polarity of the data voltage is controlled by the polarity control signals as shown in FIG. 7 in order to reduce the DC afterimage, It is preferable to implement the pixel array as shown in FIG.

As described above, the present invention reduces the number of output channels of the data lines and the data driving circuit to 1/2 or less by using the DRD panel, and it is possible to reduce the circuit cost by using the polarity control signals having different phases Thereby minimizing the DC after-image, flicker, and color distortion, thereby improving the display quality.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

1 is a block diagram showing a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram showing the pixel array of the liquid crystal display device shown in FIG. 1 in detail.

FIG. 3 and FIG. 4 are circuit diagrams showing the details of the data driving circuit shown in FIG.

Figures 5 and 6 are circuit diagrams illustrating the POL and data modulation logic circuit shown in Figure 1 in detail.

7 is a waveform diagram showing the polarity control signals of the present invention.

8 is a circuit diagram showing the data modulator shown in FIG. 5 in detail.

9 is a waveform diagram showing data voltages whose polarity is controlled according to the first polarity control signal shown in FIG. 7 and gate pulses synchronized with the data voltages.

FIGS. 10 and 11 are diagrams illustrating data polarities of liquid crystal cells that charge data voltages controlled according to the polarity control signals shown in FIG. 7 during the first to fourth frame periods.

12 is a waveform diagram illustrating overcharging of data voltages to be continuously charged in the liquid crystal cells indicated by arrows in Fig.

FIG. 13 is a diagram showing an example of down-modulation of data for preventing overcharge in FIG.

14 is a waveform diagram showing a principle in which a DC afterimage appears when interlaced data is input to a liquid crystal display device.

Fig. 15 is a diagram showing a change in data polarity of a liquid crystal cell decreasing a DC afterimage and a liquid crystal cell adjacent to and reducing flicker. Fig.

FIG. 16 is a waveform diagram showing a principle in which a DC afterimage does not appear when interlace data is input to the liquid crystal display by the liquid crystal cell shown in FIG. 15. FIG.

17 and 18 are views showing another example of a DRD panel applicable to the present invention.

Description of the Related Art

100; Liquid crystal display panel 101: Timing controller

103: POL and data modulation logic circuit 103: Data driving circuit

104: Gate drive circuit

Claims (8)

A liquid crystal layer is formed between the upper substrate and the lower substrate, m (m is a positive integer) / m arranged in a matrix form by an intersection structure of 2 data lines and 2n (n is a positive integer) A liquid crystal display panel including x n liquid crystal cells and TFTs connected to the liquid crystal cells; A data driving circuit for supplying a data voltage to the data lines in response to a polarity control signal; A gate driving circuit for supplying the gate lines; And A POL control circuit for controlling the phase of the polarity control signal differently for each frame period; And A data value for down-modulating the gray level of the digital video data corresponding to the second data voltage among the data voltages of the same polarity to be continuously charged in the liquid crystal cells existing in the neighboring lines of the liquid crystal display panel to a predetermined modulation value And a modulation circuit. The method according to claim 1, The liquid crystal cells, A first liquid crystal cell arranged on the left side of the odd data line, a second liquid crystal cell arranged on the right side of the odd data line, a third liquid crystal cell arranged on the left side of the even data line, And a fourth liquid crystal cell, The TFTs, A first TFT for supplying a data voltage from the odd data line to the pixel electrode of the first liquid crystal cell in response to a first gate pulse supplied to the odd gate line, A second TFT for supplying a data voltage from the odd data line to the pixel electrode of the second liquid crystal cell; a second TFT for supplying a data voltage from the odd data line to the pixel electrode of the third liquid crystal cell in response to the second gate pulse; And a fourth TFT for supplying a data voltage from the even data line in response to the first gate pulse to the pixel electrode of the fourth liquid crystal cell. The method according to claim 1, The POL control circuit includes: And sequentially outputs the first to fourth polarity control signals to generate the polarity control signal. The method of claim 3, The POL control circuit includes: A second polarity control signal having a phase different from that of the first polarity control signal is generated for a (4i + 2) -th frame period, A third polarity control signal is generated in a reverse phase of the first polarity control signal for a (4i + 3) -th frame period, and a fourth polarity control signal is generated in a reverse phase of the second polarity control signal in a Wherein the liquid crystal display device is a liquid crystal display device. 5. The method of claim 4, The logic of the first polarity control signal may be either a logic high by a half horizontal period, a logic low by a half horizontal period, a logic high by a half horizontal period, a logic low by a horizontal period, The high logic as much as the horizontal period, the low logic as much as the 1/2 horizontal period, and the high logic as much as the 1/2 horizontal period, The logic of the second polarity control signal may be one of a high logic by a half horizontal period, a low logic by one horizontal period, a high logic by a half horizontal period, a low logic by a half horizontal period, And a low logic as much as a half horizontal period. The method according to claim 1, Wherein the data modulator comprises: Among the data voltages of the same polarity to be continuously charged in the i-th (i is a positive integer) and i + 1-th lines every frame based on the frame count information from the frame counter and the line count information from the line counter An overcharge timing detecting section for detecting digital video data corresponding to a second data voltage and outputting a selection signal in accordance with the detection timing; A modulator for down-modulating the gray level value of the digital video data corresponding to the second data voltage to the predetermined modulation value using a memory in which the modulation value of the digital video data is stored; And The digital video data modulated by the modulating unit and the original digital video data not modulated by the modulating unit are received and the modulated digital video data is output only when a selection signal is inputted from the overcharge timing detecting unit, And a multiplexer for outputting original digital video data. The method according to claim 6, Wherein the overcharge- The digital video data of the data voltages to be charged in the liquid crystal cells of the (4i + 3) th line among the data voltages of the same polarity to be continuously charged in the liquid crystal cells of the 4i + 2 and 4i + A liquid crystal cell for detecting digital video data of a data voltage to be charged in the liquid crystal cells of the (4i + 2) th line among the data voltages of the same polarity to be continuously charged in the liquid crystal cells of the (4i + 1) Display device. The method according to claim 1, Wherein the modulation value is set differently according to the gradation of the data voltages to be continuously charged in the liquid crystal cells of the neighboring lines and the gradation value of the second data voltage.

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