KR101588897B1 - Liquid crystal display device - Google Patents

Abstract

The present invention relates to a liquid crystal panel, A printed circuit board for transmitting a system signal supplied from the outside; And a flexible printed circuit board attached to one side of the printed circuit board and one side of the liquid crystal panel, wherein the flexible printed circuit boards include a timing controller for converting a source signal, which is part of the system signals transmitted through the printed circuit board, And a data driver circuit for converting a driving signal output from the driving circuit to a data voltage and supplying the data voltage to the data lines of the liquid crystal panel are mounted on the liquid crystal display panel.

A liquid crystal display device, a printed circuit board, a driving chip

Description

[0001] LIQUID CRYSTAL DISPLAY DEVICE [0002]

The present invention relates to a liquid crystal display device.

A liquid crystal display device of an active matrix driving type displays a moving picture by using a thin film transistor (hereinafter referred to as "TFT") as a switching element. This liquid crystal display device can be downsized as compared with a cathode ray tube (CRT), and is applied to a display device in a portable information device, an office machine, a computer, etc., and is also applied to a television, thereby quickly replacing a cathode ray tube.

The liquid crystal display device includes a liquid crystal panel, a backlight unit for irradiating light to the liquid crystal panel, a timing controller for converting a part of system signals transmitted from the outside into a driving signal and a gate signal, And a gate driving circuit for converting the gate signal into a scan voltage and supplying the scan voltage to the scan lines of the liquid crystal panel.

In the conventional liquid crystal display device, a structure in which a timing controller and a data driving circuit are separately mounted on a printed circuit board (PCB) and a flexible circuit board (TCP) is used. However, in the case of a structure in which the timing controller and the data driving circuit are formed on the printed circuit board and the flexible circuit board, many signal wirings are wired on the printed circuit board, making it difficult to reduce the size of the printed circuit board There was a problem. Therefore, the conventional liquid crystal display device needs to solve the above-mentioned problems in order to increase the driving stability of the apparatus and to pursue the low cost and slimness.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned problems of the related art, and it is an object of the present invention to reduce the size of a printed circuit board and improve the driving stability of the driving chips mounted on the flexible circuit boards, And to provide a liquid crystal display device that can be used.

According to the present invention, there is provided a liquid crystal display device comprising: a liquid crystal panel; A printed circuit board for transmitting a system signal supplied from the outside; And a flexible printed circuit board attached to one side of the printed circuit board and one side of the liquid crystal panel, wherein the flexible printed circuit boards include a timing controller for converting a source signal, which is part of the system signals transmitted through the printed circuit board, And a data driver circuit for converting a driving signal output from the driving circuit to a data voltage and supplying the data voltage to the data lines of the liquid crystal panel are mounted on the liquid crystal display panel.

Each of the driving chips mounted on the flexible circuit boards can be controlled by a chip control signal so that the source signal is simultaneously supplied and the source signal is sequentially received from the first driving chip to the Nth driving chip among the driving chips have.

The liquid crystal panel may be supplied with data voltages classified by regions by respective driving chips mounted on the respective flexible circuit boards.

When the first driving chip is activated by the chip control signal, the remaining driving chips may be inactivated.

The chip control signal is included in the system signal and can correspond to the number of the respective driving chips.

The timing controller included in each drive chip can be activated by a chip control signal.

When the first timing controller included in the first driving chip is activated by the chip control signal, the first data driving circuit connected to the first timing controller supplies the data voltage to the first data lines of the liquid crystal panel and generates a carry signal .

The second timing controller included in the second driving chip adjacent to the first driving chip may be activated after receiving the chip control signal and the reception signal indicating that the source signal has been received from the first timing controller to the first timing controller .

The second data driving circuit included in the second driving chip adjacent to the first driving chip receives the carry signal from the first data driving circuit and outputs the driving signal supplied from the second timing controller included in the second driving chip to the data voltage To the second data lines of the liquid crystal panel.

The received signal is delivered in the form of a Low Voltage Differential Signaling (LVDS) interface, and the carry signal can be delivered in the form of a mini LVDS interface.

The present invention is configured such that the driving chips integrated into one chip of the timing controller and the data driving circuit are mounted on a plurality of flexible circuit boards and can be controlled thereby to reduce the size of the printed circuit board, There is an effect of providing a liquid crystal display device which is designed to improve the heat generation of the driving chips mounted on the circuit boards, thereby improving the driving stability and reducing the cost and the slimness.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a liquid crystal display device according to an embodiment of the present invention, and FIGS. 2 to 4 are equivalent circuit diagrams showing the pixel array shown in FIG.

1 to 4, a liquid crystal display according to an embodiment of the present invention includes a liquid crystal panel 10, a data driving circuit 12 connected to the data lines D1 to Dm of the liquid crystal panel 10, A gate drive circuit 13 connected to the gate lines G1 to Gn of the liquid crystal panel 10, a timing controller 11 for controlling the data drive circuit 12 and the gate drive circuit 13, And a power supply unit 15 for supplying power.

The liquid crystal panel 10 includes an upper glass substrate and a lower glass substrate opposed to each other with a liquid crystal layer interposed therebetween. The liquid crystal panel 10 includes a pixel array for displaying video data. The pixel array of the lower glass substrate includes TFTs formed at intersections of the data lines D1 to Dm and the gate lines G1 to Gn, and pixel electrodes connected to the TFTs. Each of the liquid crystal cells of the pixel array is driven by the voltage difference between the data voltage applied to the pixel electrode 1 that charges the data voltage through the TFT and the common voltage Vcom applied to the common electrode 2, And adjusts the amount of light transmitted from the light source 16 to display an image of the video data.

The pixel array can be configured in the form of an equivalent circuit of any one of Figs. Fig. 2 shows a pixel array equivalent circuit in a normal form. On the other hand, FIG. 3 shows a pixel array equivalent circuit of FIG. 2 in which the number of data lines is reduced to 1/2. This makes it possible to reduce the number of data lines to 1/2 of the structure of FIG. 2 by sharing the data lines on both sides. On the other hand, FIG. 4 shows a pixel array equivalent circuit of FIG. 2 in which the number of data lines is reduced to 1/3. This is because the R, G, and B pixels share one data line, thereby reducing the number of data lines to 1/3 of the structure of FIG.

On the upper glass substrate of the liquid crystal panel 10, a black matrix, a color filter, and a common electrode are formed. The common electrode 2 is formed on the upper glass substrate in the vertical field driving mode such as the TN mode and the VA mode and is formed on the lower glass substrate together with the pixel electrode 1 in the horizontal electric field driving method such as the IPS mode and the FFS mode . An alignment film is formed on each of the upper glass substrate and the lower glass substrate of the liquid crystal panel 10 to attach a polarizing plate and set a pre-tilt angle of the liquid crystal.

The liquid crystal mode of the liquid crystal panel 10 applicable to the present invention can be implemented in any liquid crystal mode as well as the TN mode, the VA mode, the IPS mode, and the FFS mode described above. Further, the liquid crystal display device of the present invention can be implemented in any form such as a transmissive liquid crystal display device, a transflective liquid crystal display device, a reflective liquid crystal display device, and the like. In a transmissive liquid crystal display device and a transflective liquid crystal display device, a backlight unit is required. The backlight unit 16 may be implemented as a direct type backlight unit or an edge type backlight unit. The direct-type backlight unit has a structure in which a plurality of optical sheets and a diffusion plate are stacked under the liquid crystal panel 10 and a plurality of light sources are disposed under the diffusion plate. The edge type backlight unit has a structure in which a light source is disposed so as to face the side face of the light guide plate and a plurality of optical sheets are disposed between the liquid crystal panel and the light guide plate. The light source of the backlight unit may include at least one of a hot cathode fluorescent lamp (HCFL), a cold cathode fluorescent lamp (CCFL), an external electro fluorescent lamp (EEFL), and a light emitting diode (LED).

The system board 14 is connected to the RGB video data input from the broadcast receiving circuit or the external video source and outputs a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, a dot clock CLK To the timing controller 11 through a Low Voltage Differential Signaling (LVDS) interface or a Transition Minimized Differential Signaling (TMDS) interface transmission circuit. The system board 14 is provided with a graphics processing circuit such as a scaler for interpolating and interpolating the resolution of RGB video data input from a broadcast receiving circuit or an external video source in accordance with the resolution of the liquid crystal panel, (Vin).

The power supply unit 15 generates a driving voltage by adjusting a voltage Vin supplied to the system board 14 and outputs the generated driving voltage to the timing controller 11, the data driving circuit 12, the gate driving circuit 13, To the liquid crystal panel (10). The power supply unit 15 is formed of a DC-DC converter. The drive voltage is 15V ~ the high-potential power supply voltage (Vdd) of between 20V, the logic power supply voltage (Vcc), 15V or more gate high voltage (V _GH) of about 3.3V, a gate row of -3V or less generated by the power supply section 15 voltage (V _GL), the common voltage (Vcom) between 7V ~ 8V, the positive / negative gamma reference voltages (V _GMA1 ~V _GMA10), such as core power voltage (core power voltage) between 1.2V ~ 1.8V . The high-potential power supply voltage (Vdd) is a maximum data voltage to be charged in the liquid crystal cells of the liquid crystal panel (10). The logic power supply voltage Vcc is a power supply voltage of the digital logic device such as the timing controller 11, the data driving circuit 12, and the gate driving circuit 13. The gate high voltage V _GH is a high logic voltage of the gate pulse set above the threshold voltage of the TFTs formed in the pixel array and the gate low voltage V _GL is the gate voltage of the gate pulse And is supplied to the gate drive circuit 13 as a low logic voltage of. The common voltage Vcom is supplied to the common electrode 2 of the liquid crystal cells Clc. The data driving circuit 12 can supply the common voltage Vcom to the data lines D1 to Dm as the charge sharing voltage during the high logic period of the source output enable signal SOE. In the storage on common method, the storage electrode of the storage capacitor Cst may be formed on the lower glass substrate of the liquid crystal panel 10 so as to overlap the pixel electrode 1 of the liquid crystal cells with the insulating layer sandwiched therebetween. have. In the storage-on-com method, a common voltage (Vcom) can be supplied to the storage electrode. The core power voltage is the logic voltage to generate the mini LVDS data voltage.

The timing controller 11 receives RGB digital video data, a vertical synchronizing signal Vsync, a horizontal synchronizing signal Hsync, and a data enable signal (for example, from the system board 14) via an interface receiving circuit such as an LVDS interface and a TMDS interface Data Enable, DE), a dot clock (CLK), and the like. The timing controller 11 transmits three RGB digital video data to the data driving circuit in a mini-LVDS (low-voltage differential signaling) interface method in order to reduce the swing width of EMI and data voltage on the data transmission path. The timing controller 11 generates a driving signal such as data control signals SOE and POL for controlling the data driving circuit using the timing signals Vsync, Hsync, DE and CLK and the operation timing of the gate driving circuit 13 Such as gate timing control signals GSP, GSC, and GOE, The timing controller 11 controls the timing controller 11 so that the digital video data input at a frame frequency of 60 Hz can be reproduced in the pixel array of the liquid crystal panel 10 at a frame frequency of 60 x i (i is a positive integer) The frequency of the data timing control signal can be multiplied by a frame frequency of 60 x i Hz.

The data timing control signal includes a source output enable signal SOE, a polarity control signal POL, and the like. Since the signal transmission system between the timing controller 11 and the data driving circuit 12 is a mini LVDS interface, a source start pulse (SSP) and a source sampling clock (SSC) Can be omitted. The source output enable signal SOE controls the output timing of the data driving circuit 12. The data driving circuit 12 generates a charge share voltage or a common voltage Vs in response to the pulse of the source output enable signal SOE when the polarity of the data voltage supplied to the data lines D1 to Dm is changed. Vcom to the data lines D1 to Dm and supplies the data voltages to the data lines D1 to Dm during the low logic period of the source output enable signal SOE. The charge sharing voltages are average voltages of neighboring data lines to which data voltages of opposite polarities are supplied. The polarity control signal POL inverts the polarity of the data voltage output from the data driving circuit 12 in a period of N (N is a positive integer) horizontal period.

The gate timing control signal includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), and the like. The gate start pulse (GSP) controls the timing of the first gate pulse. The gate shift clock GSC is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output timing of the gate drive circuit 13. [

The data driving circuit 12 samples and latches the RGB digital video data RGB according to the R, G, and B data of the mini LVDS interface standard and the mini LVDS clock from the timing controller 11 and converts them into data of a parallel data system do. A data drive circuit 12 to the liquid crystal cell using parallel data transmission in the system, the digital video data converted into a response to a polarity control signal (POL) positive / reverse the polarity gamma reference voltage (V _GMA1 ~ V _GMA10) And supplies them to the data lines D1 to Dm in response to the source output enable signal SOE from the timing controller 11. [

The gate driving circuit 13 includes a shift register for sequentially shifting the gate driving voltage in response to the gate timing control signals GSP, GSC and GOE from the timing controller 11 so as to be supplied to the gate lines G1 to Gn And sequentially supplies gate pulses (or scan pulses).

Hereinafter, the data driving circuit will be described in more detail.

5 is a circuit diagram showing the details of the data driving circuit.

5, the data driving circuit 12 includes a shift register 21, a data receiving unit 22, a first latch array 23, a second latch array 24, a digital-to-analog converter Quot;) 25, a charge share circuit 26, an output circuit 27, and the like.

The data receiving unit 22 receives the mini LVDS data (RGB) and the mini LVDS clock input from the timing controller 11, restores the TTL level RGB digital video data by the mini LVDS interface restoration method, and outputs the TTL level source sampling clock (SSC).

The shift register 21 generates a sampling clock by shifting the source sampling clock SSC and generates a carry signal CARRY when the data exceeding the number of latches of the first latch array 23 is supplied . The first latch array 23 samples the digital video data RGB restored from the data receiving unit 22 in response to a sampling clock sequentially input from the shift register 21 and outputs the data RGB One horizontal line is latched, and then one horizontal line of data is simultaneously output.

The second latch array 24 latches the digital video data of one horizontal line input from the first latch array 23 and then outputs the digital video data of the second latch array 24 And outputs the latched digital video data RGBeven and RGBodd.

The DAC 25 includes a P-decoder to which a positive gamma compensation voltage GH is supplied, an N-decoder to which a negative gamma compensation voltage GL is supplied, and a polarity control signal POL, And a multiplexer for selecting an output of the N-decoder. The P-decoder decodes the digital video data RGB input from the second latch array 24 and outputs a positive gamma compensation voltage GH corresponding to the gray level of the data, Decodes the digital video data input from the latch array 24 and outputs a negative gamma compensation voltage GL corresponding to the gray level value of the data. The multiplexer selects a positive gamma compensation voltage and a negative gamma compensation voltage in response to the polarity control signal.

The charge share circuit 26 shorts neighboring data output channels during the high logic period of the source output enable signal SOE to output the average value of neighboring data voltages to the charge sharing voltage, So as to reduce the rapid change of the positive polarity data voltage and the negative polarity data voltage.

The output circuit 27 uses the buffer to reduce the signal attenuation of the positive / negative analog data voltage supplied to the data lines (D1 to Dk, k is a positive integer smaller than m).

Hereinafter, the connection structure of the driving chips mounted on the flexible circuit boards according to the embodiment of the present invention will be described.

FIG. 6 is a schematic view illustrating a connection structure of driving chips mounted on flexible printed circuit boards according to an embodiment of the present invention, and FIG. 7 is a cross-sectional view of the timing controllers and data driving circuits included in the driving chips of FIG. Fig.

6 and 7, a printed circuit board 40, flexible circuit boards 30a and 30b, and a liquid crystal panel 10 are shown. The power supply unit 15 is mounted on the printed circuit board 40 and the gate drive circuits 13A and 13B are formed on the left and right sides of the liquid crystal panel 10 as an example.

The first and second flexible printed circuit boards 30a and 30b are connected to one side of the printed circuit board 40 and the liquid crystal panel 10 by an anisotropic conductive film (ACF) (10).

A system signal (SS) output from the system board (14) is supplied to the printed circuit board (40). First and second driving chips 17a and 17b are mounted on the first and second flexible printed circuit boards 30a and 30b, respectively. The first driving chip 17a is formed by integrating the first timing controller 11a and the first data driving circuit 12a into one chip and the second driving chip 17b is formed by the second timing controller 11b, 2 data driver circuits 12b are integrated into one chip.

The first and second timing controllers 11a and 11b included in the first and second driving chips 17a and 17b are connected to the source signal that is part of the system signal SS transmitted through the printed circuit board 40, RGB video data R, G and B and data control signals SOE and POL into a driving signal and supplies the driving signal to the first and second data driving circuits 12a and 12b. The first and second data driving circuits 12a and 12b convert the driving signal into a data voltage and output the data voltages to the data lines (the first data line) 10a divided into the first display area 10A and the second display area 10b D1 to Gm. The liquid crystal panel 10 is divided into the regions of the liquid crystal panel 10 by the first and second driving chips 17a and 17b mounted on the first and second FPCBs 30a and 30b The divided data voltages can be supplied.

The first and second driving chips 17a and 17b mounted on the first and second flexible printed circuit boards 30a and 30b respectively receive RGB video data R, G and B, data control signals SOE and POL ) And the like are controlled so that the source signal is sequentially received from the first driving chip 17a to the second driving chip 17b.

The first driving chip 17a and the second driving chip 17b may be controlled by the first and second chip control signals E1 and E2 included in the system signal. When the first driving chip 17a is activated by the first one of the first and second chip control signals E1 and E2, the remaining second driving chip 17b outputs the second chip control signal E2). The second timing controller 11b receives the reception signal CAA indicating that the source signal has been received by the first timing controller 11a from the first timing controller 11a and then supplies the second chip control signal E2 It can only be activated if it is received. The received signal CAA transmitted between the first timing controller 11a and the second timing controller 11b may be transmitted in the form of a Low Voltage Differential Signaling (LVDS) interface, but is not limited thereto.

The devices activated or deactivated by the first and second chip control signals E1 and E2 among the devices integrated in the first and second driving chips 17a and 17b are connected to the first and second timing controllers 11a and 11b, 11b. The first and second timing controllers 11a and 11b may include reception units supplied with the first and second chip control signals E1 and E2. The receiving units are connected to the first and second timing controllers 11a and 11b so as to receive the system signal SS output from the system board 14 when the first and second chip control signals E1 and E2 are logic high. 11b. Conversely, the receiving units are connected to the first and second timing controllers 11a and 11b so as not to receive the system signal SS output from the system board 14 when the first and second chip control signals E1 and E2 are logic low, 0.0 > 11b < / RTI > However, this is merely one example described for the sake of understanding of the embodiment, but the present invention is not limited thereto.

When the first timing controller 11a included in the first driving chip 17a is activated by the first chip control signal E1, the first data driving circuit 12a connected to the first timing controller 11a outputs the data voltage May be supplied to the first display region 10A where the first data lines of the liquid crystal panel 10 are located and a carry signal CAR may be generated. The second data driving circuit 12b included in the second driving chip 17b receives the carry signal CAR generated from the first data driving circuit 12a and is supplied from the second timing controller 11b The driving signal may be converted into a data voltage and supplied to the second display region 10B where the second data lines of the liquid crystal panel 10 are located. The carry signal CAR transferred between the first data driving circuit 12a and the second data driving circuit 12b may be transferred in the form of a mini LVDS interface, but is not limited thereto.

In the embodiment, two driving chips mounted on the flexible circuit boards are described as an example. However, the driving chips may be mounted on the respective flexible circuit boards from the first driving chip to the Nth driving chip depending on the size of the liquid crystal display device, and each of the driving chips may be mounted on the first driving chip to the Nth driving chip And can be controlled by a chip control signal to be sequentially received. In this case, the chip control signal is included in the system signal and may correspond to the number of each driving chip, but is not limited thereto. In the case of the flexible circuit boards having the driving chips formed as above, the present invention can be applied to the pixel array shown in FIGS. 2 to 4, as well as the large area display device having a large number of data lines, Device.

Hereinafter, the operation of the first and second driving chips 17a and 17b will be described in brief as follows.

When the system signal SS is outputted from the system board 14, the first and second driving chips 17a and 17b receive the system signal SS at the same time. However, the apparatus activated to substantially receive the system signal SS by the first chip control signal E1 included in the system signal SS is activated by the first timing controller 11a included in the first driving chip 17a ). At this time, the second driving chip 17b becomes inactive. The activated first timing controller 11a converts the source signal to a source signal driving signal that is part of the system signal SS and supplies the source signal to the first data driving circuit 12a. The first data driving circuit 12a converts the driving signal to a data voltage Conversion. At this time, the first timing controller 11a transmits the reception signal (CAA) indicating that the system signal SS has been completely received to the deactivated second timing controller 11b. Then, the second timing controller 11b included in the second driving chip 17b is activated by the second chip control signal E2, and the first timing controller 11a is inactivated. The activated second timing controller 11b converts the signal into a source signal driving signal that is part of the system signal SS and supplies the signal to the second data driving circuit 12b and the second data driving circuit 12b converts the driving signal into a data voltage Conversion.

The driving chips 17a and 17b including the timing controllers 11a and 11b and the data driving circuits 12a and 12b respectively receive the chip control signals E1 and E2, The system signal SS output from the system board 14 is converted into a data voltage to be supplied to the first display area 10A and the second display area 10B of the liquid crystal panel 10 .

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. There is an effect of providing a liquid crystal display device which is designed to improve the heat generation of the driving chips mounted on the circuit boards, thereby improving the driving stability and reducing the cost and the slimness.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the following claims rather than the detailed description. Also, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

1 is a block diagram showing a liquid crystal display device according to an embodiment of the present invention;

Figs. 2 to 4 are equivalent circuit diagrams showing the pixel array shown in Fig. 1. Fig.

5 is a circuit diagram showing a data driving circuit in detail;

6 is a view schematically showing a connection structure of driving chips mounted on flexible circuit boards according to an embodiment of the present invention;

FIG. 7 is a detailed view showing a connection structure of timing controllers and data driving circuits included in the driving chips of FIG. 6;

DESCRIPTION OF THE REFERENCE NUMERALS

10: liquid crystal panel 11a, 11b: timing controller

12a, 12b: data driver circuits 13a, 13b: gate driver circuits

15: power supply unit 30a, 20b: flexible circuit boards

40: printed circuit board

Claims (10)

A liquid crystal panel; A printed circuit board for transmitting a system signal supplied from the outside; And And a flexible circuit board attached to one side of the printed circuit board and one side of the liquid crystal panel, The flexible circuit boards, A timing controller for converting a source signal, which is a part of system signals transmitted through the printed circuit board, into a driving signal, and a data driving circuit for converting the driving signal output from the timing controller into a data voltage and supplying the data voltage to data lines of the liquid crystal panel And a driving chip, which is activated or deactivated by a chip control signal included in the system signal, is mounted, The source signal is simultaneously supplied to the respective drive chips mounted on the flexible circuit boards, Wherein each of the driving chips is controlled by the chip control signal such that the source signal is sequentially received from the first driving chip to the Nth driving chip among the driving chips. delete The method according to claim 1, In the liquid crystal panel, And a data voltage divided by regions is supplied to each of the driving chips mounted on each of the flexible circuit boards. The method according to claim 1, And when the first driving chip is activated by the chip control signal, the remaining driving chips are inactivated. The method according to claim 1, Wherein the chip control signal comprises: Wherein the number of the driving chips corresponds to the number of the driving chips. The method according to claim 1, Wherein the timing controller included in each of the driving chips comprises: And is activated by the chip control signal. The method according to claim 1, When the first timing controller included in the first driving chip is activated by the chip control signal, the first data driving circuit connected to the first timing controller supplies the data voltage to the first data lines of the liquid crystal panel And generates a carry signal. 8. The method of claim 7, A second timing controller included in a second driving chip adjacent to the first driving chip, Wherein the first timing controller is activated after receiving the chip control signal and a reception signal indicating that the source signal has been received from the first timing controller to the first timing controller. 8. The method of claim 7, And a second data driving circuit included in a second driving chip adjacent to the first driving chip, And a driving signal supplied from the second timing controller included in the second driving chip is converted into a data voltage and supplied to the second data lines of the liquid crystal panel . 9. The method of claim 8, Wherein the received signal is transmitted in the form of a low voltage differential signaling (LVDS) interface, and the carry signal is transmitted in the form of a mini LVDS interface.

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