KR101520492B1 - Liquid crystal display and driving method thereof - Google Patents

Abstract

An embodiment of the present invention is a liquid crystal display device including: a liquid crystal panel including sub pixels arranged in a matrix form in a display area and dummy pixels arranged in a non-display area; A gate driver for supplying a gate signal to the liquid crystal panel; A data driver for supplying a data signal to the liquid crystal panel; Gate wirings wired to the liquid crystal panel and transmitting gate signals output from the gate driver; And a data driver that is connected to the liquid crystal panel and transmits a data signal output from the data driver, wherein the data driver copies the (m-2) th data signal supplied to the (m-2) And a signal conversion unit for supplying the data signal to the (m) -th data line and supplying the third data signal to the first data line by copying the third data signal supplied to the third data line.

Liquid crystal display, data wiring, dummy pixel

Description

TECHNICAL FIELD [0001] The present invention relates to a liquid crystal display (LCD)

An embodiment of the present invention relates to a liquid crystal display and a driving method thereof.

As the information technology is developed, the market of display devices, which is a connection medium between users and information, is getting larger. Accordingly, a flat panel display (FPD) such as a liquid crystal display (LCD), an organic light emitting diode (OLED), and a plasma display panel (PDP) Usage is increasing. Among them, liquid crystal display devices capable of realizing high resolution and capable of not only miniaturization but also enlargement are widely used.

Here, the liquid crystal display device is classified into a light receiving display device. Such a liquid crystal display device can display an image by receiving a light source from a backlight unit located under the liquid crystal panel. Such a liquid crystal display device mainly comprises a transistor array substrate and a color filter substrate. A sub-pixel including a gate, a semiconductor layer, a transistor including a source and a drain, a pixel electrode connected to a source or a drain of the transistor, and the like is formed on the transistor array substrate. A color filter and a black matrix are formed on the color filter substrate.

Conventional liquid crystal display devices are capable of eliminating the interlace afterimage technique which is a problem in a television (TV), and are capable of reducing flicker due to reduction of luminance components and frequency components of alternating current (AC) A method for eliminating the occurrence phenomenon should be prepared.

An embodiment of the present invention for solving the problems of the background art described above is an image processing apparatus that removes the interlaced afterglow technique which is a problem in a television and reduces the luminance difference and the frequency component of the AC component caused by the inversion of the specific frame, And a method of driving the liquid crystal display device.

According to an aspect of the present invention, there is provided a liquid crystal display device comprising: a liquid crystal panel including subpixels arranged in a matrix in a display region and dummy pixels arranged in a non-display region; A gate driver for supplying a gate signal to the liquid crystal panel; A data driver for supplying a data signal to the liquid crystal panel; Gate wirings wired to the liquid crystal panel and transmitting gate signals output from the gate driver; And a data driver that is connected to the liquid crystal panel and transmits a data signal output from the data driver, wherein the data driver copies the (m-2) th data signal supplied to the (m-2) And a signal conversion unit for supplying the data signal to the (m) -th data line and supplying the third data signal to the first data line by copying the third data signal supplied to the third data line.

The dummy pixels include m-th dummy pixels disposed corresponding to the odd-numbered rows of the m-th column to receive the data signal from the m-th data wiring, And may include first dummy pixels arranged corresponding to even rows.

The (m-2) th data signal may be supplied to the m-th dummy pixels, and the first data signal may be supplied to the first dummy pixels.

The data lines can be wired so that the subpixels arranged on the odd line are wired to receive the data signal from the data wirings passing through the corresponding line and the subpixels arranged on the even wirings receive the data signal from the data wirings passing through the next column have.

The signal converting unit may control the polarity control signal supplied to the data driver so that the (m-2) th data signal and the first data signal are supplied to the m-th data line and the first data line.

The subpixels may be arranged in the order of red, green, and blue subpixels in the direction in which the data lines are wired.

According to another aspect of the present invention, there is provided a method of driving a liquid crystal display, including: supplying a gate signal to gate wirings wired to a liquid crystal panel; And supplying data signals to the data lines wired to the liquid crystal panel, and supplying the data signals to the m-th data line positioned at the last one by copying the (m-2) -th data signal supplied to the (m- And the third data signal supplied to the third data line is copied and supplied to the first data line.

The (m-2) -th data signal is supplied to the m-th dummy pixels located in the non-display area of the liquid crystal panel, and the first data signal may be supplied to the first dummy pixels located in the non- have.

Embodiments of the present invention are capable of eliminating the occurrence of flicker due to the reduction in the luminance difference and the frequency component of the alternating current (AC) component caused by the inversion of a specific frame while eliminating the problem of the interlace afterimage technique which is a problem in the television There is an effect of providing a liquid crystal display device and a driving method thereof.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a configuration diagram of a liquid crystal display device according to an embodiment of the present invention.

1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel 110, a timing controller 120, a gate driver 130, a data driver 140, a lamp driver 150, Unit 160 may be included.

In the liquid crystal panel 110, a liquid crystal layer is formed between two substrates. The liquid crystal panel 110 includes subpixels R, G, and B arranged in a matrix form by an intersection structure of the gate lines G1 to Gn and the data lines D1 to Dm. The subpixels R, G, and B may be arranged in the order of red, green, and blue subpixels R, G, and B in the direction in which the data lines D1 to Dm are wired.

The gate lines G1 to Gn, the data lines D1 to Dm, the TFTs and the storage capacitor Cst are formed on the first substrate of the liquid crystal panel 110, A black matrix, a color filter, and the like are formed. The liquid crystal layer is driven by an electric field formed between the pixel electrode connected to the TFT and the common electrode. Meanwhile, the common electrode is formed on the second substrate in the case of a vertical field driving method such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode, and is formed in an IPS (In Plane Switching) mode, an FFS And is formed on the first substrate together with the pixel electrode in the case of the same horizontal electric field driving method. A polarizing plate is attached to the outside of the first substrate and a second substrate of the liquid crystal panel 110, and a pre-tilt angle of liquid crystal is set inside the first and second substrates of the liquid crystal panel 110 An alignment film for setting is formed.

The timing controller 120 supplies the digital video data RGB to the data driver 140. The timing controller 120 may transmit digital video data and a mini LVDS clock to the data driver 140 using a mini-LVDS (low-voltage differential signaling) method.

The timing controller 120 multiplies the timing signals such as the vertical synchronizing signal Vsync, the horizontal synchronizing signal Hsync, the data enable signal DE and the dot clock CLK n times to obtain an input frame frequency of 60 Hz The operation timing of the data driver 140 and the gate driver 130 can be controlled with a frame frequency multiplied by a contrast n (n is a positive integer equal to or greater than 2). Since the timing controller 120 can determine the frame period by counting the data enable signal of one horizontal period, the timing control unit 120 outputs the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync ) May be omitted.

The liquid crystal panel 110 displays video data at a frame frequency of 60 x n Hz such as a frame frequency of 120 Hz, a frame frequency of 180 Hz, and a frame frequency of 240 Hz by multiplying the frame frequency of the timing controller 120, You can do it fast. The frame-speed-driving technique of the timing controller 120 is disclosed in Korean Patent Laid-Open Nos. 10-2008-0002304, 10-2008-0063435, and 10-2008-0112933 proposed by the present applicant, And can be applied as a speed-limiting driving technique. The control signals generated by the timing controller 120 may include a gate timing control signal for controlling the operation time of the gate driver 130 and a data timing control signal for controlling the operation timing of the data driver 140 and the polarity of the data voltage .

The gate timing control signal includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), and the like. The gate start pulse GSP is applied to the gate drive IC which generates the first gate pulse (or scan pulse). The gate shift clock GSC is a clock signal commonly input to the gate drive ICs, and is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output of the gate drive ICs. The gate timing control signal is multiplied n times by the timing control unit 120 according to the frame frequency.

The data timing control signal includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (POL), and a source output enable signal (SOE) . The source sampling clock SSC and the source output enable signal SOE are multiplied by the timing control unit 120 according to the frame frequency but the polarity control signal POL is divided by n so that the frequency is lower than the frame frequency. The source start pulse SSP controls the data sampling start timing of the data driver 140. The source sampling clock SSC is a clock signal for controlling the sampling operation of data in the data driver 140 based on the rising or falling edge. The polarity control signal POL controls the vertical polarity of the data voltage output from the data driver 140. The source output enable signal SOE controls the output of the data driver 140. If digital video data and a mini LVDS clock are transmitted between the timing controller 120 and the data driver 140 in the mini LVDS system, since the first clock generated after the reset signal of the mini LVDS clock serves as a start pulse, SSP) may be omitted.

The lamp driving unit 150 may receive the vertical synchronizing signal Vsync and the horizontal synchronizing signal Hsync from the timing controller 120 and may control the lamp unit 160.

The lamp unit 160 includes a cold cathode fluorescent lamp (CCFL), a hot cathode fluorescent lamp (HCFL), an external electrode fluorescent lamp (EEFL), and a light emitting diode Diode: LED), but the present invention is not limited thereto.

Hereinafter, subpixels and dummy pixels arranged in the liquid crystal panel will be described with reference to FIG.

2 is a schematic layout diagram of sub pixels and dummy pixels arranged in a liquid crystal panel.

2, the liquid crystal panel 110 includes subpixels SP arranged in a matrix form in a display area AA and dummy pixels DP1 and DPm arranged in a non-display area NA . The subpixels SP arranged in the display area AA are defined as actual pixels representing an image on the liquid crystal panel 110 and the dummy pixels DP1 and DPm arranged in the non- Are defined as dummy pixels that do not display an image on the liquid crystal panel 110. [

The subpixels SP arranged in the liquid crystal panel 110 can receive a gate signal from the gate driver 130 connected to the gate lines (not shown) A data signal can be supplied from the data driver 140.

The data lines D1 to Dm are wired so that the subpixels arranged on the odd line are supplied with the data signal from the data line passing through the corresponding line and the subpixels arranged on the even line are supplied with the data signal from the data line passing through the next column It can be wired to receive. For example, in the case of the subpixels arranged on the odd-numbered lines of the second data line, the subpixels are connected to the second data line D2 passing through the corresponding line so as to receive a data signal from the second data line D2, In the case of the subpixels arranged on the even-numbered lines, the subpixels are connected to the third data line D3 passing through the next line so as to receive the data signal from the third data line D3.

The dummy pixels DP1 and DPm include Nth dummy pixels DPm arranged corresponding to the odd rows of the Nth column to receive data signals from the Nth data line Dm, And first dummy pixels (DP1) arranged corresponding to even rows of the first column to receive data signals from the first dummy pixels (D1).

Hereinafter, the data driver will be described with reference to FIG.

3 is a configuration diagram of the data driver.

3, the data driver includes a shift register 141, a data register 142, a first latch 143, a second latch 144, a digital-to-analog converter (hereinafter referred to as a DAC) An output unit 145, an output unit 146, and the like.

The shift register 141 shifts the data sampling clock in accordance with the source sampling clock SSC supplied from the timing controller 120. In addition, the shift register 141 transfers the carry signal CAR to the shift register 141 of the next source drive IC in the neighboring stage.

The data register 142 temporarily stores the digital video data RGB supplied from the timing control unit 120 and supplies the data RGB to the first latch 143. The first latch 143 samples and latches the digital video data RGB according to a data sampling clock sequentially supplied from the shift register 141 and then simultaneously outputs the latched data RGB. The second latch 144 latches the data RGB supplied from the first latch 143 and then synchronizes with the second latch 144 of the other source drive ICs in response to the source output enable signal SOE And simultaneously outputs the latched data (RGB).

The DAC 145 includes a P-decoder to which a positive gamma reference voltage GH is supplied, an N-decoder to which a negative polarity gamma reference voltage GL is supplied, and a polarity control signal POL, And a multiplexer for selecting the output of the N-decoder. Decoder decodes the digital video data (RGB) supplied from the second latch 144 and outputs a positive gamma compensation voltage corresponding to the gray level value of the data, and the N-decoder outputs the positive gamma compensation voltage from the second latch 144 Decodes supplied digital video data (RGB), and outputs a negative gamma compensation voltage corresponding to the tone value of the data. The multiplexer alternately selects the positive gamma compensation voltage and the negative gamma compensation voltage in response to the polarity control signal POL and outputs the selected positive / negative gamma compensation voltage as the positive / negative analog video data voltage .

The output 146 shortens the neighboring data output channels during the high logic period of the source output enable signal SOE to output an average value of neighboring data voltages and output a charge share voltage To the data lines D1 to Dm and then supplies the positive / negative analog video data voltages to the data lines D1 to Dm.

The signal converting unit 148 copies the (m-2) -th data signal supplied to the (m-2) -th data line Dm-2 and supplies the copied data to the m-th data line Dm positioned at the last, The polarity control signal POL can be controlled so that the third data signal supplied to the third data line D3 is copied and supplied to the first data line D1. Accordingly, the (m-2) -th data signal may be supplied to the m-th dummy pixels DPm, and the first data signal may be supplied to the first dummy pixels DP1. The signal conversion unit 148 may be configured to copy the data signal in the above-described manner using a flip register, but the present invention is not limited thereto. Although the signal conversion unit 148 is included in the data driver 140 in the embodiment, the data driver 140 may be located outside the data driver 140.

Hereinafter, pattern patterns of the liquid crystal panel according to the output waveform of the data signal output from the data driver will be described as a comparative example and an embodiment.

FIG. 5 is a diagram for explaining an embodiment of the present invention. FIG. 6 is an output waveform diagram of a data signal according to a comparative example, and FIG. FIG. 8 is a diagram showing a pattern pattern of the panel according to the output waveform of the data signal shown in FIG. 7. FIG.

Referring to FIGS. 4 and 5, the subpixels SP and the dummy pixels DP1 and DPm are arranged in the comparative example and the embodiment as described above with reference to FIG.

The above-described comparative examples and embodiments can eliminate the interlace afterimage technique which is a problem in the television (TV). In addition, it is possible to eliminate the occurrence of flicker due to the reduction in the luminance difference and the frequency component of the AC component caused by the inversion of the specific frame.

However, the comparative example and the embodiment are similar in that the data driver is controlled so that a part of a specific data signal can be copied and supplied to another data line in order to solve the above problem. However, in the case of the method according to the comparative example, the first and last vertical lines displayed on the panel have a disadvantage in that they can display a screen that is brighter or darker than other areas. On the other hand, in the method according to the embodiment, all the vertical lines displayed on the panel have the advantage that they can display the same screen. Hereinafter, Comparative Examples and Examples will be described.

First, in the case of the comparative example shown in FIG. 4, the data driver supplies data signals to the (m-1) -th data line Dm-1 supplied to the Th data signal. And the m-th data signal supplied to the m-th data line Dm positioned at the last position of the odd-numbered line with the data signal to be supplied to the first data line D1 of the even-numbered line.

In the case of the comparative example, the data signal supplied last in the screen driving is a data signal of the m-th dummy pixel DPm of the first line, the (m-1) th subpixel SPm-1 of the second line, (M-1) th sub-pixel (SPm-1) of the fourth line. And the data signal supplied before the last scan on the screen is the (m-2) th subpixel (SPm-2) -> the (m-3) th subpixel (M-2) th sub-pixel (SPm-2) of the fourth line and the (m-3) th sub-pixel (Spm-3) of the fourth line.

In the comparative example, assuming that the black system is 10 and the white system is 250, the output waveform of the data signal by the driving method of the comparative example will be described numerically as follows.

Referring to (Dm) in FIG. 6, the data signal supplied last in the screen driving is the m-th dummy pixel (DPm) of the first line: "250" (M-1) th sub-pixel (SPm-1) of the fourth line: "250" .

Referring to (Dm-1) of FIG. 6, the data signal supplied before the last in the screen driving is the (m-2) th subpixel (SPm-2) of the first line: (M-3) th subpixel (SPm-3): "250" -> the (m-2) th subpixel Pixel (SPm-3): "250 ".

In the case of the driving method according to the comparative example, as shown in (Dm) in Fig. 6, the voltage corresponding to "250" However, as shown in (Dm-1) of FIG. 6, the voltage corresponding to "0" and "250" In this case, it can be seen that the rising time of the voltage corresponding to the data signal supplied before the last of the screen driving is relatively faster than the voltage corresponding to the data signal supplied last in the screen driving.

When the data signal output from the data driver is the same, the liquid crystal panel should display the same black series value in the odd number lines and the same white series value in the even number lines. As shown in "PT" of FIG. 8A, the (m-1) th sub-pixels SPm-1 supplied with the data signal supplied before the last one on the screen drive are located on the other even lines So that the subpixels are displayed in a light gray scale. This is because the rising time of the voltage corresponding to the data signal supplied before the last of the screen driving is relatively fast as described above.

On the other hand, in the embodiment shown in FIG. 5, the data driver supplies data signals to be supplied to the (m-2) -th data line Dm-2 of the odd- The second data signal is copied and supplied. And the third data signal supplied to the third data line D3 is supplied by the data signal to be supplied to the first data line D1 of the even-numbered line.

In the case of the embodiment, the data signal supplied last in the screen driving is the m-th dummy pixel DPm of the first line -> the (m-1) -th subpixel SPm-1 of the second line - (M-1) th sub-pixel (SPm-1) of the fourth line. And the data signal supplied before the last scan on the screen is the (m-2) th subpixel (SPm-2) -> the (m-3) th subpixel (M-2) th sub-pixel (SPm-2) of the fourth line and the (m-3) th sub-pixel (Spm-3) of the fourth line.

Assuming that the black system is 10 and the white system is 250 in the embodiment, the output waveform of the data signal according to the driving method of the embodiment will be described numerically as follows.

Referring to (Dm) in FIG. 7, the data signal supplied last in the screen driving is the m-th dummy pixel DPm of the first line: "0" (M-1) th sub-pixel (SPm-1) of the fourth line: "250" .

Referring to (Dm-1) of FIG. 7, the data signal supplied before the last scan on the screen is the (m-2) th subpixel (SPm-2) of the first line: (M-3) th subpixel (SPm-3): "250" -> the (m-2) th subpixel Pixel (SPm-3): "250 ".

In the driving method according to the embodiment, as shown in (Dm) and (Dm-1) in FIG. 7, the data signal supplied last in the screen driving and the data signal supplied in the last The voltages corresponding to "0" and "250" are repeated. In this case, it can be seen that the rising time of the voltage corresponding to the data signal supplied last in the screen driving and the voltage corresponding to the data signal supplied before the last driving on the screen are the same.

When the data signal output from the data driver is the same, the liquid crystal panel should display the same black series value in the odd number lines and the same white series value in the even number lines. As shown in "PT" in FIG. 8 (b), in the embodiment, the (m-1) -th subpixels SPm-1 supplied with the data signal supplied before the last- The same gray level as the sub-pixels located in the sub-pixels. This is because the rising time of the voltage corresponding to the data signal supplied last in the screen driving and the data signal supplied last in the last time are the same as described above.

The above embodiment can solve the phenomenon that the specific area of the panel becomes brighter or darker than other areas when the fixed gradation is used as the dummy data in the black system or the white system solid pattern.

While the present invention has been described and illustrated in detail, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but may be modified in various forms without departing from the spirit of the invention. it is possible to provide a liquid crystal display device capable of eliminating the occurrence of flicker and a method of driving the same.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the following claims rather than the detailed description. Also, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

1 is a configuration diagram of a liquid crystal display device according to an embodiment of the present invention;

2 is a schematic layout diagram of sub pixels and dummy pixels arranged in a liquid crystal panel;

3 is a configuration diagram of a data driver;

4 is a diagram for explaining a comparative example;

5 is a view for explaining an embodiment of the present invention.

6 is an output waveform diagram of a data signal according to a comparative example;

7 is an output waveform diagram of a data signal according to the embodiment;

8 is a diagram showing a pattern pattern of a panel according to an output waveform of the data signal shown in FIG.

DESCRIPTION OF THE REFERENCE NUMERALS

110: liquid crystal panel 120: timing controller

130: Gate driver 140: Data driver

150: lamp driving part 160: lamp part

141: shift register 142: data register

143: first latch 144: second latch

145: digital / analog converter 146: output section

148:

Claims (8)

A liquid crystal panel including subpixels arranged in a matrix form in a display region and dummy pixels arranged in a non-display region; A gate driver for supplying a gate signal to the liquid crystal panel; A data driver for supplying a data signal to the liquid crystal panel; Gate wirings connected to the liquid crystal panel and transmitting gate signals output from the gate driver; And And data lines which are wired to the liquid crystal panel and transmit data signals output from the data driver, The data driver may include: The (m-2) -th data signal supplied to the (m-2) -th data line is copied and supplied to the m-th data line positioned at the last, and the third data signal supplied to the And supplying the data to the first data line, The dummy pixels may include, M-th dummy pixels arranged to correspond to odd-numbered rows of the m-th column so as to receive data signals from the m-th data wiring, and m-th dummy pixels arranged to correspond to odd rows of the first column to receive data signals from the first data wiring The first dummy pixels being arranged in a first direction, And the (m-2) -th data signal is supplied to the m-th dummy pixels and the third data signal is supplied to the first dummy pixels. delete delete The method according to claim 1, The data wirings, The subpixels arranged on the odd lines are wired so as to receive data signals from the data lines passing through the corresponding lines, And the subpixels arranged on the even-numbered lines are wired so as to receive data signals from the data lines passing through the next column. The method according to claim 1, Wherein the signal conversion unit comprises: The (m-2) th data signal and the first data signal are And controls the polarity control signal supplied to the data driver to be supplied to the mth data line and the first data line. The method according to claim 1, The sub- And the red, green, and blue subpixels are arranged in the direction in which the data lines are wired. Supplying a gate signal to gate wirings wired to the liquid crystal panel; And A data signal is supplied to the data lines wired to the liquid crystal panel, the (m-2) -th data signal supplied to the (m-2) -th data line is copied and supplied to the m-th data line positioned last, And supplying the third data signal to the first data line by copying the third data signal supplied to the third data line; And the (m-2) -th data signal is supplied to the m-th dummy pixels located in the non-display area of the liquid crystal panel, and the first data signal is supplied to the first dummy pixels To the liquid crystal display panel. delete

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