KR101667048B1 - Liquid crystal display - Google Patents

Abstract

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device in which data voltages whose polarity is inverted by a frame-inversion are supplied are provided. A backlight unit for emitting light to the liquid crystal display panel; A backlight driving unit driving the light sources of the backlight unit; And a backlight controller for controlling backlight luminance by supplying backlight dimming data to the backlight driver. The backlight controller controls the backlight luminance to be higher than the backlight luminance of the frame period in which the data voltage of the second polarity is supplied to the liquid crystal display panel during a frame period in which the data voltage of the first polarity is supplied to the liquid crystal display panel.

Description

[0001] LIQUID CRYSTAL DISPLAY [0002]

The present invention relates to a liquid crystal display device.

BACKGROUND ART [0002] Liquid crystal display devices are becoming increasingly widespread due to features such as light weight, thinness, and low power consumption driving. The liquid crystal display device is used as a portable computer such as a notebook PC, an office automation device, an audio / video device, and an indoor / outdoor advertisement display device. A liquid crystal display controls an electric field applied to liquid crystal cells to modulate light incident from a backlight unit to display an image.

The liquid crystal display device is driven in an inversion mode in which the polarity of the data voltage charged in the adjacent liquid crystal cells is opposite to each other and the polarity of the data voltage is periodically inverted in order to reduce direct current residual image and prevent deterioration of the liquid crystal.

The active matrix type liquid crystal display device includes a liquid crystal display panel including a TFT (Thin Film Transistor) formed for each pixel and switching a data voltage supplied to the pixel electrode, a data driving circuit for supplying a data voltage to the data lines of the liquid crystal display panel A gate driving circuit for sequentially supplying gate pulses (or scan pulses) to the gate lines of the liquid crystal display panel, and a timing controller for controlling the operation timing of the driving circuits.

1 is a diagram showing the polarity of a data voltage applied to a liquid crystal display in a frame inversion. 2 is a diagram showing the polarity of a data voltage applied to a liquid crystal display in a line inversion. 3 is a diagram showing the polarity of the data voltage applied to the liquid crystal display in the dot inversion.

In a frame-inversion such as the one shown in Fig. 1, all the output channels of the data driving circuit output data voltages of the same polarity for one frame period, and invert the data voltage to a period of one frame period. In the frame-inversion mode, all the liquid crystal cells in the liquid crystal display panel charge data voltages of the same polarity within one frame period.

2, all the output channels of the data driving circuit output data voltages of the same polarity within the same horizontal period and reverse the polarity of the data voltages to one horizontal period period and one frame period period. In the line inversion, the odd line liquid crystal cells and the even line liquid crystal cells of the liquid crystal display panel charge data voltages of opposite polarities.

3, the polarity of the data voltage output through the odd output channels of the data driving circuit and the polarity of the data voltage output through the output channels of the data driving circuit are opposite to each other. The polarity of the data voltage outputted through the output channels of the data driving circuit in the dot inversion is inverted to one horizontal period period and one frame period period. In the dot inversion, the polarities of the data voltages charged in the left and right liquid crystal cells adjacent to the left and right and the liquid crystal cells adjacent to the upper and lower sides are opposite to each other.

The power consumption of the liquid crystal display device increases as the number of times of reversal of the polarity of the data voltage increases, that is, as the current consumption increases in the data lines. Therefore, the power consumption of the liquid crystal display device is the smallest in frame inversion, relatively large in line inversion and dot inversion, and largest in dot inversion.

Frame inversion has lower power consumption than line inversion and dot inversion, but flicker is better observed than line inversion and dot inversion. This phenomenon will be described with reference to FIG.

4 is a waveform diagram showing output (SIC output data) and gate pulses of a data driving circuit in a line inversion or a dot inversion.

Referring to FIG. 4, the first liquid crystal cell is charged with the positive data voltage during the first horizontal period, and the negative data voltage is supplied to the second liquid crystal cell during the second horizontal period. The voltage (+ Vp) of the first liquid crystal cell charged with the positive polarity data voltage is lowered by? Vp due to the parasitic capacitance of the TFT or the like. On the other hand, the voltage (-Vp) of the second liquid crystal cell charged with the negative data voltage becomes higher by? Vp due to the parasitic capacitance of the TFT or the like. The liquid crystal cells in which the positive data voltage is charged and the liquid crystal cells in which the negative data voltage is charged are alternated in units of one line or one dot in the line inversion or dot inversion. Therefore, it is difficult for the observer to feel the luminance of the liquid crystal cell charged with the positive polarity data voltage and the luminance difference of the liquid crystal cell charged with the negative polarity data voltage in the line inversion or the dot inversion. 4, "GP1" means a first gate pulse generated during a first horizontal period, and "GP2" means a second gate pulse generated during a second horizontal period. "Vdata" is a data voltage output from the data driving circuit.

On the other hand, if the polarities of the data voltages charged in all of the liquid crystal cells are the same in one frame period in the frame-inversion mode, the observer can feel the flicker in which the luminance varies in one frame period. The display image may appear bright during the frame period in which the positive polarity data voltage is charged in the frame inversion according to the driving characteristics of the liquid crystal display device and the display image may appear bright during the frame period in which the negative polarity data voltage is charged.

The present invention provides a liquid crystal display device in which frame inversion is applied to reduce power consumption and prevent display quality degradation in a frame-inversion.

According to an aspect of the present invention, a liquid crystal display device of the present invention includes: a liquid crystal display panel to which data voltages whose polarity is inverted by a frame inversion are supplied; A backlight unit for emitting light to the liquid crystal display panel; A backlight driving unit driving the light sources of the backlight unit; And a backlight controller for controlling backlight luminance by supplying backlight dimming data to the backlight driver.

The backlight controller controls the backlight luminance to be higher than the backlight luminance of the frame period in which the data voltage of the second polarity is supplied to the liquid crystal display panel during a frame period in which the data voltage of the first polarity is supplied to the liquid crystal display panel.

The present invention can reduce the power consumption of the liquid crystal display device and prevent the deterioration of the display quality by applying the frame inversion and varying the backlight luminance according to the polarity change of the data voltage.

The liquid crystal display of the present invention may be implemented in a liquid crystal mode such as TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In Plane Switching) mode and FFS . The liquid crystal display device of the present invention can be realized in a Normally White mode or a Normally Black mode when it is classified into the transmittance versus voltage characteristics.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

The names of components used in the following description are selected in consideration of ease of specification, and may be different from actual product names.

5, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal display panel 100, a backlight unit 110, a backlight controller 104, a backlight driver 105, a timing controller 101, (102), and a gate driver (103).

In the liquid crystal display panel 100, a liquid crystal layer is formed between two glass substrates. The liquid crystal display panel 100 includes mxn liquid crystal cells arranged in a matrix form by an intersection structure of m data lines D1 to Dm and n gate lines G1 to Gn.

The TFT array 100 including the data lines D1 to Dm, the gate lines G1 to Gn, the TFTs, the pixel electrodes connected to the TFTs, and the storage capacitor Cst is formed on the lower glass substrate of the liquid crystal display panel 100, . Figs. 6 to 8 are views showing various examples of the TFT array. On the upper glass substrate of the liquid crystal display panel 100, a color filter array including a black matrix and a color filter is formed. A common electrode facing the pixel electrode with the liquid crystal cell interposed therebetween is formed on the upper glass substrate in a vertical electric field driving method such as a TN mode and a VA mode and is formed on the upper glass substrate in a horizontal electric field driving method such as an IPS mode and an FFS mode And is formed on the lower glass substrate.

On the upper glass substrate and the lower glass substrate of the liquid crystal display panel 100, a polarizing plate whose optical axis is orthogonal is attached. An alignment film for forming a pre-tilt angle of the liquid crystal is formed on the interface between the upper glass substrate and the lower glass substrate of the liquid crystal display panel 100 in contact with the liquid crystal layer.

The backlight unit 110 is disposed under the liquid crystal display panel 100. The backlight unit 110 includes a plurality of light sources that are turned on and off by the backlight driver 105 to uniformly irradiate light to the liquid crystal display panel 100. The backlight unit 110 may be implemented as a direct type backlight unit or an edge type backlight unit. The light source of the backlight unit 110 may include any one or two or more kinds of light sources such as a Hot Cathode Fluorescent Lamp (HCFL), a Cold Cathode Fluorescent Lamp (CCFL), an External Electrode Fluorescent Lamp (EEFL) have. The backlight driver 105 turns on and off the light sources of the backlight unit 110 in response to the backlight dimming data DIM input from the backlight controller 104 by a PWM (Pulse Width Modulation) method or a PAM (Pulse Amplitude Modulation) Turn off.

The backlight controller 104 analyzes the input image, calculates a representative value of the input image, selects backlight dimming data (DIM) according to the representative value, and modulates pixel data of the input image. The backlight controller 104 adjusts the backlight brightness according to the polarity of the data voltage supplied to the liquid crystal display panel 100 in the same manner as in Figs. 9 to 12, in order to reduce flicker in the frame inversion. The backlight controller 104 may be incorporated in the timing controller 101.

The timing controller 101 receives digital video data RGB from an external host computer via an interface such as a low voltage differential signaling (LVDS) interface and a transition minimized differential signaling (TMDS) interface. The timing controller 101 inputs digital video data RGB input from a host computer to the backlight controller 104 and supplies data R'G'B 'modulated by the backlight controller 104 to the data driver 102 .

The timing controller 101 receives a timing signal such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a clock CLK from the host computer through an LVDS or TMDS interface receiving circuit. . The timing controller 101 generates timing control signals GDC and DDC for controlling the operation timings of the data driving unit 102 and the gate driving unit 103 based on a timing signal input from the host computer. The timing control signals include a gate timing control signal GDC for controlling the operation timing of the gate driver 103, and a data timing control signal for controlling the operation timing of the data driver 102 and the polarity of the data voltage.

The gate timing control signal GDC includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, and the like. The gate start pulse GSP is applied to a gate drive IC (Integrated Circuit) which generates the first gate pulse to control the shift start timing of the gate drive IC. The gate shift clock GSC is a clock signal commonly input to the gate drive ICs, and is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output timing of the gate drive ICs.

The data timing control signal DDC includes a source start pulse SSP, a source sampling clock SSC, a polarity control signal POL, and a source output enable signal Source Output Enable, SOE). The source start pulse SSP is applied to the source drive IC for sampling the first pixel data among the source drive ICs of the data driver 102 to control the shift start timing. The source sampling clock SSC is a clock signal for controlling the sampling timing of data in the data driving circuit 102 on the basis of the rising or falling edge. The polarity control signal POL controls the polarity of the data voltage output from the source drive ICs. The source start pulse SSP and the source sampling clock SSC may be omitted if the digital video data to be input to the data driver 102 is transmitted in the mini LVDS interface standard.

The data driver 102 includes one or more source drive ICs. Each of the source drive ICs includes a shift register, a latch, a digital-to-analog converter, an output buffer, and the like. The source drive ICs latch digital video data (R'G'B ') under the control of the timing controller 101. The source drive ICs convert the digital video data (R'G'B ') to an analog positive gamma compensation voltage and a negative gamma compensation voltage to invert the polarity of the data voltage. Each of the source drive ICs is connected to the data lines of the liquid crystal display panel by a COG (Chip On Glass) process or a TAB (Tape Automated Bonding) process.

The gate driver 103 includes one or more gate drive ICs. The gate drive ICs include shift registers, level shifters, output buffers, and the like. The gate drive ICs sequentially supply gate pulses (or scan pulses) to the gate lines G1 to Gn in response to the gate timing control signals GDC. The gate drive ICs of the gate driver 103 are connected to the gate lines of the lower glass substrate of the liquid crystal display panel 100 through a TAP process or connected to gate lines of the lower glass substrate of the liquid crystal display panel 100 by a GIP As shown in FIG.

Figs. 6 to 8 are equivalent circuits showing various examples of the TFT array formed in the liquid crystal display panel 100. Fig.

In the TFT array shown in Fig. 6, each of the red subpixel R, the green subpixel G and the blue subpixel B is arranged along the column direction. Each of the TFTs applies a data voltage from the data lines D1 to D6 to the pixel electrodes of the liquid crystal cells arranged on the left side (or right side) of the data lines D1 to D6 in response to gate pulses from the gate lines G1 to G4, . In the TFT array shown in Fig. 3, one pixel includes a red sub-pixel R, a green sub-pixel G and a blue sub-pixel B neighboring along the row direction (or the line direction) orthogonal to the column direction . When the resolution of the TFT array shown in Fig. 4 is m x n, m x 3 (where 3 is RGB) data lines and n gate lines are required.

7, the number of data lines D1 to D4 required at the same resolution as the TFT array shown in Fig. 6 is reduced to 1/2 by sharing the same data lines in the sub-pixels neighboring in the line direction And the number of necessary source drive ICs can be reduced to 1/2. In this TFT array, red subpixels (R), green subpixels (G) and blue subpixels (B), respectively, are arranged along the column direction. One pixel in the TFT array shown in Fig. 7 includes red sub-pixel R, green sub-pixel G and blue sub-pixel G neighboring along the line direction orthogonal to the column direction. Two liquid crystal cells neighboring in the line direction share the same data line and sequentially charge the data voltages supplied through the data line. The liquid crystal cell and the TFT disposed on the left side of the data lines D1 to D4 are defined as the first liquid crystal cell and the first TFT (TFT1), respectively, and the liquid crystal cell and the TFT disposed on the right side of the data lines D1 to D4 The connection relationship of the TFTs (TFT1, TFT2) defined by the second liquid crystal cell and the second TFT (TFT2) will be described below. The first TFT TFT1 supplies a data voltage from the data lines D1 to D4 to the pixel electrodes of the first liquid crystal cell in response to gate pulses from the odd gate lines G1, G3, G5 and G7. The gate electrode of the first TFT (TFT1) is connected to the odd gate lines G1, G3, G5 and G7, and the drain electrode is connected to the data lines D1 to D4. The source electrode of the first TFT (TFT1) is connected to the pixel electrode of the first liquid crystal cell. The second TFT TFT2 supplies a data voltage from the data lines D1 to D4 to the pixel electrodes of the second liquid crystal cell in response to gate pulses from the even gate lines G2, G4, G6 and G8. The gate electrode of the second TFT (TFT2) is connected to the outermost gate lines G2, G4, G6 and G8, and the drain electrode is connected to the data lines D1 to D4. And the source electrode of the second TFT (TFT2) is connected to the pixel electrode of the second liquid crystal cell.

The TFT array shown in FIG. 8 can arrange the subpixels of the same color in the row direction to reduce the number of data lines required at the same resolution by 1/3 as compared with the TFT array shown in FIG. 6, The number can also be reduced to 1/3. In this TFT array, each of the red subpixel R, the green subpixel G and the blue subpixel B is arranged along the line direction. In the TFT array shown in Fig. 8, one pixel includes a red subpixel R, a green subpixel G and a blue subpixel G neighboring along the column direction. Each of the TFTs applies a data voltage from the data lines D1 to D6 to the pixel electrodes of the liquid crystal cells arranged on the left side (or right side) of the data lines D1 to D6 in response to gate pulses from the gate lines G1 to G6, .

The TFT arrays shown in FIGS. 6 to 8 illustrate some examples of the TFT array applicable to the present invention, but the present invention is not limited thereto and can be variously changed according to the panel driving characteristics.

9 is a waveform diagram illustrating a backlight control method according to the first embodiment of the present invention.

Referring to FIG. 9, the liquid crystal display of the present invention controls the polarity of the data voltage and controls the backlight luminance by PWM by a one-frame inversion method. The one-frame inversion method charges all the liquid crystal cells of the liquid crystal display panel 100 with data voltages of the same polarity within one frame period, and inverts the polarity of the data voltage in one frame period.

When the liquid crystal display device of the normally white mode is driven by the one-frame inversion method, the luminance of the odd frame periods (Fn, Fn + 2) to which the positive polarity data voltage is supplied is the odd frame data Is higher than the period (Fn + 1, Fn + 3). The backlight controller 104 is a backlight controller for supplying a positive data voltage to the liquid crystal display panel 100 during the odd frame period (Fn, Fn + 2) when the normally gray liquid crystal display device is driven by the one- The data value of the dimming data (DIM) is increased. The backlight driver 105 applies a duty ratio of the PWM signal in response to the backlight dimming data DIM during the odd frame period (Fn, Fn + 2) during which the positive polarity data voltage is supplied to the liquid crystal display panel 100 ) To raise the backlight luminance. 9, "A + a" is a backlight on time increased in accordance with an increased duty ratio during the odd frame period (Fn, Fn + 2) Fn + 3) is the backlight on time determined by the default duty ratio.

On the other hand, when the liquid crystal display device of the Normally Black mode is driven by the one-frame inversion method, the luminance of the even frame period (Fn + 1, Fn + 3) to which the negative data voltage is supplied becomes the positive polarity data voltage Is higher than the radix frame period (Fn, Fn + 2) to be supplied. When the liquid crystal display of the Normally Black mode is driven by the one-frame version method, the backlight controller 104 outputs the odd frame period (Fn + 1, Fn + 3) in which the negative data voltage is supplied to the liquid crystal display panel 100, The data value of the backlight dimming data (DIM) is increased. The backlight driver 105 increases the duty ratio of the PWM signal in response to the backlight dimming data DIM during the frame period Fn + 1 and Fn + 3 during which the negative data voltage is supplied to the liquid crystal display panel 100, Increase the brightness.

10 is a waveform diagram illustrating a backlight control method according to a second embodiment of the present invention.

Referring to FIG. 10, the liquid crystal display of the present invention controls the polarity of the data voltage and controls the backlight luminance by PWM by a version method in which N (N is a positive integer of 2 or more) frame. The N frame inversion method charges data voltages of the same polarity to all the liquid crystal cells of the liquid crystal display panel 100 during the N frame period and inverts the polarity of the data voltage at the N frame period.

When the liquid crystal display device of the normally white mode is driven by the N frame inversion method, the luminance of the frame period (Fn, Fn + 1) to which the positive polarity data voltage is supplied is the frame period Fn + 2, Fn + 3). The backlight controller 104 performs backlight dimming during the frame period (Fn, Fn + 1) in which the positive polarity data voltage is supplied to the liquid crystal display panel 100 when the normally white liquid crystal display device is driven by the one- Increases the data value of the data (DIM). The backlight driver 105 generates a duty ratio of the PWM signal in response to the backlight dimming data DIM during the odd frame periods Fn and Fn + 2 in which the positive polarity data voltage is supplied to the liquid crystal display panel 100 Thereby increasing the backlight luminance.

On the other hand, when the liquid crystal display of the Normally Black mode is driven by the N frame inversion method, the luminance of the frame periods (Fn + 2, Fn + 3) to which the negative data voltages are supplied is maintained Is higher than the frame period (Fn, Fn + 1). When the liquid crystal display of the Normally Black mode is driven by the N frame version method, the backlight controller 104 controls the backlight controller 104 during the frame period (Fn + 2, Fn + 3) during which the negative polarity data voltage is supplied to the liquid crystal display panel 100 The data value of the backlight dimming data (DIM) is increased. The backlight driver 105 increases the duty ratio of the PWM signal in response to the backlight dimming data DIM during the frame period (Fn + 2, Fn + 3) during which the negative data voltage is supplied to the liquid crystal display panel 100, .

11 is a waveform diagram showing a backlight control method according to the third embodiment of the present invention.

Referring to FIG. 11, the liquid crystal display of the present invention controls the polarity of the data voltage and controls the backlight luminance by using the PAM by a one frame inversion method.

When the liquid crystal display device of the normally white mode is driven by the one-frame inversion method, the luminance of the odd frame periods (Fn, Fn + 2) to which the positive polarity data voltage is supplied is the odd frame data Is higher than the period (Fn + 1, Fn + 3). The backlight controller 104 is a backlight controller for supplying a positive data voltage to the liquid crystal display panel 100 during the odd frame period (Fn, Fn + 2) when the normally gray liquid crystal display device is driven by the one- The data value of the dimming data (DIM) is increased. The backlight driver 105 increases the amplitude of the PAM signal in response to the backlight dimming data DIM during the odd frame period (Fn, Fn + 2) during which the positive polarity data voltage is supplied to the liquid crystal display panel 100 to increase the backlight luminance .

On the other hand, when the liquid crystal display device of the Normally Black mode is driven by the one-frame inversion method, the luminance of the even frame period (Fn + 1, Fn + 3) to which the negative data voltage is supplied becomes the positive polarity data voltage Is higher than the radix frame period (Fn, Fn + 2) to be supplied. When the liquid crystal display of the Normally Black mode is driven by the one-frame version method, the backlight controller 104 outputs the odd frame period (Fn + 1, Fn + 3) in which the negative data voltage is supplied to the liquid crystal display panel 100, The data value of the backlight dimming data (DIM) is increased. The backlight driver 105 increases the duty ratio of the PAM signal in response to the backlight dimming data DIM during the odd frame period (Fn + 1, Fn + 3) in which the negative data voltage is supplied to the liquid crystal display panel 100, Increase the brightness.

12 is a waveform diagram showing a backlight control method according to the fourth embodiment of the present invention.

Referring to FIG. 10, the liquid crystal display of the present invention controls the polarity of the data voltage and controls the backlight luminance by the PAM using the N frame inversion method.

When the liquid crystal display device of the normally white mode is driven by the N frame inversion method, the luminance of the frame period (Fn, Fn + 1) to which the positive polarity data voltage is supplied is the frame period Fn + 2, Fn + 3). The backlight controller 104 performs backlight dimming during the frame period (Fn, Fn + 1) in which the positive polarity data voltage is supplied to the liquid crystal display panel 100 when the normally white liquid crystal display device is driven by the one- Increases the data value of the data (DIM). The backlight driver 105 increases the amplitude of the PAM signal in response to the backlight dimming data DIM during the odd frame period (Fn, Fn + 2) during which the positive polarity data voltage is supplied to the liquid crystal display panel 100 to increase the backlight luminance .

On the other hand, when the liquid crystal display of the Normally Black mode is driven by the N frame inversion method, the luminance of the frame periods (Fn + 2, Fn + 3) to which the negative data voltages are supplied is maintained Is higher than the frame period (Fn, Fn + 1). When the liquid crystal display of the Normally Black mode is driven by the N frame version method, the backlight controller 104 controls the backlight controller 104 during the frame period (Fn + 2, Fn + 3) during which the negative polarity data voltage is supplied to the liquid crystal display panel 100 The data value of the backlight dimming data (DIM) is increased. The backlight driver 105 increases the amplitude of the PAM signal in response to the backlight dimming data DIM during the frame period (Fn + 2, Fn + 3) during which the negative data voltage is supplied to the liquid crystal display panel 100, Increase.

A liquid crystal display according to another embodiment of the present invention controls the polarity of a data voltage by a frame inversion method and controls the backlight luminance by a hybrid method using PWM and PAM. For example, the duty ratio of the PWM signal for controlling the backlight luminance can be increased during the frame period in which the positive data voltage (or the negative data voltage) is supplied, and the amplitude of the PWM signal can be increased.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

1 is a diagram showing the polarity of a data voltage applied to a liquid crystal display in a frame inversion.

2 is a diagram showing the polarity of a data voltage applied to a liquid crystal display in a line inversion.

3 is a diagram showing the polarity of the data voltage applied to the liquid crystal display in the dot inversion.

4 is a waveform diagram showing the output of the data driving circuit and the gate pulses in the line inversion or the dot inversion.

5 is a block diagram illustrating a liquid crystal display device according to an embodiment of the present invention.

6 to 8 are equivalent circuits showing various examples of the TFT array.

9 is a waveform diagram illustrating a backlight control method according to the first embodiment of the present invention.

10 is a waveform diagram illustrating a backlight control method according to a second embodiment of the present invention.

11 is a waveform diagram showing a backlight control method according to the third embodiment of the present invention.

12 is a waveform diagram showing a backlight control method according to the fourth embodiment of the present invention.

Description of the Related Art

100: liquid crystal display panel 102:

103: gate driver 104: backlight controller

105: Backlight driver

Claims (5)

A liquid crystal display panel to which data voltages whose polarities are inverted in frame inversion are supplied; A backlight unit for emitting light to the liquid crystal display panel; A backlight driving unit driving the light sources of the backlight unit; And And a backlight controller for supplying backlight dimming data to the backlight driver to control the backlight brightness, The backlight controller controls the backlight luminance to be higher than the backlight luminance of the frame period in which the data voltage of the second polarity is supplied to the liquid crystal display panel during a frame period in which the data voltage of the first polarity is supplied to the liquid crystal display panel . The method according to claim 1, The backlight controller includes: The first backlight dimming data value for controlling the backlight luminance during a frame period in which the data voltage of the first polarity is supplied to the liquid crystal display panel is supplied to the liquid crystal display panel during the frame period in which the data voltage of the second polarity is supplied, And a second backlight dimming data value for controlling the brightness. 3. The method of claim 2, The backlight driver includes: And increases the duty ratio of the PWM signal for turning on and off the light sources of the backlight unit in response to the first backlight dimming data value. 3. The method of claim 2, The backlight driver includes: And increases the amplitude of the PAM signal for turning on and off the light sources of the backlight unit in response to the first backlight dimming data value. 3. The method of claim 2, The backlight driver includes: And increases the duty ratio and amplitude of the PWM signal for turning on and off the light sources of the backlight unit in response to the first backlight dimming data value.

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