KR20010062477A - Dielectric filling electric wiring planes - Google Patents
Dielectric filling electric wiring planes Download PDFInfo
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- KR20010062477A KR20010062477A KR1020000076961A KR20000076961A KR20010062477A KR 20010062477 A KR20010062477 A KR 20010062477A KR 1020000076961 A KR1020000076961 A KR 1020000076961A KR 20000076961 A KR20000076961 A KR 20000076961A KR 20010062477 A KR20010062477 A KR 20010062477A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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Abstract
Description
본 발명은 집적 회로내 전기 와이어링 평면의 유전체 충전에 관한 것이다.The present invention relates to dielectric charging of electrical wiring planes in integrated circuits.
집적 회로는 대부분 기판상에 층으로 배치되는 다수의 개별 구조들로 구성된다. 통상 저항, 커패시터, 다이오드, 트랜지스터 등과 같은 전자 부품은 기판 내에 제조된다. 그런 다음 그 위에 놓인 와이어링 평면(소위 금속 증착 평면) 내에 개별 부품의 전기 회로 설계가 실시된다.Integrated circuits consist of a number of discrete structures, most of which are arranged in layers on a substrate. Typically, electronic components such as resistors, capacitors, diodes, transistors, etc. are manufactured in the substrate. The electrical circuit design of the individual components is then carried out in the wiring plane (so-called metal deposition plane) which lies above it.
전기 와이어링에 사용되는 방법은 기판 상에 도전층을 디포짓하는 것이다. 이어서 상기 도전층은 도체 레일이 그 사이에 놓인 트렌치에 의해 형성되도록 포토리소그래피에 의해 구조화된다. 통상 상기 트렌치는 실리콘 산화물로 된 유전체로 채워진다. 이를 위해 예컨대 붕소 규산염 유리, 인 규산염 유리 또는 비소 규산염 유리 내지는 상기 물질의 혼합물과 같이 도핑된 실리콘 산화물이 사용된다. 도핑된 규산염 유리는 높은 온도에서 유동하는 특성을 갖는다. 그로 인해 트렌치가 절연 유전체로 채워질 수 있다.The method used for electrical wiring is to deposit a conductive layer on a substrate. The conductive layer is then structured by photolithography such that the conductor rails are formed by trenches sandwiched therebetween. Typically the trench is filled with a dielectric of silicon oxide. For this purpose doped silicon oxides are used, for example boron silicate glass, phosphorus silicate glass or arsenic silicate glass or mixtures of the above materials. Doped silicate glass has the property of flowing at high temperatures. This allows the trench to be filled with an insulating dielectric.
물론 도핑된 규산염 유리는 약 4 정도의 높은 유전 상수를 갖는다는 단점이 있다. 높은 유전 상수는 전기 접속 라인으로 신호를 전파하는 속도에 악영향을 끼치며, 상기 접속 라인은 높은 유전 상수에 의해 큰 정전 용량을 가진다. 큰 정전 용량은 긴 RC-시간을 초래한다. 긴 RC-시간의 문제는 차후에 더 첨예화된다. 그 이유는 부품이 점점 작아지고 있는 추세에 따라 개별 도체 레일 사이의 간격도 계속 줄어들고 있으며, 이는 정전 용량을 더 크게 하기 때문이다.Of course doped silicate glass has a disadvantage of having a high dielectric constant of about four. The high dielectric constant adversely affects the rate of propagation of the signal to the electrical connection line, which has a large capacitance due to the high dielectric constant. Large capacitance results in long RC-times. The problem of long RC-times is further compounded later. The reason is that as parts get smaller, the spacing between individual conductor rails continues to shrink, which leads to greater capacitance.
전기 회로가 지속적으로 축소됨에 따른 또 다른 문제는 도핑된 규소 유리의 유동성이 제한된다는 점이다. 그로 인해 도체 레일들 사이의 트렌치가 점점 더 좁아지면 도핑된 규소 유리가 더 이상 다다를 수 없는 공동이 형성된다. 상기 공동은 습기를 축적시키는 바람직하지 않은 특성을 가지고 있다. 예컨대 납땜시 집적 회로가 거치게 되는 온도 단계에서, 상기 집적 회로는 축적된 습기의 증발에 의해폭발함에 따라 사용할 수 없게 된다.Another problem as the electrical circuit continues to shrink is that the flowability of the doped silicon glass is limited. As a result, the trench between conductor rails becomes narrower, creating a cavity in which the doped silicon glass can no longer reach. The cavity has the undesirable property of accumulating moisture. For example, in a temperature step where an integrated circuit passes through during soldering, the integrated circuit becomes unusable as it explodes by evaporation of accumulated moisture.
또 다른 단점은 도핑된 규소 유리층의 높은 반사율로 인해 후속하는 리소그래피 단계에서 잘못된 노광 및 잘못된 프로세싱이 야기될 수 있다는 점이다.Another drawback is that the high reflectivity of the doped silicon glass layer can result in incorrect exposure and incorrect processing in subsequent lithography steps.
본 발명의 목적은 바람직한 충전 특성 및 유동 특성, 낮은 유전 상수 및 포토리소그래피 단계시 반사 억제 특성을 갖는, 집적 회로의 전기 와이어링 평면을 위한 유전층을 제공하는 것이다.It is an object of the present invention to provide a dielectric layer for the electrical wiring plane of an integrated circuit having desirable charging and flow characteristics, low dielectric constant and reflection suppression characteristics during the photolithography step.
도 1은 선행 기술에 따른 전기 와이어링을 위한 층 구조.1 is a layer structure for electrical wiring according to the prior art;
도 2는 본 발명에 따른 층 구조의 제 1 실시예.2 shows a first embodiment of a layer structure according to the invention.
도 3은 본 발명에 따른 층 구조의 제 2 실시예.3 shows a second embodiment of a layer structure according to the invention.
도면의 주요 부호 설명Description of the major signs in the drawings
1 : 본체 6 : 제 1 유전층1 main body 6 first dielectric layer
2 : 도전층 7 : 실리콘 산화물층2: conductive layer 7: silicon oxide layer
3 : 제 1 도체 레일 8 : 실리콘 질화물층3: first conductor rail 8: silicon nitride layer
4 : 제 2 도체 레일 9 : 제 2 유전층4: second conductor rail 9: second dielectric layer
5 : 트렌치5: trench
상기 목적은 본 발명에 따라The object according to the present invention
- 본체;- main body;
- 도전층으로서, 상기 본체 위에 배치되고, 제 1 도체 레일, 제 2 도체 레일 및 상기 두 도체 레일 사이의 트렌치를 포함하도록 구조화된 도전층;A conductive layer disposed over the body and structured to include a first conductor rail, a second conductor rail and a trench between the two conductor rails;
- 상기 도전층 위에 배치되고 트렌치를 적어도 부분적으로 채우며, 중합체 재료인 폴리벤조옥사졸 및/또는 폴리노르보르넨 및/또는 이들의 유도체 중 하나를 포함하는 제 1 유전층을 갖는 집적 회로의 전기 와이어링에 의해 달성된다.Electrical wiring of an integrated circuit having a first dielectric layer disposed over the conductive layer and at least partially filling the trench and comprising one of the polymeric materials polybenzoxazole and / or polynorbornene and / or derivatives thereof. Is achieved by.
폴리벤조옥사졸 외에도 마찬가지로 스핀-온 방법에 의해 웨이퍼상에 디포짓될 수 있는 다른 물질들도 적합하다. 여기에는 수소 실세퀴옥산과 같은 무기 물질 및 폴리벤조옥사졸, 폴리이미드, 페릴렌, 폴리노르보르넨 및 폴리테트라플루오로에틸렌과 같은 유기 물질 및 그들의 유도체, 특히 플루오르화 유도체가 속한다.In addition to polybenzoxazoles, other materials which can likewise be deposited on the wafer by the spin-on method are also suitable. These include inorganic materials such as hydrogen silsesquioxane and organic materials such as polybenzoxazoles, polyimides, perylenes, polynorbornene and polytetrafluoroethylene and their derivatives, in particular fluorinated derivatives.
상기 방법과 관련된 목적은The purpose associated with the method is
- 본체(1) 위에 도전층(2)을 형성하는 단계;Forming a conductive layer 2 on the body 1;
- 제 1 도체 레일(3), 제 2 도체 레일(4) 및 상기 두 도체 레일 사이의 트렌치(5)가 형성되도록 상기 도전층(2)을 구조화하고, 이 때 폴리벤조옥사졸 및/또는 폴리노르보르넨 및/또는 이들의 유도체 중 하나를 포함하는 중합체로 이루어진 제 1 유전층(6)이 상기 도전층(2) 위에 스핀-온 디포짓됨으로써 상기 트렌치(5)가 적어도 부분적으로 충전되는 단계를 포함하는, 집적 회로의 전기 와이어링 제조 방법에 의해 달성된다.The conductive layer 2 is structured such that a first conductor rail 3, a second conductor rail 4 and a trench 5 between the two conductor rails are formed, wherein the polybenzoxazole and / or poly A step of filling the trench 5 at least partially by spin-on depositing a first dielectric layer 6 made of a polymer comprising norbornene and / or one of its derivatives on the conductive layer 2 It is achieved by a method for manufacturing electrical wiring of an integrated circuit.
바람직한 실시예는 각각의 종속항에 제시되어있다.Preferred embodiments are set forth in the respective dependent claims.
중합체 재료인 폴리벤조옥사졸(PBO)는 스핀 코팅(spin coating)에 의해 도포될 수 있기 때문에 아주 작은 틈까지 공동없이 채워질 수 있다는 특징을 갖는다. 따라서 HAST-테스트(Humidity Accelleration Stress Test)에서 습기를 축적하고 후속하는 온도 단계에서 폭발될 수 있는(팝콘-효과) 공동의 형성이 예방된다. 이러한 뛰어난 평탄화 특성 외에도 폴리벤조옥사졸은 경화 후에 400℃ 이상까지 내열성 및 낮은 수분 흡수율을 갖는다. 또한 폴리벤조옥사졸의 유전 상수는 경화된 상태에서 2.9 미만이다. 작은 유전 상수는 소수의 기생 커패시터에 의한, 집적 회로의 빠른 신호를 가능하게 한다. 또한 폴리벤조옥사졸은 그의 흡수 특성을 통해 후속하는 포토리소그래피 코팅 단계시 반사를 억제한다. 그로 인해 후속하는 포토리소그래피 단계시 확실히 개선된 융해도가 달성된다.Polybenzoxazole (PBO), a polymeric material, is characterized by being able to be applied by spin coating, so that even small gaps can be filled without cavities. This prevents the formation of cavities that accumulate moisture in the HAST-Test (Humidity Accelleration Stress Test) and can explode in subsequent temperature steps (popcorn-effect). In addition to these excellent planarization properties, polybenzoxazoles have heat resistance and low water absorption up to 400 ° C. or higher after curing. In addition, the dielectric constant of polybenzoxazole is less than 2.9 in the cured state. Small dielectric constants enable fast signals in integrated circuits with few parasitic capacitors. Polybenzoxazoles also inhibit their reflection during subsequent photolithographic coating steps through their absorption properties. This ensures that improved meltability is achieved in subsequent photolithography steps.
본 발명에 따른 장치의 개선된 제조에서는 유전층의 상부에 실리콘 질화물 층이 배치된다. 상기 실리콘 질화물 층은 수증기, 알칼리 이온 및 기타 부식성 물질에 대한 뛰어난 보호 작용을 하는 패시베이션층으로서 사용될 수 있다.In an improved manufacture of the device according to the invention, a silicon nitride layer is arranged on top of the dielectric layer. The silicon nitride layer can be used as a passivation layer that provides excellent protection against water vapor, alkali ions and other corrosive substances.
본 발명에 따른 장치의 제 2 개선예에서는 제 1 유전층과 실리콘 질화물 층 사이에 실리콘 산화물 층이 배치된다.In a second refinement of the device according to the invention, a silicon oxide layer is arranged between the first dielectric layer and the silicon nitride layer.
본 발명에 따른 장치의 제 3 개선예에서는 제 1 유전층의 상부에 폴리벤조옥사졸 또는 감광성 폴리이미드로 이루어진 제 2 유전층이 배치된다.In a third refinement of the device according to the invention, a second dielectric layer consisting of polybenzoxazole or photosensitive polyimide is arranged on top of the first dielectric layer.
본 발명의 실시예는 도면을 참고로 하기에 자세히 설명된다.Embodiments of the present invention are described in detail below with reference to the drawings.
도 1에는 선행 기술에 따른 전기 와이어링의 층 구조가 도시되어있다. 저항, 커패시터, 다이오드, 트랜지스터, 패시베이션 층 등과 같은 전자 부품이 미리 포함되어있을 수 있는 본체(1)상에 도전층(2)이 디포짓된다. 통상 도전층(2)은 알루미늄이나 구리와 같은 금속으로 형성된다. 상기 도전층은 제 1 도체 레일(3), 제 2 도체 레일(4) 및 상기 두 도체 레일 사이에 놓인 트렌치(5)가 형성되도록 구조화된다. 이어서 도핑된 규산염 유리가 디포짓되고, 온도 단계를 거쳐 트렌치(5)를 충전하여 실리콘 산화물 층(7)을 형성한다. 이어서 상기 실리콘 산화물 층(7) 위에 뛰어난 보호 효과를 나타내는 패시베이션 층으로서 실리콘 질화물 층(8)이 형성된다. 그런 다음 상기 실리콘 질화물 층(8) 위에 제 2 유전층(9)이 형성된다. 상기 제 2 유전층(9)은 포토 레지스트 층으로서 사용되며, 예컨대 폴리이미드, 감광성 폴리이미드, 폴리이미드 유도체, 폴리벤조옥사졸, 감광성 폴리벤조옥사졸 또는 폴리벤조옥사졸 유도체로 구성된다.1 shows the layer structure of electrical wiring according to the prior art. A conductive layer 2 is deposited on the body 1, which may contain previously electronic components such as resistors, capacitors, diodes, transistors, passivation layers and the like. Usually, the conductive layer 2 is formed of a metal such as aluminum or copper. The conductive layer is structured such that a first conductor rail 3, a second conductor rail 4 and a trench 5 lying between the two conductor rails are formed. The doped silicate glass is then deposited and subjected to a temperature step to fill the trench 5 to form the silicon oxide layer 7. Subsequently, a silicon nitride layer 8 is formed on the silicon oxide layer 7 as a passivation layer exhibiting an excellent protective effect. A second dielectric layer 9 is then formed over the silicon nitride layer 8. The second dielectric layer 9 is used as a photoresist layer and is composed of, for example, polyimide, photosensitive polyimide, polyimide derivative, polybenzoxazole, photosensitive polybenzoxazole or polybenzoxazole derivative.
도 2의 경우 트렌치(5)를 충전하고 도전층(2)을 커버함으로써 제 1 도체 레일(3) 및 제 2 도체 레일(4)을 커버하기 위해 제 1 유전층(6)이 사용된다는 점에서도 1과 차이가 있다. 제 1 유전층(6)에 있어서 예컨대 중합체 재료인 폴리벤조옥사졸이 고려된다. 폴리벤조옥사졸로 이루어진 제 1 유전층(6)의 본 발명에 따른 장점은 2.9 미만의 낮은 유전 상수 및 후속하는 리소그래피 단계시 반사를 감소시키는 것과 같은 뛰어난 충전 특성에 있다.In the case of FIG. 2, the first dielectric layer 6 is also used to cover the first conductor rail 3 and the second conductor rail 4 by filling the trench 5 and covering the conductive layer 2. There is a difference. In the first dielectric layer 6, polybenzoxazole, for example a polymer material, is contemplated. The advantage according to the invention of the first dielectric layer 6 made of polybenzoxazole lies in its low dielectric constant of less than 2.9 and excellent filling properties such as reducing reflections in subsequent lithography steps.
도 3의 경우 유전층(6) 위에 실리콘 질화물 층(8)이 형성된다. 이와 달리 도 2에 도시된 실시예에서는 먼저 실리콘 산화물 층(7)이 유전층(6) 위에 형성된 다음, 그 위에 실리콘 질화물 층(8)이 형성된다.3, a silicon nitride layer 8 is formed over the dielectric layer 6. In contrast, in the embodiment shown in FIG. 2, a silicon oxide layer 7 is first formed over the dielectric layer 6, and then a silicon nitride layer 8 is formed thereon.
또 다른 장점은 빈번하게 기계적 변형을 일으키는 실리콘 질화물 층(8)에 대해 상기 유전층(6)이 응력 감소층으로서 작용함에 따라, 실리콘 질화물 층의 기계적 응력에 의해 야기되는 집적적인 문제가 감소되거나 제거된다는 점이다. 그밖에도 도 3의 유전층(6)의 두께가 도 1의 실리콘 산화물 층(7)의 두께보다 더 얇게 형성될 수 있기 때문에, 패시베이션 층의 개방을 위해 후속되는 건식 에칭 단계의 소요 시간이 더 짧아짐에 따라 더 경제적이다.Another advantage is that as the dielectric layer 6 acts as a stress reducing layer for the silicon nitride layer 8 which frequently causes mechanical deformation, the integrated problems caused by the mechanical stress of the silicon nitride layer are reduced or eliminated. Is the point. In addition, since the thickness of the dielectric layer 6 of FIG. 3 can be made thinner than that of the silicon oxide layer 7 of FIG. 1, the time required for the subsequent dry etching step for opening the passivation layer is shorter. It is more economical accordingly.
본 발명에 의해 바람직한 충전 특성 및 유동 특성, 낮은 유전 상수 및 포토리소그래피 단계시 반사 억제 특성을 갖는, 집적 회로의 전기 와이어링 평면을 위한 유전층을 제공하는 것이 보증된다.It is ensured by the present invention to provide a dielectric layer for the electrical wiring plane of an integrated circuit having desirable charging and flow characteristics, low dielectric constant and reflection suppression characteristics during the photolithography step.
Claims (10)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19961103.3 | 1999-12-17 | ||
| DE19961103A DE19961103C2 (en) | 1999-12-17 | 1999-12-17 | Dielectric filling of electrical wiring levels and method for producing electrical wiring |
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| Publication Number | Publication Date |
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| KR20010062477A true KR20010062477A (en) | 2001-07-07 |
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| KR1020000076961A KR20010062477A (en) | 1999-12-17 | 2000-12-15 | Dielectric filling electric wiring planes |
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| US (1) | US6380076B2 (en) |
| EP (1) | EP1109220A3 (en) |
| JP (1) | JP2001230505A (en) |
| KR (1) | KR20010062477A (en) |
| DE (1) | DE19961103C2 (en) |
| TW (1) | TW492110B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6413827B2 (en) | 2000-02-14 | 2002-07-02 | Paul A. Farrar | Low dielectric constant shallow trench isolation |
| US6677209B2 (en) | 2000-02-14 | 2004-01-13 | Micron Technology, Inc. | Low dielectric constant STI with SOI devices |
| US6890847B1 (en) * | 2000-02-22 | 2005-05-10 | Micron Technology, Inc. | Polynorbornene foam insulation for integrated circuits |
| DE10155802B4 (en) * | 2001-11-14 | 2006-03-02 | Infineon Technologies Ag | Semiconductor chip with FIB protection |
| US20050077540A1 (en) * | 2002-01-25 | 2005-04-14 | Axel Hulsmann | Integrated circuit arrangement |
| US20040253837A1 (en) * | 2003-06-10 | 2004-12-16 | Yu-Hao Yang | Method for forming a dielectric layer of a semiconductor |
| TW200609118A (en) * | 2004-05-21 | 2006-03-16 | Jsr Corp | Laminated body and semiconductor device |
| KR100598991B1 (en) | 2005-06-29 | 2006-07-12 | 주식회사 하이닉스반도체 | Composition for forming interlayer dielectric and forming process of interlayer dielectric using thereof |
| CN101080813A (en) * | 2005-07-07 | 2007-11-28 | 松下电器产业株式会社 | Multilayer wiring structure and method for forming same |
| US7927948B2 (en) | 2005-07-20 | 2011-04-19 | Micron Technology, Inc. | Devices with nanocrystals and methods of formation |
| JP6248392B2 (en) | 2013-01-17 | 2017-12-20 | 富士電機株式会社 | Semiconductor device |
| CN108257934B (en) | 2016-12-29 | 2021-02-19 | 联华电子股份有限公司 | Method for manufacturing welding pad opening and fuse welding opening and welding pad opening structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPS512125A (en) * | 1974-06-22 | 1976-01-09 | Jidosha Kiki Co | DORYOKUKAJITORISOCHINO SEIGYOBENSOCHI |
| GB1590723A (en) * | 1976-08-03 | 1981-06-10 | Raychem Ltd | Hv insulation materials |
| JPS6185844A (en) * | 1984-09-28 | 1986-05-01 | シーメンス、アクチエンゲゼルヤフト | Integrated circuit and making thereof |
| DE3802403A1 (en) * | 1988-01-28 | 1989-08-10 | Licentia Gmbh | SEMICONDUCTOR ARRANGEMENT WITH POLYIMIDE PASSIVATION |
| JP3006218B2 (en) * | 1991-10-08 | 2000-02-07 | 日立化成工業株式会社 | Semiconductor device and composition for interlayer insulating film and / or surface protective film for semiconductor multilayer wiring |
| JPH08139194A (en) * | 1994-04-28 | 1996-05-31 | Texas Instr Inc <Ti> | Manufacture of electrical connection onto semiconductor device and semiconductor device with electrical connection manufactured by said method |
| US5512514A (en) * | 1994-11-08 | 1996-04-30 | Spider Systems, Inc. | Self-aligned via and contact interconnect manufacturing method |
| JP3789545B2 (en) * | 1995-10-09 | 2006-06-28 | ソニー株式会社 | Formation method of insulating film |
| US6010956A (en) * | 1996-02-29 | 2000-01-04 | Tokyo Ohka Kogyo Co., Ltd. | Process for producing multilayer wiring boards |
| KR100205318B1 (en) * | 1996-10-11 | 1999-07-01 | 구본준 | Manufacture of low dielectric isolation film of low |
| US5763016A (en) * | 1996-12-19 | 1998-06-09 | Anon, Incorporated | Method of forming patterns in organic coatings films and layers |
| US6117763A (en) * | 1997-09-29 | 2000-09-12 | Advanced Micro Devices, Inc. | Method of manufacturing a semiconductor device with a low permittivity dielectric layer and contamination due to exposure to water |
| JPH11181094A (en) * | 1997-12-24 | 1999-07-06 | Sumitomo Bakelite Co Ltd | Production of fluorine-containing polybenzoxazole and its use |
| KR100635685B1 (en) * | 1998-05-25 | 2006-10-17 | 가부시키가이샤 히타치세이사쿠쇼 | Semiconductor equipment and fabrication method thereof |
| SG104255A1 (en) * | 1998-09-29 | 2004-06-21 | Sumitomo Bakelite Co | Polybenzoxazole resin and precursor thereof |
| US6235628B1 (en) * | 1999-01-05 | 2001-05-22 | Advanced Micro Devices, Inc. | Method of forming dual damascene arrangement for metal interconnection with low k dielectric constant materials and oxide middle etch stop layer |
| US6187668B1 (en) * | 1999-07-06 | 2001-02-13 | United Microelectronics Corp. | Method of forming self-aligned unlanded via holes |
-
1999
- 1999-12-17 DE DE19961103A patent/DE19961103C2/en not_active Expired - Fee Related
-
2000
- 2000-12-07 EP EP00126887A patent/EP1109220A3/en not_active Withdrawn
- 2000-12-13 JP JP2000379303A patent/JP2001230505A/en active Pending
- 2000-12-15 KR KR1020000076961A patent/KR20010062477A/en not_active Application Discontinuation
- 2000-12-15 TW TW089126871A patent/TW492110B/en not_active IP Right Cessation
- 2000-12-18 US US09/741,308 patent/US6380076B2/en not_active Expired - Lifetime
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| Publication number | Publication date |
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| EP1109220A2 (en) | 2001-06-20 |
| DE19961103A1 (en) | 2001-07-05 |
| US6380076B2 (en) | 2002-04-30 |
| JP2001230505A (en) | 2001-08-24 |
| DE19961103C2 (en) | 2002-03-14 |
| TW492110B (en) | 2002-06-21 |
| EP1109220A3 (en) | 2003-12-17 |
| US20010004539A1 (en) | 2001-06-21 |
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