KR100244801B1 - Method for manufacturing semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device without deforming the metal wiring film while using the interlayer insulating film as a film having low dielectric constant.

The present invention provides a method for manufacturing a semiconductor device, the method comprising: (a) forming a semiconductor substrate on which a gate and a junction region are formed; (b) forming a first interlayer insulating film on the semiconductor substrate; (c) forming an etch stop layer on the first interlayer insulating film; (d) forming a contact hole by etching the first interlayer insulating layer and the etch stop layer to expose a predetermined portion of the junction region; (e) forming a first metal wire on the etch stop layer to contact the exposed junction region; (f) forming a second interlayer insulating film on the etch stop layer on which the first metal wiring is formed; (g) forming a via hole by etching the second interlayer insulating layer to expose a predetermined portion of the first metal wire; (h) forming a second metal wiring on the second interlayer insulating film to be in contact with the exposed first metal wiring; (i) selectively removing the second interlayer insulating film; (j) filling an insulating film having a low dielectric constant in a portion where the second interlayer insulating film is removed, wherein the dielectric constant of the insulating film having the low dielectric constant is 2 to 4.

Description

Manufacturing method of semiconductor device

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing an interlayer insulating film of a semiconductor device.

In general, the performance of a semiconductor device depends on the signal delay time (T = R (resistance) × C (capacity)).

Conventionally, a material having a low specific resistance is used as the metal wiring film, and an insulating film having a low capacitance, that is, a low dielectric constant (ε = 2 to 4), is also used as the interlayer insulating film.

Here, a conventional multilayer metal wiring method will be described with reference to FIG. 1.

As shown in the figure, an element isolation film 2 is formed on the semiconductor substrate 1 to separate the element regions, and in the element region, the transistor 3 composed of the gate 3a and the junction regions 3b and 3c is known. Is formed in a manner. Then, the first interlayer insulating film 4 is deposited to a predetermined thickness on the semiconductor substrate resultant. Subsequently, the first interlayer insulating film 4 is partially etched to expose the junction regions 3b and 3c to form contact holes. Thereafter, in the contact hole, the first plug 5 is embedded and formed in a known manner, and then the first metal wiring 6 is formed to be in contact with the plug. Thereafter, after the second interlayer insulating film 7 is deposited, a via hole is formed so that a predetermined portion of the first metal wiring 6 is exposed. Subsequently, after the second plug 8 is formed in a known manner in the via hole, the second metal wiring 9 is formed to be in contact with the second plug 8.

Here, an aluminum metal film having excellent conductivity may be used as the first and second metal wiring films 6 and 9, and an oxide film or a planarization film may be used as the first and second interlayer insulating films 4 and 7.

As described above, when the oxide film or the oxide film-based planarization film is used as the first and second interlayer insulating films 4 and 7, the F (fluorine) ions can be implanted in order to achieve the dielectric constant of the interlayer insulating film. However, in such a case, F ions may cause corrosion of the metal wiring.

Therefore, another method for shortening the signal delay time of the conventional semiconductor device is a method of laminating and using the resin film 7a and the oxide film 7b as the second interlayer insulating film 7, as shown in FIG. This has been proposed. Here, since the dielectric constant of the resin film 7a is 2 to 4, the dielectric constant of the resin film 7a is much lower than that of the general silicon oxide film. At this time, since the first interlayer insulating film 4 must be in contact with the transistor 3, a resin film having a low dielectric constant is not used.

As described above, the signal delay time of the semiconductor element can be reduced by using a resin film having a low dielectric constant as the interlayer insulating film between the metal wirings in the multilayer metal wiring process.

However, the prior art using a resin film as an interlayer insulating film has the following problems.

That is, the resin film having the low dielectric constant may have a reduced stability at the deposition temperature upon subsequent metal wiring formation after application, and thus may not be adhered to the strain or the lower layer.

Further, at this heat treatment temperature, the previously formed first plug 5 and the first metal wiring film 6 reach the melting point (660 ° C.), which makes it difficult to maintain the shape.

Accordingly, it is an object of the present invention to provide a method for manufacturing a semiconductor device in which an interlayer insulating film is used as a film having a low dielectric constant and no deformation of the insulating film at the time of metal wiring formation.

1 and 2 are diagrams for explaining a conventional method for manufacturing a semiconductor device.

3A to 3E are cross-sectional views of respective manufacturing processes for explaining a method of manufacturing a semiconductor device according to the present invention.

4 is a cross-sectional view for explaining another embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

11 semiconductor substrate 12 device isolation film

13: transistor 14: first interlayer insulating film

15 silicon nitride film 16 first plug

17 first metal wiring 18 second interlayer insulating film

19: second plug 20: second metal wiring

21: insulating film with low dielectric constant

In order to achieve the above object of the present invention, the present invention, (a) forming a semiconductor substrate having a gate and a junction region formed; (b) forming a first interlayer insulating film on the semiconductor substrate; (c) forming an etch stop layer on the first interlayer insulating film; (d) forming a contact hole by etching the first interlayer insulating layer and the etch stop layer to expose a predetermined portion of the junction region; (e) forming a first metal wire on the etch stop layer to contact the exposed junction region; (f) forming a second interlayer insulating film on the etch stop layer on which the first metal wiring is formed; (g) forming a via hole by etching the second interlayer insulating layer to expose a predetermined portion of the first metal wire; (h) forming a second metal wiring on the second interlayer insulating film to be in contact with the exposed first metal wiring; (i) selectively removing the second interlayer insulating film; (j) filling an insulating film having a low dielectric constant in a portion where the second interlayer insulating film is removed, wherein the dielectric constant of the insulating film having the low dielectric constant is 2 to 4.

According to the present invention, a multi-layer metal wiring is formed with a silicon oxide interlayer insulating film therebetween, the interlayer insulating film is removed by an etching solution, and a film having a low dielectric constant is filled in the removed portion. The capacitance will be lowered.

EXAMPLE

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3A through 3E are cross-sectional views of respective manufacturing processes for describing a method of manufacturing a semiconductor device according to the present invention, and FIG. 4 is a cross-sectional view illustrating another embodiment of the present invention.

First, referring to FIG. 3A, a transistor including a gate 13a and junction regions 13b and 13c is formed in an element region of a semiconductor substrate 11 in which an element isolation layer 12 is formed to separate an element region and a field region. 13) is formed in a known manner. Then, the first interlayer insulating film 14, for example, a silicon oxide film-based insulating film is deposited on the resultant semiconductor substrate 11 to a predetermined thickness. Thereafter, the first interlayer insulating film 14 is subjected to a chemical mechanical polishing process so that the surface is planarized. Subsequently, an insulating film having a different etching rate from the first interlayer insulating film 14, for example, a silicon nitride film 15 or a boron nitride film is deposited on the first interlayer insulating film 14 to a predetermined thickness.

Thereafter, as shown in FIG. 3B, the silicon nitride film 15 and the first interlayer insulating film 14 are etched to expose predetermined portions of the junction regions 13b and 13c to form contact holes (not shown). do. Thereafter, the first plug 16 is formed in the contact hole by a known metal filling method. At this time, a tungsten metal film is used as the first plug 16. Subsequently, a first metal wire 17 is formed on the silicon nitride film 15 to be in contact with the first plug 16 by a metal deposition and patterning process. Here, Al or Cu metal having excellent conductivity is used as the first metal wiring 17.

Then, as shown in FIG. 3C, a second interlayer insulating film 18, for example, a plasma applied TIEOS oxide film is deposited to a predetermined thickness and chemically mechanically polished so as to planarize the surface of the semiconductor substrate 11. . Subsequently, the second interlayer insulating layer 18 is etched to expose a predetermined portion of the lower first metal wiring 17 to form a via hole. Thereafter, a second plug 19 is formed in the via hole in the same manner as the first plug 16 formation method. In the drawing, even up to two layers of metal wirings have been described, but the multilayer metal wiring film can be formed by repeating the above-described interlayer insulating film deposition process, via hole forming process, plug forming process, and metal wiring forming process.

The specimen (not shown) in which the multilayer metal wiring is formed is immersed in an oxide etching solution, for example, a buffered oxide etchant (BOE) solution, and as illustrated in FIG. 3D, the second interlayer insulating film 18 is selectively removed. do. At this time, if the metal wiring structure is two or more layers, the interlayer insulating film such as the second, third, fourth, etc. is removed.

In this case, since the first interlayer insulating layer 15 is covered with the silicon nitride layer 15 having a very low etching rate, the first interlayer insulating layer 15 is not removed by the BOE solution, thereby protecting the lower transistor.

Then, as illustrated in FIG. 3E, the specimen in which the second interlayer insulating film is removed may include an insulating film 21 having a low dielectric constant (ε = 2 to 4), for example, polyimid and parylene ( A resin film such as parylene and teflon is formed. Here, the resin film 21 is formed by spin coating a resin material on a specimen, or is formed by immersing in a resin material. Thereafter, a predetermined drying or curing step is performed to solidify.

The resin film 21 formed in this manner fills the gap between the second metal wiring 20 and the first metal wiring 17 sufficiently, thereby lowering the capacitance of the interlayer insulating film. In addition, since the first interlayer insulating film 14 in the portion in direct contact with the transistor 13 is not removed by the silicon nitride film 15, the electrical characteristics of the transistor are not affected.

In addition, after all the metal wiring forming processes, the interlayer insulating film is removed, and the insulating film having the low dielectric constant is filled in the removed portion, thereby not affecting the metal wiring.

In addition, between the step of removing the second interlayer insulating film 18 and the step of filling the insulating film having a low dielectric constant, as shown in FIG. The Al or Cu metal film 22 having a low specific resistance can be coated on the surfaces of the second metal wires 17 and 20 and the second plug 19.

In addition, the insulating film 21 having the low dielectric constant may form a fine foam in the insulating film 21 by injecting a gas during the filling or curing process or in order to further lower its capacitance.

The present invention is not limited to the above embodiment.

In the present embodiment, the two-layer metal wiring has been described as an example, but the same applies to the multilayer metal wiring such as three and four layers.

In addition, in the present embodiment, the contact hole or the via hole is formed by filling a separate plug metal film. However, the contact hole or the via hole may be buried at the same time as the metal wiring.

As described in detail above, according to the present invention, a multilayer metal wiring is formed with an interlayer insulating film of a silicon oxide layer interposed therebetween, the interlayer insulating film is removed by an etching solution, and the removed portion has a low dielectric constant. By filling the film, the capacitance of the interlayer insulating film is lowered.

Therefore, the signal delay time of the semiconductor device is reduced, thereby improving the performance of the semiconductor device.

Claims (13)

(a) forming a semiconductor substrate having gates and junction regions formed thereon; (b) forming a first interlayer insulating film on the semiconductor substrate; (c) forming an etch stop layer on the first interlayer insulating film; (d) forming a contact hole by etching the first interlayer insulating layer and the etch stop layer to expose a predetermined portion of the junction region; (e) forming a first metal wire on the etch stop layer to contact the exposed junction region; (f) forming a second interlayer insulating film on the etch stop layer on which the first metal wiring is formed; (g) forming a via hole by etching the second interlayer insulating layer to expose a predetermined portion of the first metal wire; (h) forming a second metal wiring on the second interlayer insulating film to be in contact with the exposed first metal wiring; (i) selectively removing the second interlayer insulating film; (j) manufacturing a semiconductor device comprising filling the insulating film having a low dielectric constant in a portion where the second interlayer insulating film is removed, wherein the dielectric constant of the insulating film having the low dielectric constant is 2-4. Way. The method of claim 1, wherein the etch stop layer is a silicon nitride film or a boron nitride film. The method of manufacturing a semiconductor device according to claim 1, wherein the second interlayer insulating film is a plasma applied TIOS oxide film. The method of claim 1, wherein in the step (i), the second interlayer insulating layer is selectively removed by a buffered oxide etchant (BOE) solution. The method of manufacturing a semiconductor device according to claim 1, wherein the steps (f), (g) and (h) are repeated at least once between the steps (h) and (i). The method of claim 1, wherein the forming of the first metal wire in the step (e) comprises: forming a contact plug to be filled only in the contact hole; Forming a metal pattern on the etch stop layer so as to be in contact with the contact plug. The method of claim 1, wherein the forming of the second metal wire in the step (h) comprises: forming a via plug to fill only the via hole; And forming a metal pattern on the second interlayer insulating layer so as to be in contact with the via plug. The method of manufacturing a semiconductor device according to claim 1, wherein the insulating film having a low dielectric constant is a resin film such as polyimide, parylene, and teflon. The method of claim 1 or 8, wherein in the step (j), filling the insulating film having a low dielectric constant comprises spin coating the insulating material having the low dielectric constant or applying the insulating material having the low dielectric constant to the insulating material having the low dielectric constant. Method for manufacturing a semiconductor device, characterized in that the filling by dipping. The method of manufacturing a semiconductor device according to claim 1, further comprising coating a metal film on the surfaces of the first metal wiring and the second metal wiring between steps (ii) and (j). . The method of manufacturing a semiconductor device according to claim 10, wherein the metal film is an Al film or a Cu film. The method of claim 1, further comprising, after the step (j), drying or curing the insulating film having the low dielectric constant. The method of manufacturing a semiconductor device according to claim 1 or 12, wherein in the filling or curing step of the insulating film having the low dielectric constant, air or gas is injected to form a foam in the insulating film.

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