KR19990050337A - Method and apparatus for implementing split screen synchronization - Google Patents

Abstract

The present invention relates to a divided screen synchronization realization apparatus capable of realizing synchronization of a divided screen of an LCD monitor using screen division.

The divided screen synchronization implementing apparatus of the present invention divides the input video signal into even and odd pixel data to reduce the frequency to half, and the synchronization signal according to various types of signals input with the reduced frequency. And detecting the first clock signal and generating the first clock signal, dividing the first clock signal according to the control value, and generating the second clock signal according to the divided clock synchronizing signal. It is done.

According to the present invention, in realizing a high resolution by screen division, by matching the synchronization signal of the divided screen, there is an effect that can prevent the screen shake or overlapping phenomenon.

Description

Method and apparatus for implementing split screen synchronization

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display (hereinafter referred to as an LCD device), and more particularly, to a method and an apparatus for implementing a divided screen synchronization capable of realizing synchronization of divided screens of an LCD monitor using screen division. .

In general, in order to implement an LCD monitor and a flat panel display (FDP), an input analog signal is converted into a digital signal to enlarge or interpolate a signal suitable for a panel. As the spread of LCD monitors expands recently, the need for a video processor capable of high resolution is increasing.

In the LCD monitor, if the left and right sides of the screen to be implemented by using the same two video processors are processed by dividing the image using one video processor, a resolution higher than the resolution can be obtained. .

In detail, first, an input video signal is divided into a left half and a right half or an upper half and a lower half by using a memory at an input terminal of a video processor, and recorded in a memory.

Then, the data is read out from the memory using a clock frequency that is 1/2 of the input clock frequency. In other words, the region including the inactive region of the input video signal is divided into a left half and a right half or an upper half and a lower half.

Accordingly, the video signal input to the memory is input to the video processor with the same number of pixels in each of the left and right halves.

In this case, the inactive regions of the two signals divided into the left half and the right half are set to be the same and input to the left half and right half video processors, respectively, and the left and right half video signals are detected by detecting horizontal and vertical synchronization signals of the input signals. Input the horizontal and vertical synchronizing signal transformed accordingly.

The video processor is thus enlarged or interpolated to the desired resolution from the video signal and the horizontal and vertical sync signal clock frequencies. At this time, as shown in Figure 2, the left half and the right half of the output synchronization signal is processed by the left half and the right half, respectively, there is a problem that the synchronization does not match each other.

Accordingly, in synthesizing the output video signal with the left and right half output signals, the left and right half screens oscillate with each other, and thus, video pixels at the midpoint of the screen division overlap with each other.

1 is a block diagram illustrating an LCD device implementing high resolution by screen division.

In the LCD device of Fig. 1, horizontal and vertical synchronization signals having a phase difference with the divided video signals are input to the left and right half video processors 2 and 4, respectively. Each of the left and right half video processors 2 and 4 enlarges or interpolates the input video signal and outputs horizontal and vertical synchronization signals and video signals as shown in FIG. The video signals output from each of the left half and right half video processors 2 and 4 are recorded in the left half memory 8 and the right half memory 10, respectively.

Each of the left half memory 8 and the right half memory 10 includes a left half rain and left half radix memory 8a and 8b and a right half rain even and right half radix memory 10a and 10b. The and odd video signals are recorded separately. Data recorded in each of the left half memory 8 and the right half memory 10 is read and output at a clock frequency twice the input clock frequency. The first multiplexer 12 selects a left half or right half video signal from the left half or right half storm memory 8a, 10a and outputs it to the panel driver 16. The second multiplexer 14 selects a left half or right half radix video signal from the left half or right half radix memories 8b, 10b and outputs the same to the panel driver 16. The panel driver 16 drives the panel 18 according to the video signals input through the first and second multiplexers 12 and 14.

As described above, when the left half and the right half of the input video signal are processed and output, the synchronization of the output video signal does not match.

Accordingly, when synthesizing the left half and right half video signals, the center portion of the combined screen is shaken and the screen overlaps.

Accordingly, an object of the present invention is to provide a method and an apparatus for implementing a divided screen synchronization, which can eliminate not only the shaking of the screen but also the overlapping phenomenon by matching the synchronized screen.

Another object of the present invention is to provide a partitioned screen synchronization implementing method and apparatus capable of implementing multiple synchronizations.

Another object of the present invention is to provide a divided screen synchronization implementing method and apparatus for inputting clocks divided with respect to a clock on an input side into a left half and a right half video processor so that the left and right half of the output screen are synchronized.

1 is a block diagram showing a conventional LCD driving apparatus having a divided screen.

FIG. 2 is a timing diagram of left and right half data in the LCD driving device of FIG. 1; FIG.

3 is a block diagram illustrating a divided screen synchronization implementing device according to the present invention;

4 is an output waveform diagram of each configuration in the synchronization implementing apparatus shown in FIG. 3;

<Description of the symbols for the main parts of the drawings>

2, 4: video processor 8, 10: memory

12, 14: multiplexer 16: panel driver

18: Panel 20, 30: PLL

22: 2-bit counter 24: 2-bit comparator

26: control data storage unit

28: 1 bit counter

In order to achieve the above object, the apparatus for implementing the divided picture synchronization according to the present invention comprises the step 1 of dividing the input video signal into even and odd pixel data to reduce the frequency to 1/2 and being input with the reduced frequency. Two steps of generating a first clock signal by detecting a synchronization signal according to various types of signals, three steps of dividing the first clock signal according to a control value, and generating a second clock signal according to the divided clock synchronization signals Characterized in that it comprises a four step.

In addition, the divided screen synchronization implementing apparatus according to the present invention counts the first clock signal generating means for generating the first clock signal according to various input synchronization signals, the clock signal from the clock signal generating means, and resets it by the feedback signal. A first count means, a comparison means for comparing the count value from the count means with an arbitrary division control value, a comparison means for generating a pulse signal and outputting the pulse signal to the first count means, storage means for storing the division control value; And second clock signal generating means for generating a second pulse signal by the pulse signal from the comparing means and applying the second pulse signal to the video processor.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 3 and 4.

Briefly referring to the operation of the LCD driving apparatus having a divided screen, the LCD driving apparatus has a variety of input signals, and the clock frequency determined by the input signals also varies. Accordingly, in the case of signal processing corresponding to various input signals, necessary clock signals are generated by using the PLL.

In addition, when a high resolution screen is to be implemented, the required clock frequency becomes very high. Thus, in order to implement a higher resolution than the resolution that the video processor can implement, each pixel is separated into even and odd data and input to the video processor.

The clock frequencies required for the video processor processing the left and right half screens are either used as they are or in order to synchronize with the various clocks generated by the input PLL, or divided clock frequencies, e.g., 2, 4, 8 Divided clock frequency is used.

3 is a block diagram illustrating a divided screen synchronization implementing device according to the present invention, wherein the synchronization implementing device of FIG. 3 is connected in series to a first PLL (Phase Locking Loop) circuit 20. A bit counter 22, a 2-bit comparator 24, a 1-bit counter 28, a second PLL circuit 30, and a control data storage 26 connected to the 2-bit comparator 24 are provided. Here, the output of the 2-bit comparator 24 is fed back to the reset signal of the 2-bit counter 22.

In the divided screen synchronization implementing apparatus of FIG. 3, the first PLL 20 generates and outputs a clock frequency as shown in FIG. 3A from an input horizontal synchronization signal. The 2-bit counter 22 counts the clock frequency from the first PLL 20 and outputs a count signal as shown in FIG. The 2-bit comparator 24 compares the count signal from the 2-bit counter 22 with the control data 26 [0: 3] to be divided and generates and outputs a comparison pulse.

For example, when the control data 26 is set to [3], the comparator 24 outputs a pulse signal having a 4 division ratio with respect to the output pulse of the first PLL 20 as shown in FIG. The pulse signal output from the 2-bit comparator 24 is fed back to the 2-bit counter 22 to enable the 2-bit counter 22.

Accordingly, the comparator 24 continuously outputs a pulse having a 0 to 3 division ratio according to the control data 26. The 1-bit counter 28 outputs a pulse signal having 2, 4, and 8 division ratios according to the pulse signal output from the comparator 24.

In other words, since the 1-bit counter 28 outputs the pulse signal toggled at the falling edge of the pulse signal having the 4 division ratio from the comparator 24 as shown in FIG. A pulse signal having an eight-division ratio is output with respect to the output pulse of the 1PLL 20. The pulse signal of the 1-bit counter 28 is input to the second PLL 30 on the video processor output side to be synchronized with the first PLL 20 on the input side.

Here, the 2-bit and 1-bit counters 22 and 28 can be implemented in other forms according to the division ratio, and can cope with various types of input signals such as LCD monitors.

By the above-described method, it is possible to prevent the screen shaking and the overlapping of the screen due to the inconsistency of the left and right screen synchronization signals occurring when the left and right half screens are separated.

As described above, according to the apparatus for implementing the screen split synchronization according to the present invention, in order to achieve high resolution by screen splitting, the screen may be prevented from shaking or overlapping by matching the sync signal of the split screen.

On the other hand, it will be appreciated by those skilled in the art that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (5)

In a method of implementing a synchronization of a video processor for dividing one pixel into a left half and a right half, A first step of dividing the input video signal into even and odd pixel data to reduce the frequency by half; Generating a first clock signal by detecting a synchronization signal according to various types of signals input with the reduced frequency; Dividing the first clock signal according to a control value; And generating a second clock signal according to the divided clock synchronizing signal. The method of claim 1, In the third step And dividing the first clock signal into one of 0 division and 2 division. The method of claim 1, In step 3 above And dividing the first clock signal into one of four divisions and eight divisions. An apparatus for synchronizing a video processor that divides and processes one pixel into a left half and a right half, First clock signal generation means for generating a first clock signal by various input synchronization signals; First count means for counting a clock signal from said clock signal generating means and resetting by a feedback signal; Comparison means for generating a comparison pulse signal by comparing the count value from the counting means with an arbitrary division control value, and outputting the comparison pulse signal to the first counting means; Storage means for storing the dispensing control value; And second clock signal generating means for generating a second pulse signal by the pulse signal from said comparing means and applying it to said video processor. The method of claim 4, wherein And a 1-bit counting means for counting pulses from said comparing means.