JP3221562B2 - Pseudo video signal generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a pseudo video signal generation circuit, and more particularly, to a pseudo video signal generation circuit used for a video signal output device.

[0002]

2. Description of the Related Art In a video signal output device, for example, a video reproducing device, when it is detected that there is no input signal, a CRT is used.
Output the pseudo video signal by switching the display on the screen, etc.
Some include a pseudo video signal generation circuit that displays a single color such as blue on a screen. This prevents the video playback device from displaying an out-of-synchronization noise screen when the video input goes into a no-signal state due to a channel change or stoppage of video playback.

FIG. 13 is a block diagram showing a configuration example of a conventional pseudo video signal generation circuit. An external clock 6 having a frequency sufficiently higher than the frequency of the color subcarrier signal (hereinafter, referred to as fsc signal) is provided outside the pseudo video signal generation circuit.
An external oscillator 61 for generating the signal 9 and supplying it to the pseudo video signal generation circuit is provided. The pseudo video signal generation circuit includes a frequency dividing circuit 63 that generates a counter clock 70 based on an input external clock 69, and an n-ary counter 62 that generates a horizontal synchronization signal 72 based on the counter clock 70. The pseudo video signal generation circuit further includes a horizontal synchronization signal 7.
2, a pseudo video timing generation circuit 65 that generates a pseudo synchronization signal 67 based on an external clock 69, an fsc shifter 64 that generates a color phase signal 71 based on an external clock 69, and a pseudo synchronization signal 67 based on the pseudo phase signal 71 and the color phase signal 71 Pseudo video signal 68
And a pseudo video signal output circuit 66 for generating and outputting the same.

The above-described conventional pseudo video signal generation circuit operates as follows. Here, the National Television Syst
The em Committee (hereinafter simply referred to as NTSC) video system will be described as an example.

In the pseudo video signal generating circuit, a frequency dividing circuit 63
Divides the external clock 69 to output a counter clock 70, and the n-ary counter 62 counts the counter clock 70, thereby generating a horizontal synchronization signal 72 conforming to the NTSC video system. Next, the pseudo video timing generation circuit 65 receives and decodes the horizontal synchronizing signal 72 which is the count value of the n-ary counter 62, and generates a pseudo synchronizing signal 67 conforming to the standard of the video signal. At this time, the fsc shifter 64 shifts the fsc signal input from outside the circuit using the external clock 69, and
Generate The pseudo video signal output circuit 66 combines the pseudo synchronizing signal 67 generated based on the horizontal synchronizing signal 72 defined in the NTSC video system with the color phase signal 71 obtained by applying phase modulation to the fsc signal, and outputs a signal such as blue. To generate a pseudo video signal 68 for displaying a single color.

[0006] In the NTSC video system, fsc signal is 3.579545MH _Z, a horizontal synchronization period 1 / f _H 63.556μs
= Because it is 2 fsc / 455, the _{1 / f H ≒ 227.5 / fsc} .
Therefore, simply inputting the fsc signal cannot satisfy the standard of the horizontal synchronization cycle of the pseudo video signal to be generated. Therefore, a signal having a cycle of 2n times (n is a natural number) of the fsc signal is input to the horizontal synchronization counter. It is necessary to satisfy the horizontal synchronization cycle.

FIG. 14 is a timing chart for explaining the timing of each signal when a horizontal synchronizing signal is generated. The figure shows the timing when an external clock (4 · fsc signal) 69 having a frequency four times the frequency of the fsc signal is input from the external oscillator 61.

As described above, the horizontal synchronization cycle 1 / f _H of the horizontal synchronization signal 72 is defined as 1 / f _H = 63.556 μs = 455 / 2fsc. The external clock 69 from the frequency divider 61 is frequency-divided, and a 2 · fsc signal whose frequency is twice the frequency of the fsc signal is generated as the counter clock 70. Next, the counter clock 70 is set to the n-ary counter 62.
And a horizontal synchronization signal (horizontal synchronization counter) is generated. Horizontal scanning is performed according to the horizontal synchronization signal, and vertical scanning is performed according to the vertical synchronization signal (vertical synchronization counter).
Is displayed on the screen. Here, the case where a 4 · fsc signal is input as the external clock 69 has been described, but when an external clock of another frequency is input,
A similar function can be realized by changing the frequency division ratio of the frequency dividing circuit 63.

FIG. 15 is a timing chart for explaining the operation when the color phase signal 71 is generated. Since the color phase signal 71 is a signal obtained by applying phase modulation to the fsc signal, it is generated by shifting the fsc signal to the external clock 69 at a higher frequency of 4 · fsc. In this example, since the 4 · fsc signal is used for the external clock 69, the fsc signal is shifted by 45 ° to 0
Eight types of color phase signals ranging from ° to 315 ° are generated.

[0010]

In the above-mentioned conventional pseudo video signal generating circuit, an external clock 69 obtained by multiplying the fsc signal by 2n in advance is input for the above-mentioned reason caused by the NTSC video system, and the pseudo video signal 68 Depends on the accuracy of the external clock 69. Therefore, in a video reproducing apparatus including such a pseudo video signal generation circuit, an expensive crystal oscillator or the like is mounted as the external oscillator 61 for the purpose of guaranteeing the accuracy of the pseudo video signal 68. That is, since the expensive external oscillator 61 is used only when there is no input signal, there are problems such as an increase in the number of components and an increase in manufacturing cost.

To solve this problem, the fsc signal is set to 2n
There is also an attempt to reduce the number of components by incorporating a multiplying circuit for multiplying in the pseudo video signal generating circuit. However, in order to realize a high-precision multiplication circuit that can guarantee the accuracy of the pseudo video signal 68, the circuit scale becomes large, and it becomes difficult to solve the cost problem.

Further, in the above-mentioned conventional pseudo video signal generation circuit, a signal of 2n times is used as the external clock 69, and fs
For example, the color phase signal 71 is generated by shifting the c signal by a predetermined angle. For this reason, for example,
When the sc signal is used, the color phase signal 71 is limited to eight colors, and when the 2 · fsc signal is used, the color phase signal 71 is limited to four colors.
This is limited by the frequency of the external clock 69 supplied from 1 and the frequency of the multiplied signal.

In view of the above, the present invention can generate a pseudo video signal having a period conforming to a video signal standard from a color subcarrier signal without depending on an expensive external oscillator or the like.
An object of the present invention is to provide a pseudo video signal generation circuit capable of reducing the number of components and reducing manufacturing costs. It is still another object of the present invention to provide a pseudo video signal generation circuit capable of setting the phase difference with respect to the color subcarrier signal more finely and increasing the number of colors corresponding to the pseudo video signal.

[0014]

To achieve the above object, a pseudo video signal generating circuit according to the present invention comprises: an oscillating circuit for outputting an internal clock having a frequency higher than the frequency of an input color subcarrier signal; A color sub-carrier signal and the internal clock are input, and a signal corresponding to a rising and falling change of the color sub-carrier signal, and having a frequency twice as high as the color sub-carrier signal, A counter clock generation circuit that generates a counter clock in synchronization with the internal clock; an internal high-speed counter that counts the internal clock and is reset by the counter clock; and a counter clock immediately before the internal high-speed counter is reset by the counter clock. A predetermined value determined based on the count value of the high-speed counter and the count value of the internal high-speed counter A coincidence detection circuit that outputs a coincidence signal when coincidence occurs, and a phase that generates a logical sum of the counter clock and the coincidence signal to generate a phase generation clock having a frequency that is a predetermined multiple of the frequency of the color subcarrier signal. A generation clock generation circuit, a color phase generation circuit that generates a phase signal having a phase difference with respect to the color subcarrier signal by shifting the color subcarrier signal according to the phase generation clock, And a pseudo video signal output circuit for generating and outputting a pseudo video signal based on the phase signal and the pseudo sync signal.

In the pseudo video signal generation circuit according to the present invention, a counter clock having a frequency n times the color subcarrier signal synchronized with the rising or falling of the internal clock from the oscillation circuit can be generated. For this reason, it is possible to generate a pseudo video signal having a cycle conforming to the video signal standard from the color subcarrier signal without depending on an expensive external oscillator or a high-precision multiplication circuit. In addition, since a phase generation clock having a frequency that is a predetermined multiple of the frequency of the color subcarrier signal can be generated, a pseudo video signal can be generated without being limited by the frequency of an external clock from an external oscillator.

Here, it is preferable that the color phase generation circuit comprises a shifter for shifting the color subcarrier signal in accordance with the phase generation clock, and a selection circuit for selecting a shift amount by the shifter. In this case, the phase difference with respect to the color subcarrier signal can be finely set using a phase generation clock having a frequency that is a predetermined multiple of the frequency of the color subcarrier signal, so that the number of colors corresponding to the pseudo video signal increases.

Further, the pseudo video signal generation circuit according to the present invention comprises:
According to another aspect, an oscillation circuit that outputs an internal clock having a higher frequency than the frequency of the input color subcarrier signal,
The chrominance sub-carrier signal and the internal clock are input, and a signal corresponding to a rise and fall change of the chrominance sub-carrier signal, respectively, having a frequency twice as high as the chrominance sub-carrier signal, A counter clock generation circuit that generates a counter clock in synchronization with the internal clock, and by delaying the color subcarrier signal by a predetermined time,
A color phase generation circuit that generates a color phase signal having a phase difference with respect to the color subcarrier signal; a pseudo synchronization signal generation circuit that generates a pseudo synchronization signal based on the counter clock; A pseudo video signal output circuit that generates and outputs a pseudo video signal based on the synchronization signal.

According to the above configuration, it is possible to generate a signal having a frequency twice as high as that of the color subcarrier signal, which corresponds to the rise and fall of the color subcarrier signal, as the counter clock. In addition, a phase signal having a phase difference from the color subcarrier signal can be generated by delaying the color subcarrier signal by a predetermined time. Therefore, a pseudo-synchronous signal based on a counter clock is generated by a pseudo-synchronous signal generation circuit without depending on an expensive external oscillator or a high-precision multiplication circuit, and a pseudo video signal is generated based on the pseudo-synchronous signal and the color phase signal. Can be generated.

Preferably, the color phase generation circuit includes a delay circuit for delaying the color subcarrier signal for a predetermined time, and a selection circuit for selecting a delay time of the delay circuit. In this case, by delaying the color subcarrier signal for a predetermined time, the phase difference with respect to the color subcarrier signal can be set finely, and the number of colors corresponding to the pseudo video signal can be increased.

According to another aspect of the present invention, there is provided a pseudo video signal generating circuit which outputs an internal clock having a frequency higher than the frequency of an input color subcarrier signal, the color subcarrier signal and the internal clock. And a signal corresponding to a change in the rise and fall of the color subcarrier signal, the signal having twice the frequency of the color subcarrier signal being synchronized with a counter clock in synchronization with the internal clock. And a counter clock generation circuit that generates the color subcarrier signal as an input, and generates a color phase signal having a desired phase difference with respect to the color subcarrier in response to predetermined rising detection potential and falling detection potential. A potential detection circuit for outputting, a pseudo-synchronization signal generation circuit for generating a pseudo-synchronization signal based on the counter clock, and a potential detection circuit based on the color phase signal and the pseudo-synchronization signal. There characterized in that it comprises a pseudo video signal output circuit for generating and outputting a pseudo video signal.

According to the above configuration, it is possible to generate, as the counter clock, a signal having a frequency twice as high as that of the color subcarrier signal, which corresponds to the rise and fall of the color subcarrier signal. Further, the color sub-carrier signal is input, and a color phase signal having a desired phase difference with respect to the color sub-carrier can be output corresponding to a predetermined rising detection potential and falling detection potential. Therefore, a pseudo-synchronous signal based on the counter clock is generated by the pseudo-synchronous signal generation circuit without depending on an expensive external oscillator or a high-precision multiplication circuit, and a pseudo video signal is generated based on the pseudo-synchronous signal and the phase signal. Can be generated.

Preferably, the apparatus further comprises a selection circuit for setting the predetermined rising detection potential and falling detection potential. In this case, the phase difference with respect to the color subcarrier signal can be set finely, and the number of colors corresponding to the pseudo video signal can be increased.

According to still another aspect, the pseudo video signal generating circuit of the present invention receives a chrominance subcarrier signal, generates a signal obtained by inverting the level of the chrominance subcarrier signal, and generates the chrominance subcarrier signal or A counter clock output circuit that selects and outputs the inverted signal in accordance with the level of an operating point selection signal, an n-number (n is a natural number) counter that counts the counter clock, and each time the n-number counter counts n A circuit for generating the operating point selection signal whose level is inverted, and a pseudo video timing generator for receiving an output of the n-ary counter, generating a timing of a synchronization signal conforming to a video signal standard, and outputting the same as a pseudo synchronization signal Circuit and
The color subcarrier signal is input, a color phase generation circuit that generates a color phase signal having a phase difference with respect to the color subcarrier signal, and a pseudo video signal based on the pseudo synchronization signal and the color phase signal. And a pseudo video signal output circuit for generating and outputting.

According to the above configuration, a pseudo video signal having a cycle conforming to the video signal standard can be obtained only by inputting the chrominance subcarrier signal without providing an oscillator inside or outside the circuit. In addition, a pseudo video signal can be generated from a color subcarrier signal without depending on an expensive external oscillator or a high-precision multiplication circuit, so that the number of components can be reduced and cost can be reduced.

[0025]

The present invention will be described in more detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a pseudo video signal generation circuit according to a first embodiment of the present invention. This pseudo video signal generation circuit is used for a video signal output device such as a video playback device, and includes a high-speed oscillation circuit 13,
A retiming circuit 11, an n-ary counter 12, a pseudo video timing generating circuit 15, a color phase generating circuit 14,
A pseudo video signal output circuit 16.

The high-speed oscillation circuit 13 outputs an internal clock 19 having a frequency higher than the frequency of the input fsc signal. The self-propelled oscillation circuit 13 oscillates at its own frequency without receiving a synchronization pulse from the outside. A free-running oscillation circuit, for example, a ring oscillation circuit using an inverter or the like. The retiming circuit 11 is a circuit having a retiming function for synchronizing an asynchronous signal, and includes an internal clock 19 from the high-speed oscillation circuit 13 and an external clock from the circuit.
An fsc signal is input, and a counter clock 20 and a phase generation clock 22 are output.

The n-ary counter 12 has a horizontal synchronization counter and a vertical synchronization counter. The counter clock 20 is input to the horizontal synchronization counter and counted, whereby
A cycle of horizontal synchronization is generated and output as a count value 32. The pseudo video timing generation circuit 15 receives the count value 32 from the n-ary counter 12 and, for example,
The timing of the synchronization signal conforming to the standard of the video signal of the video system is generated and output as the pseudo synchronization signal 17.

The color phase generation circuit 14 is provided with fs from the outside of the circuit.
The c signal, the internal clock 19 from the high-speed oscillator 13 and the phase generation clock 22 from the retiming circuit 11 are input, and a phase signal 21 is generated and output. The pseudo video signal output circuit 16 receives the pseudo synchronizing signal 17 from the pseudo video timing generation circuit 15 and the color phase signal 21 from the color phase generation circuit 14, and generates and outputs a pseudo video signal 18. The n-ary counter 12 and the pseudo video timing generation circuit 15 constitute a pseudo synchronization signal generation circuit that generates the pseudo synchronization signal 17 based on the counter clock 20.

FIG. 2 is a block diagram showing the retiming circuit 11 of FIG. 1 in detail. Retiming circuit 11
Is a differential circuit 25, an internal high-speed counter 26, Max / 2f
It includes an etch circuit 27, a coincidence detection circuit 29, and a 4 · fsc generation circuit 30. A counter clock generating circuit is constituted by the differentiating circuit 25, and the internal high-speed counter 26 and Max / 2fetch
The circuit 27, the coincidence detection circuit 29, and the 4 · fsc generation circuit 30 constitute a phase generation clock generation circuit.

The differentiating circuit 25 inputs the fsc signal and the internal clock 19, and multiplies the fsc signal by n (natural number) times, for example, 2
A counter clock generation circuit that generates a counter clock 20 having a double frequency in synchronization with the rise or fall of the internal clock 19 is configured. That is, the differentiation circuit 2
5 detects a rising point and a falling point of the fsc signal, respectively, and counts a half cycle of the fsc signal, thereby outputting a 2 · fsc signal having a frequency twice as high as the fsc signal as the counter clock 20. .

The internal high-speed counter 26 includes a high-speed oscillation circuit 1
3 to generate an internal count value 23 which is reset by the counter clock 20. The Max / 2fetch circuit 27 has an internal high-speed counter 26
Is held as a Max / 2 value (specific value) 33, which is 1/2 of the count value immediately before resetting. Also, the match detection circuit 2
9 is the internal count value 23 from the internal high-speed counter 26
Is compared with the Max / 2 value 33 held in the Max / 2fetch circuit 27, and when both values match, a match signal 34 is output.

4. The fsc generation circuit 30 generates the internal clock 19
And the counter clock 20 and the coincidence signal 34,
A phase generation clock generation circuit that generates a phase generation clock 22 having a frequency 2 ⁿ times the frequency of the fsc signal is configured. In this embodiment, the 4 · fsc generation circuit 30 outputs the 4 · fsc signal having a frequency four times the frequency of the fsc signal to the phase generation clock 22.
Output as Also, an internal high-speed counter 26, Max / 2f
The etch circuit 27 and the coincidence detection circuit 29 constitute a second counter clock generation circuit.

Next, the operation of the pseudo video signal generation circuit of the embodiment will be described. FIG. 3 is a timing chart showing the operation of the pseudo video signal generation circuit.

First, when the internal clock 19 from the high-speed oscillation circuit 13 and the fsc signal asynchronously input from the outside of the circuit are input to the retiming circuit 11, the differentiating circuit 25
Detect both the rising and falling change points of the fsc signal. The differentiating circuit 25 further generates a 2 · fsc signal having a frequency twice as high as the fsc signal according to the standard of the video signal to be displayed in synchronization with the rising edge of the internal clock 19.
Output as the counter clock 20. Next, the n-ary counter 12 inputs and counts the counter clock 20, and outputs the value as a count value 32. Further, the similar video timing generation circuit 15 decodes the count value 32 and generates the pseudo synchronizing signal 17 conforming to the standard of the video signal.

On the other hand, the internal high-speed counter 26 receives the internal clock 19 and the counter clock 20 and counts the internal clock 19 to generate and output an internal count value 23. The internal count value 23 is a value counted up in synchronization with the rising of the internal clock 19, and is reset every time a pulse of the counter clock 20 is output. Immediately before the internal count value 23 is reset by the counter clock 20, the Max / 2fetch circuit 27 outputs the Max / 2 fetch circuit at the same timing as the reset.
The value 33 is retained.

Next, the coincidence detecting circuit 29 compares the internal count value 23 from the internal high-speed counter 26 with the Max / 2 value 33, which is the value n / 2 held by the Max / 2fetch circuit 27. Then, “1” is output as the coincidence signal 34. Here, the 4 · fsc generation circuit 30 receives the internal clock 19, the counter clock 20, and the coincidence signal 34, and performs a logical sum operation of the counter clock 20 and the coincidence signal 34 on a phase having a frequency four times the frequency of the fsc signal. It is output as a generated clock 22.

FIG. 4 shows the color phase generation circuit 1 of FIGS.
FIG. 4 is a block diagram showing the details of FIG. Color phase generation circuit 1
4 is composed of a shifter 24 and a selection circuit 28,
The color phase signal 21 is generated and output according to the selection signal 39 based on the fsc signal. That is, in the color phase generation circuit 14, the shifter 24 operates every period of the phase generation clock 22.
The fsc signal is shifted using the internal clock 19, and a color phase signal 21 having a desired phase difference with respect to the fsc signal is output. The selection circuit 28 selects a shift amount by the shifter 24 according to a selection signal 39. The selection signal 39 is generated by a selection signal generation circuit 54 provided inside the circuit.

FIG. 5 is a timing chart showing the operation of the color phase generation circuit 14, and shows the operation when a single red color is displayed on the screen.

Since the phase generation clock 22 has four times the frequency of the fsc signal, the cycle of one clock of the phase generation clock 22 is 360 ° ÷ 4 = 90 when the phase is replaced with a phase.
°. Since the shifter 24 adjusts the shifter amount by the selection circuit 28 according to the selection signal 39, a plurality of signals having different phase differences can be generated as shown in FIG. Here, since the phase difference between the signal necessary for displaying red and the fsc signal is about 90 °, the selection circuit 28 shifts the fsc signal by one clock of the phase generation clock 22 corresponding to about 90 °. Select the amount to shift,
The shifter 24 is set. As a result, the red display phase signal 21 is output to the pseudo video signal output circuit 16.

Next, the pseudo video signal output circuit 16 outputs the pseudo synchronizing signal 17 from the pseudo video timing generation circuit 15.
And the color phase signal 21 from the color phase generation circuit 14 are input and synthesized, and a pseudo video signal 18 having a phase for displaying red is displayed.
Is output. As a result, a single red color is displayed on a screen such as a CRT.

As described above, the 4 · fsc generation circuit 30
Since a 4 · fsc signal equivalent to four times the signal is generated and the color phase generation circuit 14 shifts the fsc signal using the 4 · fsc signal, the phase difference from the fsc signal can be set finely. Therefore, without being limited by the frequency of the external clock from the external oscillator or the frequency of the multiplied signal,
By generating a phase difference inside the circuit, a phase signal 21 corresponding to many colors can be generated, and a variety of display colors can be increased.

In the color phase generation circuit 14, the color of the video signal is
Since it is determined by the phase difference from the fsc signal, the higher the frequency of the input phase generation clock 22 is higher than the frequency of the fsc signal,
The phase signal 21 obtained by finely dividing the phase can be generated. Therefore, in order to generate the pseudo video signal 18 corresponding to many colors, the high-frequency phase generation clock 22
is necessary. In the present embodiment, the Max / 2fetch circuit 27
From the counter clock 20, which is the 2 · fsc signal.
4. The fsc signal was generated. For example, the Max / 2fetch circuit 27
Another fetch circuit having the same configuration as that described above can be provided. In this case, the coincidence detection circuit 29 compares the internal count value 23 from the internal high-speed counter 26 with the plurality of specific values held in the plurality of fetch circuits, respectively. The coincidence signal 34 is output. Further, by taking the logical sum of the counter clock 20 and the coincidence signal 34, it is possible to output the phase generation clock 22 having a frequency which is n ² times the frequency of the fsc signal.

In this embodiment, the differentiating circuit 25 detects both the rising and falling transition points of the chrominance subcarrier signal, thereby detecting the n of the fsc signal synchronized with the rising or falling of the internal clock 19. The counter clock 20 having a double cycle can be generated. Therefore, since the fsc signal is directly input from the outside of the circuit and retiming is performed, and furthermore, a cycle synchronized horizontally by the n-ary counter 12 can be generated, conventionally, without using a signal input from an external oscillator or the like,
Operation equivalent to the conventional operation can be realized.

As described above, in the present embodiment, the pseudo video signal 18 having a cycle conforming to the video signal standard can be generated from the fsc signal without depending on an expensive external oscillator or a high-precision multiplication circuit. For this reason, an expensive external oscillator such as a crystal oscillator or a high-precision multiplying circuit, which is conventionally required only for generating a pseudo video signal, becomes unnecessary. The oscillation frequency of the high-speed oscillation circuit 13 only needs to be higher than the fsc signal, and accuracy is not required.
It can be manufactured at low cost and can contribute to cost reduction of the pseudo video signal generation circuit.

In general, the oscillator has a large transistor size in order to obtain a large gain. In a conventional video reproducing apparatus having an external oscillator, since the external oscillator and the pseudo video signal generation circuit are connected to terminals, it is likely to affect other components and wiring on the substrate. That is,
In a system where digital and analog parts are mixed or located close to each other, not only the pseudo video signal generation circuit but also other parts on the same board are liable to be affected by second harmonics and the like. Problems may occur. In contrast,
In the pseudo video signal generation circuit, since no external oscillator is required, such a problem can be solved.

FIG. 6 is a block diagram showing a pseudo video signal generation circuit according to the second embodiment in which the configuration of the color phase generation circuit according to the first embodiment is changed. In the present embodiment,
The configuration other than the color phase generation circuit 14 'is the same as that of the first embodiment, except that the internal clock 19 which is the output of the high-speed oscillation circuit 13 and the phase generation clock 22 which is the output of the retiming circuit 11 are different from the color phase generation circuit. 14 'is not supplied. That is, the retiming circuit 11 in the present embodiment example
Comprises only the differentiating circuit 25 in FIG.

The color phase generation circuit 14 ′ includes a delay circuit 38 and a selection circuit 28, receives a selection signal 39 and an fsc signal from outside the circuit, generates a color phase signal 21 according to the selection signal 39, and outputs the color phase signal 21. I do. That is, the color phase generation circuit 1
In 4 ', the selection circuit 28 appropriately selects and sets the delay time of the delay circuit 38, so that the delay circuit 38
The fsc signal is delayed by a set predetermined time. As a result, a signal having a phase difference corresponding to a desired display color is generated, and is output as a color phase signal 21 having a phase difference with the fsc signal.

FIG. 7 is a timing chart showing the operation of the color phase generation circuit 14 '. In the figure, the selection circuit 28 sets the delay amount d in the delay circuit 38 to generate the color phase signal 21 having a desired phase difference with respect to the fsc signal.

As described above, the same effects as those of the pseudo video signal generation circuit of the first embodiment can also be obtained by the pseudo video signal generation circuit of the second embodiment.

FIG. 8 is a block diagram showing a pseudo video signal generation circuit according to the third embodiment in which the configuration of the color phase generation circuit according to the first embodiment is changed. In the present embodiment,
The configuration other than the color phase generation circuit 14 ″ is the same as that of the first embodiment, except that the internal clock 19, which is the output of the high-speed oscillation circuit 13, and the phase generation clock 22, which is the output of the retiming circuit 11, are a color phase generation circuit. 14 "is not supplied. That is, the retiming circuit 11 in the present embodiment example
Comprises only the differentiating circuit 25 in FIG.

The color phase generation circuit 14 ″ of the present embodiment is
It comprises a potential detection circuit 51 and a selection circuit 28, receives a selection signal 39 and an fsc signal, and generates and outputs a color phase signal 21 according to the selection signal 39. The potential detection circuit 51 detects the potential of the fsc signal such as a sine wave input from outside the circuit, and the selection circuit 28 sets the rising detection potential and the falling detection potential according to the instruction of the selection signal 39.

9 is a timing chart showing the operation of the color phase generation circuit 14 ". The potential detection circuit 51 has a rising detection potential A and a falling detection potential B as two thresholds. The potential of the input fsc signal is
Detection is performed according to selection of the detection potential by the selection circuit 28.

For example, when the potential of the fsc signal becomes higher than the rising detection potential A, the color phase signal 21 becomes "1" level, and the potential of the fsc signal becomes the falling detection potential B
At the point where the color phase signal 21 becomes lower, the color phase signal 21 becomes “0” level. When the rising detection potential is set to A 'and the falling detection potential is set to B' by the selection circuit 28, the phases are shifted as in the color phase signal 21 shown on the lower side of FIG. As described above, the rise detection potential and the fall detection potential are appropriately set by the selection circuit 28, so that the color phase signal 21 having a desired phase difference with respect to the fsc signal can be generated.

As described above, the same effect as the pseudo video signal generation circuit of the first embodiment can be obtained by the pseudo video signal generation circuit of the third embodiment.

FIG. 10 is a block diagram showing a configuration of a pseudo video signal generation circuit according to a fourth embodiment of the present invention.
This pseudo video signal generation circuit does not include the high-speed oscillation circuit 13 included in the pseudo video signal generation circuit of the first embodiment.

The pseudo video signal generation circuit of this embodiment is
A retiming circuit 41, an n-ary counter 42, a pseudo video timing generating circuit 45, a color phase generating circuit 44,
A pseudo video signal output circuit 46.

The retiming circuit 41 inputs the operating point selection signal 49 and the fsc signal from outside the circuit, and generates a counter clock 4 generated by inverting or inverting the level of the fsc signal.
3 is formed. n
The decimal counter 42 outputs the count value 32 obtained by counting the counter clock 43 via the decoder 53, and outputs an operation point selection signal 49 for inverting the level and inverting the counter clock 43 every time the counter clock 43 is counted to a predetermined value. A signal output circuit that outputs the signal via the decoder 53 is configured.

The pseudo video timing generation circuit 45 receives the count value 32 from the n-ary counter 42, generates the timing of a synchronization signal conforming to the video signal standard, and outputs it as a pseudo synchronization signal 47. Color phase generation circuit 44
Receives a fsc signal from the outside of the circuit, generates and outputs a color phase signal 50 having a phase difference with respect to the fsc signal. The pseudo video signal output circuit 46 receives the pseudo synchronizing signal 47 from the pseudo video timing generation circuit 45 and the color phase signal 50 from the color phase generation circuit 44, and generates and outputs a pseudo video signal 48.

Next, the operation of the pseudo video signal generation circuit in this embodiment will be described. FIG. 11 is a timing chart showing an operation in the pseudo video signal generation circuit.

The retiming circuit 41 is connected to the outside of the circuit.
fsc signal and operating point selection signal 49 from n-ary counter 42
, The counter clock 43 is output according to the level of the operating point selection signal 49. For example, when the operating point selection signal 49 is “1”, the fsc signal is output as the counter clock 43, and when the operating point selection signal 49 is “0”, a signal obtained by inverting the fsc signal is output as the counter clock 43. .

The n-ary counter 42 is composed of an i + 1-level horizontal counter 42a and a j + 1-level vertical counter, and each time the horizontal counter 42a counts from "0" to "i", the operating point The level of the selection signal 49 is inverted from “0” to “1” or from “1” to “0”. Since the level of the horizontal counter section 42a changes at the rising edge of the counter clock 43, the operation is i +
Functions as a 0.5-digit counter.

Next, the pseudo video timing generation circuit 45
Inputs the count value 32 from the n-ary counter 42,
The timing of the synchronization signal conforming to the video signal standard is generated and output as the pseudo synchronization signal 47. On the other hand, the color phase generation circuit 44 receives an fsc signal from outside the circuit, generates a phase difference with respect to the fsc signal, and outputs a color phase signal 50. Accordingly, the pseudo video signal output circuit 46 receives the color phase signal 50 and the pseudo synchronizing signal 47 from the pseudo video timing generation circuit 45, and generates and outputs a pseudo video signal 48.

FIG. 12 is a timing chart showing the operation of the pseudo video signal generation circuit of this embodiment when the video signal standard is the NTSC video system.

In the case of the NTSC video system, the relationship between the fsc signal and the horizontal synchronization period 1 / f _H is expressed as 1 / f _H = 455/2 · fsc = 63.556 μs. According to this relational expression, it can be seen that a signal having a frequency twice as high as the fsc signal should be counted in 455 base in order to satisfy the period of the horizontal synchronization. That is,
A similar effect can be obtained by counting the fsc signal in 227.5 base.

When the operating point selection signal 49 is at the "0" level, the counter clock 43 is an inverted signal of the fsc signal, so that the horizontal counter 42a of the n-ary counter 42
It counts up in synchronization with the falling transition point of the fsc signal. When the horizontal counter 42a counts up to 227, the operating point selection signal 49 is inverted and changes to "1" level. On the other hand, when the operating point selection signal 49 is at the “1” level, the counter clock 43 is in phase (normal rotation) with the fsc signal.
Therefore, the horizontal counter section 42a of the n-ary counter 42
Counts up again in synchronization with the rising transition point of the fsc signal.

As described above, in the fourth embodiment, the period of the synchronizing signal conforming to the standard of the video signal can be obtained only by inputting the fsc signal from the outside of the circuit without providing any oscillator inside or outside the circuit. Can be obtained. In addition, similarly to the first embodiment, a pseudo video signal having a cycle conforming to the video signal standard can be generated from the fsc signal without depending on an expensive external oscillator or a high-precision frequency multiplier. . As a result, the number of parts can be reduced and cost can be reduced.

Although the present invention has been described based on the preferred embodiment, the pseudo video signal generating circuit of the present invention
It is not limited only to the configuration of the above embodiment,
A pseudo video signal generation circuit obtained by making various modifications and changes from the configuration of the above-described embodiment is also included in the scope of the present invention.

[0068]

As described above, according to the pseudo video signal generating circuit of the present invention, a pseudo video signal having a cycle conforming to the video signal standard can be converted into a color subcarrier without depending on an expensive external oscillator or the like. Can be generated from signals. Furthermore, cost can be reduced by reducing the number of parts.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a pseudo video signal generation circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a retiming circuit according to the first embodiment in detail;

FIG. 3 is a timing chart illustrating an operation of the pseudo video signal generation circuit according to the first embodiment.

FIG. 4 is a block diagram showing in detail a color phase generation circuit according to the first embodiment.

FIG. 5 is a timing chart illustrating an operation of the color phase generation circuit according to the first embodiment.

FIG. 6 is a block diagram showing a pseudo video signal generation circuit according to a second embodiment of the present invention.

FIG. 7 is a timing chart illustrating an operation of the color phase generation circuit according to the second embodiment.

FIG. 8 is a block diagram showing a configuration of a pseudo video signal generation circuit according to a third embodiment of the present invention.

FIG. 9 is a timing chart illustrating the operation of the color phase generation circuit according to the third embodiment.

FIG. 10 is a block diagram showing a configuration of a pseudo video signal generation circuit according to a fourth embodiment of the present invention.

FIG. 11 is a timing chart showing an operation of the pseudo video signal generation circuit according to the fourth embodiment.

FIG. 12 is a timing chart showing the operation of the pseudo video signal generation circuit of the fourth embodiment in the case of the NTSC video system.

FIG. 13 is a block diagram illustrating a configuration example of a conventional pseudo video signal generation circuit.

FIG. 14 is a timing chart for explaining the timing of each signal when a conventional pseudo video signal generation circuit generates a horizontal synchronization signal.

FIG. 15 is a timing chart for explaining an operation when a color phase signal is generated by a conventional pseudo video signal generation circuit.

[Explanation of symbols]

 11, 41 Retiming circuit 12, 42 N-ary counter 13 High-speed oscillation circuit 14, 14 ', 14 ", 44, color phase generation circuit 15, 45 Pseudo video timing generation circuit 16, 46 Pseudo video signal output circuit 25 Differentiation circuit 26 Internal high-speed counter 27 Max / 2fetch circuit 30 4 · fsc generation circuit

────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-3-175793 (JP, A) JP-A-3-166865 (JP, A) JP-A 1-248872 (JP, A) JP-A-6- 351033 (JP, A) Hikaru 2-685834 (JP, U) (58) Fields studied (Int. Cl. ⁷ , DB name) H04N 9/44

Claims (7)

(57) [Claims] 1. An oscillation circuit for outputting an internal clock having a frequency higher than the frequency of an input chrominance sub-carrier signal, and an input of the chrominance sub-carrier signal and the internal clock, and a rise and a rise of the chrominance sub-carrier signal A counter clock generation circuit that generates a signal corresponding to the change of the falling edge and having a frequency twice as high as that of the color subcarrier signal as a counter clock in synchronization with the internal clock; and counting the internal clock. An internal high-speed counter reset by the counter clock; a predetermined value determined based on a count value of the high-speed counter immediately before the internal high-speed counter is reset by the counter clock; and a count value of the internal high-speed counter. A match detection circuit that outputs a match signal when A phase generation clock generation circuit that generates a phase generation clock having a frequency that is a predetermined multiple of the frequency of the color subcarrier signal by taking a logical sum with the coincidence signal; and shifting the color subcarrier signal according to the phase generation clock. A color phase generation circuit that generates a phase signal having a phase difference with respect to the color subcarrier signal; a pseudo synchronization signal generation circuit that generates a pseudo synchronization signal based on the counter clock; A pseudo video signal output circuit that generates and outputs a pseudo video signal based on the pseudo sync signal. 2. The color phase generating circuit according to claim 1, further comprising: a shifter that shifts the color subcarrier signal in accordance with the phase generation clock; and a selection circuit that selects a shift amount by the shifter. A pseudo video signal generation circuit according to any one of the preceding claims. 3. An oscillating circuit for outputting an internal clock having a frequency higher than the frequency of an input chrominance subcarrier signal, an input of the chrominance subcarrier signal and the internal clock, and the rise and rise of the chrominance subcarrier signal A counter clock generation circuit that generates a signal corresponding to the change of the falling, which has a frequency twice as high as that of the color subcarrier signal, as a counter clock in synchronization with the internal clock; A color phase generation circuit that generates a color phase signal having a phase difference with respect to the color sub-carrier signal by delaying the color sub-carrier signal, and a pseudo synchronization signal generation circuit that generates a pseudo synchronization signal based on the counter clock. A pseudo video signal output circuit that generates and outputs a pseudo video signal based on the color phase signal and the pseudo synchronization signal. Pseudo video signal generating circuit. 4. The color phase generating circuit according to claim 3, wherein said color phase generating circuit comprises a delay circuit for delaying said color subcarrier signal for a predetermined time, and a selecting circuit for selecting a delay time of said delay circuit. Pseudo-signal generation circuit. 5. An oscillation circuit for outputting an internal clock having a frequency higher than the frequency of an input chrominance sub-carrier signal, inputting the chrominance sub-carrier signal and the internal clock, and rising and rising the chrominance sub-carrier signal A counter clock generation circuit that generates a signal corresponding to the change of the falling, which has a frequency twice as high as that of the color subcarrier signal, as a counter clock in synchronization with the internal clock; And a potential detection circuit that outputs a color phase signal having a desired phase difference with respect to the color subcarrier in response to predetermined rising detection potential and falling detection potential, A pseudo synchronizing signal generation circuit for generating a synchronizing signal; a pseudo video signal for generating and outputting a pseudo video signal based on the color phase signal and the pseudo synchronizing signal Pseudo video signal generating circuit, characterized by an output circuit. 6. The pseudo video signal generation circuit according to claim 5, further comprising a selection circuit for setting the predetermined rising detection potential and falling detection potential. 7. A color subcarrier signal is input, a signal is generated by inverting the level of the color subcarrier signal, and the color subcarrier signal or the inverted signal is selected according to the level of an operating point selection signal. And a counter clock output circuit for counting and outputting the counter clock (n is a natural number)
Binary counter, a circuit for generating the operating point selection signal whose level is inverted each time the n-ary counter counts n, and a timing of a synchronization signal which receives an output of the n-ary counter and conforms to a video signal standard A pseudo-image timing generation circuit that generates a pseudo-synchronous signal, and a color phase generation circuit that receives the color subcarrier signal and generates a color phase signal having a phase difference with respect to the color subcarrier signal, A pseudo video signal generation circuit, comprising: a pseudo video signal output circuit that generates and outputs a pseudo video signal based on the pseudo synchronization signal and the color phase signal.