JPH04154383A - Horizontal synchronizing signal protecting circuit - Google Patents

Abstract

PURPOSE:To eliminate the omission and the fluctuation of a synchronizing signal and to eliminate the shift of a display on a display screen by inputting a dummy horizontal signal made by a secondary variable frequency division counter to an output timing generating circuit. CONSTITUTION:A dummy horizontal synchronizing signal 36 being an output of a secondary variable frequency division counter 23 is a 1/455 frequency division output of a frequency of a voltage control oscillator 11, therefore, its timing matches with a horizontal synchronizing input signal 37, and also, even when the horizontal synchronizing input signal 37 is missing, a normal output is executed. Accordingly, in an output timing generating circuit 24 for inputting the dummy horizontal synchronizing signal 36, a stable operation being free from a malfunction can be obtained, therefore, especially, when the circuit is used for an on-screen character display, even under a state that fluctuation and omission of the horizontal synchronizing input signal by the influence of a weak electric field, etc., exist, an easily visible screen on which a character display position on a television display screen does not shifts nor fluctuates can be obtained.

Description

[Detailed Description of the Invention] ° [Field of Industrial Application] The present invention relates to a horizontal synchronization signal protection circuit, particularly for on-screen character displays that display characters such as time and channel numbers on a television display screen. This invention relates to a horizontal synchronization signal protection circuit.

[Conventional technology]

Conventionally, in this type of on-screen character display circuit, a horizontal synchronization input signal inputted from an input terminal, together with a horizontal timing generation clock inputted from another input terminal, determines the time on the television display screen. Horizontal position 1 of character display such as channel number
The signal was directly input to the horizontal output timing generation circuit that controlled the output timing in the horizontal direction.

[Problem to be solved by the invention]

In the conventional circuit described above, the horizontal synchronization input signal is directly input to the output timing generation circuit that controls the display position, so the synchronization signal may be missing due to the influence of a weak electric field etc. on the horizontal synchronization input signal. Such a horizontal synchronizing signal causes the horizontal output timing generation circuit to malfunction, causing the character display position on the television display screen to shift or sway.

An object of the present invention is to provide a horizontal synchronization signal protection circuit which eliminates such drawbacks, eliminates synchronization signal loss and fluctuation, and eliminates display deviations on a display screen.
There is an oscillation circuit that oscillates at a frequency 0 times the frequency f of the horizontal synchronization signal, which is installed before the output timing generation circuit that outputs the timing of the on-screen display that displays pictures, etc., and 8 circuits of this oscillation circuit are counted. a timing discrimination circuit that compares and discriminates the change in the output of the first variable frequency division counter with the horizontal synchronization signal; and a control signal counting circuit that counts the discrimination results of the timing discrimination circuit. and a secondary variable frequency divider circuit whose frequency division ratio is controlled by the counting result of the control signal counting circuit and counts the output of the oscillation circuit, and outputs a dummy horizontal synchronization signal generated by the secondary variable frequency divider counter. It is characterized by being input to a timing generation circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, including an oscillation circuit 10, a first variable frequency division counter 20, a second variable frequency division counter 23, a timing discrimination circuit 21, a control signal counting circuit 22, and an output timing. It is composed of a generating circuit 25.

The oscillation circuit 10 also includes a voltage controlled oscillator 11 that receives the video signal color subcarrier from the input terminal 1 and oscillates at a frequency twice the video signal color subcarrier frequency. This is a PLL means that matches the phase with the subcarrier.

Since the video signal color subcarrier frequency is fsc, horizontal synchronization, and the frequency of the voltage controlled oscillator 11 is 2×fsc, horizontal synchronization timing can be obtained by dividing the frequency by 455 to create the frequency f)I.

This 455 frequency division counter has a primary variable frequency division counter of 20
There are two types, 1 and 23, and a secondary variable frequency division counter 23, each with a variable division ratio from 454 to 456,
The frequency division ratio is controlled by frequency division ratio control signals 32-35.

The primary variable frequency division counter 20 and the secondary frequency division counter 23 are reset by a reset signal from the initial setting reset terminal 3, and then count the output of the voltage controlled oscillator 11. The primary variable frequency division counter 2o outputs a signal 31 for timing comparison with the horizontal synchronization input signal 37 from the horizontal synchronization signal input terminal 2 to the timing discrimination circuit 21, and this timing discrimination circuit 21
7 and the timing comparison signal 31 are compared. If the horizontal synchronization input signal 37 is earlier than the timing comparison signal 31 by more than M consecutive cycles (M; 23.4...), the frequency division ratio is set to 45.
The frequency division ratio control signal 32 set to 4 is output to the primary variable frequency division counter 20, and thereafter the primary variable frequency division counter 20 divides the frequency by 454 once to output the timing comparison signal 31 earlier.

Similarly, if the horizontal synchronization input signal 37 is slower than the timing comparison signal 31 for more than M continuous periods, a frequency division ratio control signal 33 that sets the frequency division ratio to 456 is output to the primary variable frequency division counter. After that, the primary variable frequency division counter 20 will be counted once as 456.
The frequency is divided and the timing comparison signal 31 is outputted later.

This operation allows the timing comparison signal 31 to always capture the position of the horizontal synchronization input signal.

Further, the control signal counting circuit 22 which receives the frequency division ratio control signals 32 and 33 counts the frequency division ratio control signals 32 and 33,
If the signal 32 is output for two or more cycles while the signal 33 is not output, a frequency division ratio control signal 34 for setting the frequency division ratio to 454 is output to the secondary variable layer division counter 23. After this, the secondary variable frequency division counter 23 divides the frequency by 454 once.

Similarly, in the control signal counting circuit 22, if the signal 33 is output for two or more cycles while the signal 32 is not output,
The frequency division ratio control signal 35 that sets the frequency division ratio to 456 is output to the secondary variable frequency division counter 23, and then f! The secondary variable aggregation counter 23 divides the frequency by 456 once. When the signal 34.35 is not output, the secondary variable frequency dividing counter 23 will divide the frequency by 455. Due to this operation, the timing of the dummy horizontal synchronization signal 36, which is the output of the secondary variable frequency division counter 23, matches the horizontal synchronization input signal 37, and furthermore, the timing of the dummy horizontal synchronization signal 36, which is the output of the secondary variable frequency division counter 23, coincides with the horizontal synchronization input signal 37. Therefore, even if the horizontal synchronization input signal 37 is missing, normal output is performed. Therefore, stable operation without malfunction can be obtained in the output timing generation circuit 24 which receives the dummy horizontal synchronization signal 36 as input.

A timing diagram of this embodiment is shown in FIG. Figure 2 (a>
is an example in which the horizontal synchronization input signal 37 is earlier than the timing comparison signal 31 from the primary variable frequency division counter 20, and if the state of the X mark continues for more than M periods, the frequency division ratio control signal 3
Outputs 2. FIG. 2(b) is an example in which the horizontal synchronization input signal 37 is slower than the timing comparison signal 31. FIG. 2(c) is a diagram showing the relationship between the frequency division ratio control signal 32.33 and the signal 34.35. When the frequency division ratio control signal 32 is output for two or more cycles, the frequency division ratio control signal 34 is When the frequency division ratio control signal 33 is output for two or more cycles, the frequency division ratio control signal 35 is output.

The count M of the timing determination circuit 21 can correspond to the fluctuation period and number of omissions of the horizontal synchronization input signal.

〔Effect of the invention〕

As explained above, the present invention enables the output timing generation circuit to be stable even in situations where the horizontal synchronization input signal fluctuates or is missing due to the influence of weak electric fields, especially when used for on-screen character displays. Since the dummy horizontal synchronization signal is output, it is possible to obtain an easy-to-read screen that does not shift or shake the character display position on the television display screen.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2(a)
, (b) and (c) are timing diagrams in the above embodiment, respectively. 1. Video signal color subcarrier input terminal, 2. Horizontal synchronization signal input terminal, 3. Initial state setting terminal, 4. Clock input terminal for horizontal timing generation, 5. Output terminal, 10
...Oscillation circuit (PLL means), 11. Voltage controlled oscillator, 12.. Frequency divider, 13. Phase comparator, 14.. Integrator, 21. Timing discrimination circuit, 22.. Control signal counting circuit. , 232nd order variable frequency division counter, 24... Output timing generation circuit, 31... Timing comparison signal, 3
2 to 35: Frequency division ratio control signal, 36: Dummy horizontal synchronization signal, 37: Horizontal synchronization input signal.

Claims (1)

[Claims] The frequency f of the horizontal synchronizing signal is provided before the output timing generation circuit that outputs the timing of the on-screen display that displays predetermined characters, pictures, etc. on the display screen.
An oscillation circuit that oscillates at a frequency n times higher than _H, a primary variable fractional counter that counts the output of this oscillation circuit, and a timing for comparing the output change of this primary variable frequency division counter with the horizontal synchronization signal to determine the timing. a discrimination circuit; a control signal counting circuit that counts the discrimination results of the timing discrimination circuit;
and a secondary variable frequency divider circuit whose frequency division ratio is controlled by the counting result of the control signal counting circuit and counts the output of the oscillation circuit, and outputs a dummy horizontal synchronization signal generated by the secondary variable frequency divider counter. A horizontal synchronization signal protection circuit characterized in that it is input to a timing generation circuit.