KR100234738B1 - Synchronous processing apparatus for lcd projector - Google Patents

Abstract

The present invention relates to a synchronous processing apparatus for a liquid crystal projector, and more particularly, to a synchronous processing apparatus for a liquid crystal projector, in which a horizontal synchronizing signal before AFC is used during a copy protection period or header switching and a read and a write clock are different from each other, It was invented. The present invention relates to a semiconductor memory device which is enabled to a reference signal WRES and stores an output signal of the analog / digital conversion means 211 in accordance with a write clock, is enabled in a reference signal RRES and outputs stored data in accordance with a read clock, A phase synchronizing unit 214 for generating a reference clock signal WRES and a write clock by receiving a horizontal synchronizing signal after the AFC and an output clock of the clock generator 216 to generate a free running clock A phase adjusting unit 215 receiving a horizontal synchronizing signal after AFC and outputting a double speed synchronizing signal on the basis of a vertical synchronizing signal and generating a read clock and a read reference signal, A switch SW1 for selecting one of the output clocks of the phase synchronization unit 214 and the adjustment unit 215 and outputting it as a write clock, And a switch SW2 for selecting one of the output reference signals and outputting it as a reference signal WRES.

Description

Synchronous Processing Device of Liquid Crystal Projector

Figure 1 is a block diagram of a typical liquid crystal projector.

FIG. 2 is a block diagram of a conventional double speed processing circuit. FIG.

FIG. 3 is an example showing a position where deterioration of image quality generally occurs. FIG.

4 is a block diagram of an embodiment according to the present invention.

FIG. 5 is a timing chart showing a refresh interval of a double speed synchronizer in the present invention. FIG.

FIG. 6 is a timing chart at the time of head switching in the present invention. FIG.

Description of the Related Art

211: analog / digital conversion unit 212: memory

213: LCD driver 214:

215: phase regulator 216: clock generator

The present invention relates to a liquid crystal projector, and more particularly, to a synchronous processing apparatus of a liquid crystal projector for stabilizing an unstable synchronous signal.

Typically, a liquid crystal projector must have a resolution of 640 * 480, since it must be compatible with video signals and PC signals (VGA signals).

In other words, the resolution of most LCD panels is composed of 640 (H) * 480 (V) pixels.

Therefore, the interlaced video signal of the NTSC system requires 262.5 lines per field, so that the 480-line LCD signal must be subjected to the speed-up processing to scan the video signal.

In general, in most cases, the liquid crystal projector has a completely independent structure of the LCD drive circuit.

That is, as shown in FIG. 1, a general liquid crystal projector is structured such that the double speed processing circuit 101 and the LCD drive circuit 102 are independent from each other in order to speed-up the video signal.

The double speed processing circuit (PLL1) 101 receives the horizontal synchronizing signal (Hsync) and outputs the double speed synchronizing signal (2HS) to the LCD driving circuit (102).

The LCD drive circuit 102 includes a phase locked loop (PLL2) and an LCD (LCD).

As shown in FIG. 2, the conventional speed-up processing circuit includes an analog / digital conversion section 111 for digitally converting an analog video signal in synchronization with a clock WCLK, A memory 112 for storing an output signal of the analog / digital conversion unit 111 according to a clock signal RCLK and for outputting stored data according to a clock RCLK enabled by a reference signal RRES, And outputs a control signal WRES (RRES) and a clock WCLK (RCLK) to the analog / digital conversion unit 111 and the memory 112 as inputs and generates a synchronous signal 2HS And an LCD drive circuit 113 for receiving an output signal of the memory 112 and displaying an image based on the synchronization synchronizing signal 2HS of the phase synchronizer 114.

The LCD drive circuit 113 includes a phase locked loop (PLL2) and an LCD (LCD).

The operation of the conventional art will be described as follows.

The phase synchronizer 114 receiving the 15.75 kHz horizontal synchronizing signal Hsync generates the clock WCLK RCLK and the reference signal WRES RRES and the double speed synchronizing signal 2 HS.

At this time, the analog / digital conversion unit 111 performs digital conversion on the analog video signal in synchronization with the clock WCLK, and outputs the analog video signal to the memory 112.

Accordingly, the memory 112 enabled to the reference signal WRES generated by the phase synchronizer 114 is switched to the analog / digital converter 111 according to the clock WCLK generated by the phase synchronizer 114, And stores the output signal of the output terminal.

Thereafter, the memory 112 is enabled to the reference signal RRES of the phase synchronizer 114 and outputs the stored data to the LCD drive circuit 113 in accordance with the clock RCLK.

The LCD drive circuit 113 scans the output signal of the memory 112 on the screen based on the double speed synchronizing signal 2HS of the horizontal synchronizing signal Hsync output from the phase synchronizing section 114, .

That is, the LCD drive circuit 113 drives the LCD according to the output signal of the phase locked loop PLL2, which receives the double speed synchronizing signal 2HS of the phase synchronizer 114, The image is displayed by scanning the signal.

However, in the related art, when the horizontal synchronizing signal Hsync passes through two phase-locked loops (PLL), the picture is distorted when the horizontal synchronizing signal Hsync is unstable.

For example, if the VCR (VCR) operates in the double or search mode, the horizontal synchronization is very unstable, so that the two PLLs are not locked and the picture quality is greatly degraded.

In addition, conventionally, video signals are reproduced by rotation of a video header to display an image on a screen, which causes deterioration of image quality when the rotation speed is unstable.

Particularly, in the header switching section at the lower end of the screen, the synchronization is unstable and the screen is shaken.

In other words, conventionally, when the headers are switched and the copier is attached to the video tape, the section of the copier becomes unstable in the section after the vertical synchronizing signal, that is, in the section where the image starts to appear, It is warped and displayed.

The section where such screen deterioration occurs is the same as the example of FIG.

In order to solve the conventional problems, the present invention provides a liquid crystal projector in which a horizontal synchronizing signal before AFC is used in a copy protection period or a header switching, and a read and a write clock are made different from each other in an overall section of a screen, And to provide a synchronization processing apparatus of the same.

In order to achieve the above object, the present invention provides an analog / digital conversion means for converting an analog video signal into a digital signal in synchronism with a write clock, and an output means for outputting the output signal of the analog / digital conversion means in accordance with a write clock, A memory means for storing the read reference signal and outputting the stored data in accordance with the read clock, a phase synchronizing means for generating a write reference signal and a write clock by inputting a horizontal synchronizing signal after the AFC, A free running clock is generated by counting the output clock of the clock generating means, a horizontal synchronous signal after the AFC is received, a double clock synchronous signal is outputted on the basis of the vertical synchronous signal, and a lead clock and a lead A phase adjusting means for generating a reference signal, A first switching means for selecting an output clock of the phase adjusting means in an interval in which the leveling synchronization is unstable and selecting the output clock of the phase synchronization means in a period in which the horizontal synchronization is stable and outputting the selected output clock as a write clock; And a second switching means for selecting an output reference signal of the phase synchronization means and outputting it as a write reference signal in a period in which the horizontal synchronization is stable.

Wherein the phase adjusting means is provided for each vertical synchronization signal. So that the double speed synchronizing signal is reset.

In this case, the write clock and the read clock are different from each other, thereby stabilizing the synchronization signal.

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 4 is a block diagram showing an embodiment of the present invention. As shown in FIG. 4, an analog / digital converter 211 for digitally converting an analog video signal in synchronization with a clock WCLK, A memory 212 for storing an output signal of the analog / digital converter 211 according to a clock WCLK and being enabled by a reference signal RRES and outputting stored data according to a clock RCLK, A phase synchronizer 214 for generating a reference signal WRES and a clock CLK1 by inputting a synchronizing signal Hsync2, a clock generator 216 for oscillating a clock CLK of 28.6 MHz, And outputs the divided free running clock signal CLK2 and outputs the double speed synchronizing signal 2HS on the basis of the vertical synchronizing signal VS with the horizontal synchronizing signal Hsync2 as an input In addition, a phase adjustment for generating a clock (RCLK) and a control signal (RRES) And the output clocks CLK1 and CLK2 of the phase synchronization unit 214 and the phase adjustment unit 215 to output the write clock WCLK to the analog / digital conversion unit 211 and the memory And outputs the write reference signal WRES to the memory 212 by selecting one of the horizontal synchronizing signal Hsync1 without the AFC and the output clock of the phase synchronizing unit 214 And a switch SW2.

The operation and effect of the present invention will be described as follows.

The phase synchronization unit 214 receiving the 15.75 kHz horizontal synchronization signal Hsync2 generates a clock and a reference signal for use in a period in which the horizontal synchronization is stable and the phase can be stabilized.

The phase adjusting unit 215 receives the output of the clock generator 216 to generate a free running clock and receives the horizontal synchronizing signal Hsync2 to generate a clock RCLK The control signal RRES is generated and the 2-times speed synchronizing signal 2HS is generated.

At this time. The switch SW1 receives the output clock of the phase synchronizing unit 214 and the output clock of the phase adjusting unit 215 and selects the output clock of the phase synchronizing unit 214 in a period in which the horizontal synchronization is unstable, Digital converter 211 and the memory 212 by selecting the output clock of the phase adjusting unit 215. The analog /

The switch SW2 receives the horizontal synchronizing signal Hsync1 and the synchronizing signal of the phase synchronizing unit 214 and selects the horizontal synchronizing signal Hsync1 in the period in which the horizontal synchronizing signal is unstable, And outputs the reference signal WRES to the memory 212 by selecting the output synchronization signal of the phase synchronization unit 214. [

Accordingly, when the analog / digital conversion unit 211 performs the analog-to-digital conversion of the analog video signal, the memory 212 is enabled to the control signal WRES input from the switch SW2, WCLK).

Thereafter, the memory 212 is enabled to the reference signal RRES of the phase adjusting unit 215 and outputs the stored data to the LCD driver 213 in accordance with the clock RCLK.

Therefore, the LCD driver 213 receives the output data of the memory 212 according to the double speed synchronizing signal 2HS in the phase adjusting unit 215, and drives the LCD to display an image.

In performing the above-described operation, the phase-locked loop (PLL) can not be locked from this line to the last line in the header switching period because the horizontal synchronization is unstable until 3 μs compared to the reference horizontal synchronization. The video signal and the synchronizing signal are shifted from each other, and the screen is warped or completely broken.

In the case of a video tape that is copy protected, since the signal is shaken to such an extent that the synchronization can not be separated to the entire line where the screen is displayed, if the AFC is used, the copy protection section affects the section where the screen is displayed .

Therefore, in the two sections, the switch SW1 selects the sync signal Hsync1 before the AFC separated from the composite video signal as the reference signal WRES for the write operation of the memory 212, The unstable part of the upper and lower portions of the screen is stabilized by compensating for the bending of the screen by using the frequency (CLK2) of 14.3 MHz frequency dividing the oscillation frequency of MHz as the clock (WCLK).

The timing chart of these parts is shown in Fig.

On the other hand, most liquid crystal projectors are composed of two phase-locked loops (PLLs) as in the first aspect. If the phase-locked loop of the first stage is unstable, the phase-locked loop of the second stage is affected, Or one or two lines are twisted.

Accordingly, in the present invention, the double-speed synchronizing signal 2HS output from the phase adjusting unit 215 is generated at 31.5 kHz to stably operate the phase-locked loop PLL2 of the LCD driver 213. [

That is, the phase adjusting unit 215 counts the oscillation frequency of 28.6 MHz of the clock generator 216 by 910 and outputs the frequency of 31.5 kHz as the double-speed synchronizing signal 2 HS.

As a result, the deterioration of image quality caused by the phase locked loop PLL2 hardly occurs.

However, when the frequency of 31.5 kHz is generated as the free running clock, the write and read operations in the memory 212 are not timed to each other, and the signal of the previous line may be read in a certain period.

Accordingly, as shown in FIG. 5, the double-speed synchronizing signal 2HS is refreshed every one vertical synchronizing signal to generate a synchronizing signal, thereby preventing deterioration of the screen.

The phase synchronization loop can not be locked in the vertical synchronization period as in the fifth aspect, and the required period from when the synchronization signal is unstable in the phase synchronization loop PLL2 of the LCD driver 213 to when the synchronization signal is unstable is the double speed synchronization signal 2HS, About 25 cycles on the basis of.

However, since this interval is a vertical retrace interval which does not appear on the screen, it is not related to the delay, and therefore, it is not related to image quality.

That is, in the present invention, during the copy protection period or the header switching for the picture quality period of the third aspect, the screen deterioration is eliminated by using the horizontal synchronization signal Hsync1 and the free running clock CLK2 before the AFC, The screen deterioration of the phase-locked loop is eliminated by differentiating the write clock WCLK and the read clock RCLK.

As described above in detail, according to the present invention, the synchronization signal is appropriately processed according to whether the synchronization is unstable or not, thereby eliminating the screen warping phenomenon at the upper and lower ends of the screen, The effect of eliminating the synchronization deflection phenomenon is eliminated.

Claims (4)

An analog / digital conversion means for digitally converting the analog video signal in synchronization with the clock WCLK; an analog / digital conversion means for enabling the reference signal WRES to store the output signal of the analog / digital conversion means in accordance with the clock WCLK, A memory means for outputting stored data in accordance with a clock RCLK enabled by the clock signal RRES, a phase synchronizing means for generating a reference signal RES1 and a clock CLK1 by inputting the horizontal synchronizing signal Hsync2, A clock generating means for generating a free running clock CLK2 by counting a clock CLK of the clock generating means and receiving a horizontal synchronizing signal Hsync2 as a reference and outputting a vertical synchronizing signal VS as a reference Phase synchronizing means for synchronizing the output clocks CLK1 and CLK2 of the phase adjusting means and the output clocks CLK1 and CLK2 of the phase adjusting means to generate a clock RCLK and a control signal RRES, Selection A first switching means for outputting a clock (WCLK) to the analog / digital conversion means and the memory means, and a second switching means for selecting one of the horizontal synchronization signal (Hsync1) before the AFC and the output signal (RES1) And outputting the reference signal (WRES) to the memory means. 2. The phase locked loop circuit according to claim 1, wherein the first switching means selects the output clock (CLK2) of the phase adjusting means in a period in which the horizontal synchronization is unstable, selects the output clock (CLK1) (WCLK) of the synchronizing signal. The apparatus according to claim 1, characterized in that the second switching means selects the horizontal synchronizing signal (Hsync1) before the AFC in the section in which the horizontal synchronization is unstable, selects the output signal (RES1) WRES). ≪ / RTI > The synchronous processing apparatus according to claim 1, wherein the phase adjusting means resets the double speed synchronizing signal for each vertical synchronizing signal.