JP4646637B2 - Genlock device - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit suitable for application to a genlock device that synchronizes an input signal and an output signal.

  As represented by television systems such as NTSC, PAL, and SECAM, there are various types of video signals with different field frequencies and the number of scanning lines. In recent years, they are used as video display devices for personal computers. Diversification of video signals is progressing.

  Therefore, a genlock device is used to convert these video signals into other forms for display. The genlock device, for example, generates a WCK (write clock) synchronized with an input video signal, and writes the input video signal converted into a digital signal in a memory in a field or frame unit. Thereafter, the data is read from the memory and converted into an analog signal by the read clock RCK corresponding to the signal form to be converted. According to this configuration, since the normal video signal frequency is obtained for the video signal to be converted with respect to the input video signal, the video field, frame omission, and duplication do not occur.

  In order to realize this, for example, the genlock configuration shown in Patent Document 1 has been proposed, and the configuration is shown in FIG. In FIG. 4, 101 is an input terminal for the video signal VI, 102 is a synchronization separation circuit for separating the horizontal synchronization signal HS from the input signal VI, 103 is a clock generation circuit for generating a write clock that is phase-synchronized with the separated synchronization signal HS, Reference numeral 104 denotes an A / D conversion circuit that samples the input video signal VI from the terminal 101 with the write clock WCK and converts it into digital data.

  A frequency dividing circuit 105 divides the horizontal synchronizing signal HS separated from the input signal by N (N is a natural number) and outputs a phase comparison signal R, and 106 divides the signal from the phase comparison reference signal R from the frequency dividing circuit 105. The phase comparator 107 compares the phases of the two signals of the phase comparison signal V from the peripheral circuit 107 and outputs a phase error signal. 107 is a read clock RCK generated by the voltage controlled oscillator 108 for M (M is a natural number). A frequency divider circuit that circulates and supplies it to the phase comparator 106 as the phase comparison signal V is shown.

  Further, 108 is a voltage-controlled oscillator with high frequency stability and a narrow variable frequency range, 109 is a control circuit that generates a control signal group necessary for the signal processing circuit 110 including the write clock WCK and the read clock RCK, and 110 is an A / A A signal processing circuit that converts a signal converted into digital data by the D conversion circuit 104 into a video signal of a different form using an internal memory, 111 is a memory circuit provided in the signal processing circuit 110, and 112 is a signal processing A D / A conversion circuit 113 converts the digital data processed by the circuit 110 into an analog signal and outputs it as an output signal VO, and 113 represents an output terminal of the output signal VO.

  This read clock RCK divides the write clock WCK having the frequency fw generated from the input video signal by N (FIG. 4 shows an example of dividing HS by N, but WCK may be divided by N). A read clock RCK having a frequency of fr = fw × M / N can be obtained by multiplying this signal by M by a PLL (phase lock loop) using this signal as a reference signal. That is, one input frequency of the phase comparator 106 is fw / N and the other input frequency is fr / M. When these input frequencies and output frequencies coincide with each other, phase comparison becomes possible, so fw / N = Fr / M. Consequently, a read clock (read clock specified in the video signal to be converted) of fr = fw × M / N is generated.

Therefore, since the normal video signal frequency is obtained for the video signal to be converted with respect to the input video signal, the video field or frame is not lost or duplicated. That is, the scan time of one horizontal period is basically different due to the difference in the television system, but when one field or one frame is scanned, by matching the time regardless of the difference in the television system, The above-mentioned omission and duplication are not caused.
JP-A-5-207413

  However, the conventional genlock device including the above-described Patent Document 1 includes two analog circuits, ie, a phase comparator and a voltage controlled oscillator. In general, an LSI in which analog circuits are mixed has a more complicated process than an LSI composed of only digital circuits, resulting in a decrease in yield and an increase in shipment test items such as a Wafer test. There is a problem that the LSI unit price is high.

  An object of the present invention is to provide a genlock device configured without using an analog circuit other than an A / D conversion circuit and a D / A conversion circuit. .

In order to solve the above problems, the following configuration is mainly employed in the present invention.
An input video signal is A / D converted, the A / D converted digital data is converted into a video signal of a different signal format using a memory, and the converted digital data is D / A converted. A genlock device that outputs an output video signal,
Counting means for counting the clock from the clock generating means from the time of power-on,
Holding means A for holding the count value of the counting means at an interval of a synchronization signal synchronized with the input video signal;
Holding means B for holding the count value of the counting means at an interval of a synchronizing signal synchronized with the output video signal;
A calculation means for calculating the count difference by inputting the count values held by the holding means A and the holding means B;
Control means for generating a synchronization signal to be input to the holding means B based on the calculation result of the count difference by the calculating means,
The digital data is read out from an address corresponding to the line head of the memory in response to a synchronization signal generated by the control means and input to the holding means B.
The count values held by the holding means A and the holding means B are taken in at the edge of the latest sync signal and the values N (A) and N (B) taken at the latest sync signal edge. Values (N-1) (A) and (N-1) (B)
The calculating means is | N (A) − (N−1) (A) | which is the difference between the N (A) and the (N−1) (A) in the holding means A, and the holding means B. | N (B) − (N−1) (B) |, which is the difference between N (B) and (N−1) (B), is calculated as | N (A ) - (N-1) ( a) | - | N (B) - (N-1) (B) | a a structure to the calculation result.

The input video signal is A / D converted, the A / D converted digital data is converted into a video signal of a different signal format using a memory, and the converted digital data is converted to D / D. A genlock device that performs A conversion and outputs an output video signal,
First clock generation means for generating a clock for the D / A conversion;
A second clock generation means that is separate from the first clock generation means and is capable of adjusting a clock frequency;
Counting means for counting the clock from the second clock generating means from the time of power-on;
Holding means A for holding the count value of the counting means at an interval of a synchronization signal synchronized with the input video signal;
Holding means B for holding the count value of the counting means at an interval of a synchronizing signal synchronized with the output video signal;
A calculation means for calculating the count difference by inputting the count values held by the holding means A and the holding means B;
Control means for generating a synchronization signal to be input to the holding means B based on the calculation result of the count difference by the calculating means,
In response to a synchronization signal generated by the control means and input to the holding means B, the digital data is read from an address corresponding to the line head of the memory,
The count values held by the holding means A and the holding means B are taken in at the edge of the latest sync signal and the values N (A) and N (B) taken at the latest sync signal edge. Values (N-1) (A) and (N-1) (B)
The calculating means is | N (A) − (N−1) (A) | which is the difference between the N (A) and the (N−1) (A) in the holding means A, and the holding means B. | N (B) − (N−1) (B) |, which is the difference between N (B) and (N−1) (B), is calculated as | N (A ) − (N−1) (A) | − | N (B) − (N−1) (B) | as the calculation result, and when the predetermined time has elapsed after power-on, the second clock The clock frequency of the generation unit is reduced.

  According to the present invention, a free-run counter and a register for holding and updating the output of the free-run counter at regular intervals are provided on the input video signal side and the output video signal side, respectively, and the count value held in each register is set. The difference (count value held by the latest sync signal-count value held by the previous sync signal) can be calculated, and the phase on the output video signal side can be adjusted based on the calculation result. The signal and the output video signal are kept in a locked relationship, and as a result, no video field, frame loss, or duplication occurs.

  In addition, by making the frequency of the clock that is input to the free-run counter variable independently of other clocks, this clock frequency is set low when the accuracy of the phase difference between the input video signal and the output video signal is not required. Therefore, low power consumption can be achieved.

  A genlock device according to an embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a block diagram showing a configuration of a genlock device according to a first embodiment of the present invention. FIG. 2 is an explanatory diagram showing the number of clocks in the horizontal and vertical directions at the time of panel output in the genlock apparatus according to the embodiment of the present invention. FIG. 3 is a block diagram showing the configuration of the genlock device according to the second embodiment of the present invention.

“First Embodiment”
In FIG. 1, 1 is an input terminal for a video signal VI, 2 is a synchronization separation circuit for separating a synchronization signal from the input signal VI, 3 is a clock generation circuit for generating a write clock WCK phase-synchronized with the separated horizontal synchronization signal HS_A, 4 is an A / D conversion circuit that samples the input video signal VI from the terminal 1 with the write clock WCK and converts it into digital data, and 5 is a panel clock PCK (for example, a clock for displaying on the VGA panel) that controls the entire LSI. Panel clock generation circuit to be generated, 6 is a free-run counter that operates with the panel clock PCK and free-runs after the power is turned on, 7 is a register A that fetches the count value of the free-run counter 6 at the timing of the synchronization signal VS_A, 8 is free The timing of the sync signal VS_B, which will be described later, is used as the count value of the run counter 6. Capturing register B, 9 represents arithmetic circuit for calculating the difference captures the count value held in the register A7 and register B8, respectively.

  Further, 10 is a control circuit B that generates the synchronization signal VS_B based on the result of the arithmetic circuit 9, and 11 is a control circuit A that generates a control signal group necessary for the signal processing circuit 12 from the write clock WCK and the panel clock PCK. , 12 is a signal processing circuit for converting a signal converted into digital data by the A / D conversion circuit 4 into a video signal of a different signal form using an internal memory, and 13 is a memory provided in the signal processing circuit 12 Reference numeral 14 denotes a D / A conversion circuit that converts digital data processed by the signal processing circuit 12 into an analog signal and outputs the analog signal as an output signal VO. Reference numeral 15 denotes an output terminal of the output signal VO.

  The present embodiment is applied to a genlock device for converting an input video signal into a video signal of a different signal form. Here, an NTSC signal (field frequency 59.94 Hz, 1 frame 525 lines, horizontal synchronization frequency fh) is applied. = 15.734 KHz) An example of displaying an input video signal VI on a VGA panel (640 × 480 pixels) is shown.

  When the video signal VI input from the input terminal 1 is sampled at, for example, 4 fsc (four times the frequency of the color subcarrier), that is, fw = 14.331818 MHz (fh × 910), the frequency obtained by dividing WCK by 910 ( The clock generation circuit 3 is configured so that fw / 910) is equal to the frequency fh (15.734 KHz) of HS_A.

  The write clock WCK generated by the clock generation circuit 3 is input to the A / D conversion circuit 4 and the control circuit A11. In the A / D conversion circuit 4, the video signal VI input from the terminal 1 is sampled by the write clock WCK, converted into a digital signal, and input to the signal processing circuit 12. In accordance with the control signal group generated by the control circuit A11, the signal processing circuit 12 sequentially writes the digital data input from the A / D conversion circuit 4 into the memory 13 so as to have the same address for each field.

  On the other hand, consider a case where the panel clock PCK generated by the panel clock generation circuit 5 is 27 MHz. If the number of bits of the free-run counter 6 is 20 bits, for example, the panel clock PCK always counts from 0 to 1048575 after the power is turned on.

  For example, the register A7 captures the count value of the free-run counter 6 at the falling timing of the synchronization signal VS_A, and similarly captures the count value of the free-run counter 6 at the falling timing of the synchronization signal VS_B. The frequency fv_a of the synchronization signal VS_A is (2/525) fh = 59.93904... Hz (field frequency of the NTSC signal), and the frequency of the synchronization signal VS_B is derived from (PCK / number of horizontal clocks) / number of vertical lines. It is.

  Then, the register A7 and the register B8 can take in the count value of the free-run counter 6 again at the fall of the next synchronization signals VS_A and VS_B. That is, the register A7 and the register B8 can hold the count value acquired by the synchronization signal for at least two cycles. Here, the count values are CA0, CA1 (register A7 side), CB0, CB1 (register B8 side).

  The arithmetic circuit 9 reads the count values CA0 and CA1 held in the register A7 and the count values CB0 and CB1 held in the register B8, calculates the difference between them, and based on the result, sends the control signal to the control circuit B. Output to. That is, the arithmetic circuit 9 first calculates CA2 = | CA0-CA1 | and CB2 = | CB0-CB1 |, further calculates | CB2-CA2 |, and the control circuit B10 generates the synchronization signal VS_B from the result. .

  For example, if the difference | CB2−CA2 | between the count value CA2 and the count value CB2 calculated by the arithmetic circuit 9 is larger for each synchronization signal, the interval between the synchronization signals VS_B is wider than the interval between the synchronization signals VS_A. For this reason, the arithmetic circuit 9 acts on the control circuit B10 so as to narrow the cycle of the synchronization signal VS_B. Conversely, if the difference | CB2−CA2 | between the count value CA2 and the count value CB2 calculated by the arithmetic circuit 9 is small, it indicates that the interval of the synchronization signal VS_B is narrower than the interval of the synchronization signal VS_A. Therefore, the arithmetic circuit 9 controls the control circuit B10 so as to widen the cycle of the synchronization signal VS_B.

  The synchronization signal VS_B is simultaneously input to the control circuit A11, and the signal processing circuit 12 reads data from the address corresponding to the head of the line from the memory 13 by the control signal group generated by the control circuit A11. The data read from the memory 13 is converted into analog data by the D / A conversion circuit 14 at the timing of the panel clock PCK and output from the output terminal 15 as the output signal VO.

  Here, since the PCK is displayed on the VGA panel at 27 MHz, the horizontal and vertical clock numbers (Htotal and Vtotal) shown in FIG. 2 are derived from the following calculations. In order to output to the VGA panel, Hactive = 640, Vactive = 480, and if the horizontal synchronization frequency is 31.5 KHz and the vertical synchronization frequency is 60 Hz, 27 MHz / 31.5 KHz = 857.142, 31.5 KHz / 60 Hz = 525. Therefore, Htotal is approximately 857 and Vtotal is 525, and at this time, the relationship between the input video signal and the panel output is substantially locked.

  However, since Htotal and Vtotal need to be positive integers, the horizontal synchronization frequency is actually 27 MHz / 857 = 31.50525 KHz, for example, and the vertical synchronization frequency fv_b is 31.50525 KHz / 525 = 60. Because it is 01 Hz, it is not the same frequency as fv_a ((2/525) fh = 59.93904... Hz), and it cannot be said that it is strictly locked. Become.

  At this time, since the relationship fv_a <fv_b is established, the difference | CB2−CA2 | between the count value CA2 and the count value CB2 tends to be narrowed for each vertical synchronization signal, so the arithmetic circuit 9 sends the synchronization signal VS_B to the control circuit B10. Work to widen the cycle. For example, when Htotal is controlled, that is, when Htotal is set to 859, 27 MHz / 859 = 31.43189 KHz, the vertical synchronization frequency fv_b is 31.43189 KHz / 525 = 59.87026 Hz, and the relationship of fv_a> fv_b is established, so the synchronization signal VS_B This period tends to be wider than VS_A.

  Next, if the relationship of fv_a> fv_b continues for a long time, it may cause omission and duplication of video fields and frames. Therefore, by returning Htotal to, for example, 857, the relationship of fv_a <fv_b is established, and the period of the synchronization signal VS_B Tends to be narrower than VS_A.

  Thus, if the relationship of fv_a <fv_b is satisfied, the value of Htotal is increased, and conversely, if the relationship of fv_a> fv_b is satisfied, the value of Htotal is decreased, thereby maintaining the relationship where the input video signal and the panel output are locked, As a result, video fields and frames are not lost or duplicated.

“Second Embodiment”
FIG. 3 is a block diagram showing a configuration of a genlock device when an input video signal is converted into a video signal having a different signal format according to the second embodiment of the present invention. In FIG. 3, 1 is an input terminal for the video signal VI, 2 is a sync separator for separating the sync signal from the input signal VI, 3 is a clock generator for generating a write clock WCK that is phase-synchronized with the separated horizontal sync signal HS_A, 4 is an A / D conversion circuit that samples the input video signal VI from the terminal 1 with the write clock WCK and converts it into digital data, 5 is a panel clock generation circuit that generates a panel clock PCK that controls the entire LSI, and 16 is a clock FCK. The generated clock generation circuits B and 6 are operated by the clock FCK and are free-run counters that are free-running after the power is turned on. The count value of the counter 6 is obtained at the timing of a synchronization signal VS_B described later. Writing register B, 9 represents arithmetic circuit for calculating the difference captures the count value held in the register A7 and register B8, respectively.

  Further, 10 is a control circuit B that generates the synchronization signal VS_B based on the result of the arithmetic circuit 9, and 11 is a control circuit A that generates a control signal group necessary for the signal processing circuit 12 from the write clock WCK and the panel clock PCK. , 12 is a signal processing circuit for converting a signal converted into digital data by the A / D conversion circuit 4 into a video signal of a different form using an internal memory, and 13 is a memory circuit provided in the signal processing circuit 12 , 14 represents a D / A conversion circuit that converts the digital data processed by the signal processing circuit 12 into an analog signal and outputs the analog signal, and 15 represents an output terminal of the output signal VO.

  Here, the clock generation circuit B16 is a circuit that generates a clock by dividing a system clock (not shown), for example, and can freely generate a frequency equal to or lower than the system clock. Therefore, since the frequency of the clock FCK can be controlled, it is possible to adjust the progress of the count value of the free-run counter. In other words, the frequency of the clock FCK is set high in an excessive state such as immediately after the power is turned on, the accuracy of the count value stored in the register A7 and the register B7 is increased, and the problem is not caused in the stable state from the excessive period. The frequency of the clock FCK can be set low to reduce power consumption.

  As in the first embodiment of the present invention described above, the input video signal VI of the NTSC signal (field frequency 59.94 Hz, 1 frame 525 lines, horizontal synchronization frequency fh = 15.734 KHz) is converted into a VGA panel (640 × 480). An example of display on a pixel) is shown.

  When the video signal VI input from the input terminal 1 is sampled at, for example, 4 fsc (four times the frequency of the color subcarrier), that is, fw = 14.331818 MHz (fh × 910), the frequency obtained by dividing WCK by 910 ( The clock generation circuit 3 is configured so that fw / 910) is equal to the frequency fh (15.734 KHz) of HS_A.

  The write clock WCK generated by the clock generation circuit 3 is input to the A / D conversion circuit 4 and the control circuit A11. In the A / D conversion circuit 4, the video signal VI input from the terminal 1 is sampled by the write clock WCK, converted into a digital signal, and input to the signal processing circuit 12. In accordance with the control signal group generated by the control circuit A11, the signal processing circuit 12 sequentially writes the digital data input from the A / D conversion circuit 4 into the memory 13 so as to have the same address for each field.

  On the other hand, consider a case where the clock FCK generated by the clock generation circuit B16 is 1 MHz. If the number of bits of the free-run counter 6 is, for example, 20 bits, the clock FCK always counts from 0 to 1048575 after the power is turned on. Since the clock FCK is 1 MHz, one count is 1000 ns. This is called 1000 ns resolution.

  The values of the registers A7 and B8 captured at the fall of the vertical synchronization signals VS_A and VS_B at a certain moment are set to CA0 and CB0, and the values of the registers A7 and B8 captured at the fall of the next vertical synchronization signals VS_A and VS_B Is CA1 and CB1, the vertical synchronization signals VS_A and VS_B are approximately 60 Hz, respectively. For example, | CA1-CA0 | is 16666 and | CB1-CB0 | is 16667. That is, the difference between | CA1−CA0 | and | CB1−CB0 | is 1 count, which indicates that the period of the vertical synchronization signal VS_A is narrower by about 1000 ns than the vertical synchronization signal VS_B. Further, since the clock FCK is 1 MHz, it also means that an interval shift shorter than 1000 ns cannot be measured.

  If the time is stable after the power is turned on, the vertical synchronization signal interval is considered to be substantially constant. Therefore, no problem occurs even if the deviation of the interval shorter than 1000 ns cannot be measured. However, it is advantageous that the deviation between the vertical synchronization signals VS_A and VS_B can be detected with the smallest possible value immediately after the power is turned on or immediately after the frequency of the vertical synchronization signal changes.

  For example, when the clock FCK is 100 MHz, one count of the free-run counter 6 is 10 ns. Therefore, it is possible to detect a deviation between the vertical synchronization signals VS_A and VS_B with a resolution of 10 ns, and it is possible to correct a smaller deviation as compared with the case where the clock FCK is 1 MHz.

  In the second embodiment, the number of bits of the free-run counter 6 is 20 bits, but any number of bits can be used as long as it can count the time for displaying several frames. Further, the frequency of the clock FCK generated by the clock generation circuit B16 is not limited to 1 MHz and 100 MHz, and can be freely selected. Furthermore, the signals input to the register A7 and the register B8 are synchronization signals synchronized with the input video signal or the output video signal, but need not be the output of the synchronization separation circuit.

  As described above, in the first embodiment of the present invention, a free-run counter that operates with a fixed frequency clock and a register that holds and updates the output of the free-run counter at regular intervals are output to the input video signal side. The relationship between the input video signal and the output video signal is locked because it is provided on the video signal side, and the difference between the count values held in the previous register can be calculated and the phase on the output video signal side can be adjusted according to the calculation result. As a result, there is no occurrence of video field, frame loss, or duplication.

  Further, in the second embodiment, the frequency of the clock input of the free-run counter in the first embodiment can be controlled, so that the input video signal and the output video signal are not only kept in a locked relationship. In a stable state where a sufficient time has elapsed after the power is turned on, the frequency can be lowered and power consumption can be reduced.

  As described above, the semiconductor integrated circuit of the genlock device according to the embodiment of the present invention includes the following configuration. That is, a synchronization separation circuit that synchronously separates a video input signal, a clock generation circuit that generates a first clock from a first synchronization signal generated by the synchronization separation circuit, and sampling A / An A / D conversion circuit that performs D conversion, a panel clock generation circuit that generates a second clock that is a panel clock, a signal processing circuit that receives the A / D converted digital data, and a signal processing circuit And a memory that is written in frame or field units with the first clock and reads out with the second clock, and the output digital data of the signal processing circuit is converted into analog data at the timing of the second clock. A D / A conversion circuit for converting to a first control circuit, a first control circuit controlled by the first clock and the second clock, and the second clock A free-run counter that operates and counts by free-run, a first register that captures a count value of the free-run counter at a cycle of the first synchronization signal, and a second synchronization signal that operates by the second clock And a second register that captures the count value of the free-run counter in the cycle of the second synchronization signal.

It is a block diagram which shows the structure of the genlock apparatus which concerns on the 1st Embodiment of this invention. It is explanatory drawing showing the clock number of the horizontal and vertical direction at the time of panel output in the genlock apparatus which concerns on embodiment of this invention. It is a block diagram which shows the structure of the genlock apparatus which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the genlock apparatus regarding a prior art.

Explanation of symbols

1 Video Signal Input Terminal 2 Sync Separation Circuit 3 Clock Generation Circuit 4 A / D Conversion Circuit 5 Panel Clock Generation Circuit 6 Free Run Counter 7 Register A
8 Register B
9 Arithmetic circuit 10 Control circuit B
11 Control circuit A
12 signal processing circuit 13 memory 14 D / A conversion circuit 15 video signal output terminal 16 clock generation circuit B
DESCRIPTION OF SYMBOLS 101 Video signal input terminal 102 Sync separation circuit 103 Clock generation circuit 104 A / D conversion circuit 105 1 / N frequency divider 106 Phase comparator 107 1 / M frequency divider 108 Voltage control oscillator 109 Control circuit 110 Signal processing circuit 111 Memory 112 D / A conversion circuit 113 Video signal output terminal

Claims (4)

An input video signal is A / D converted, the A / D converted digital data is converted into a video signal of a different signal format using a memory, and the converted digital data is D / A converted. A genlock device that outputs an output video signal,
Counting means for counting the clock from the clock generating means from the time of power-on,
Holding means A for holding the count value of the counting means at an interval of a synchronization signal synchronized with the input video signal;
Holding means B for holding the count value of the counting means at an interval of a synchronizing signal synchronized with the output video signal;
A calculation means for calculating the count difference by inputting the count values held by the holding means A and the holding means B;
Control means for generating a synchronization signal to be input to the holding means B based on the calculation result of the count difference by the calculating means,
The digital data is read out from an address corresponding to the line head of the memory in response to a synchronization signal generated by the control means and input to the holding means B.
The count values held by the holding means A and the holding means B are taken in at the edge of the latest sync signal and the values N (A) and N (B) taken at the latest sync signal edge. Values (N-1) (A) and (N-1) (B)
The calculating means is | N (A) − (N−1) (A) | which is the difference between the N (A) and the (N−1) (A) in the holding means A, and the holding means B. | N (B) − (N−1) (B) |, which is the difference between N (B) and (N−1) (B), is calculated as | N (A ) - (N-1) ( a) | - | N (B) - (N-1) (B) | genlock device, characterized in that the said calculation result. In claim 1,
The clock from the clock generation means is supplied to the counting means, and is further supplied as a clock for the D / A conversion and further as a clock for the control means. An input video signal is A / D converted, the A / D converted digital data is converted into a video signal of a different signal format using a memory, and the converted digital data is D / A converted. A genlock device that outputs an output video signal,
First clock generation means for generating a clock for the D / A conversion;
A second clock generation means that is separate from the first clock generation means and is capable of adjusting a clock frequency;
Counting means for counting the clock from the second clock generating means from the time of power-on;
Holding means A for holding the count value of the counting means at an interval of a synchronization signal synchronized with the input video signal;
Holding means B for holding the count value of the counting means at an interval of a synchronizing signal synchronized with the output video signal;
A calculation means for calculating the count difference by inputting the count values held by the holding means A and the holding means B;
Control means for generating a synchronization signal to be input to the holding means B based on the calculation result of the count difference by the calculating means,
The digital data is read out from an address corresponding to the line head of the memory in response to a synchronization signal generated by the control means and input to the holding means B.
The count values held by the holding means A and the holding means B are taken in at the edge of the latest sync signal and the values N (A) and N (B) taken at the latest sync signal edge. Values (N-1) (A) and (N-1) (B)
The calculating means is | N (A) − (N−1) (A) | which is the difference between the N (A) and the (N−1) (A) in the holding means A, and the holding means B. | N (B) − (N−1) (B) |, which is the difference between N (B) and (N−1) (B), is calculated as | N (A ) - (N-1) ( a) | - | N (B) - (N-1) (B) | genlock device, characterized in that the said calculation result. In claim 3,
A genlock apparatus for reducing the clock frequency of the second clock generation means when a predetermined time has elapsed after power-on.

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