JP2000244768A - Video signal processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent degradation of video quality after A/D conversion. SOLUTION: A sampling clock CLK synchronized with variable phase synchronizing signals CHSYNC is generated by using a PLL circuit 1, a clock 1/2CLK is generated by frequency dividing the sampling clock CLK by 2 and the clock 1/2CLK is latched by delay edge signals S2 for which the edge of the front side of video signals VIDEO is delayed for the 1/2 cycle of the sampling clock CLK. The latched judgment signals S3 are integrated, synchronizing signals HSYNC from the outside are sampled corresponding to the level of the integrated judgment signals S4 and the variable phase synchronizing signals CHSYNC are generated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing circuit, and more particularly to a video signal processing circuit which accepts a synchronizing signal of a video signal and automatically adjusts a phase of a sampling clock which is generated based on the synchronizing signal. To a circuit that adjusts to

[0002]

2. Description of the Related Art In the era of multimedia, digital signal processing is used in video signal processing, for example, when a television signal or an RGB video signal of a personal computer is taken into a projector and displayed on a large screen or printed out by a printer. Is being adopted. Since the television signal and the RGB video signal of a personal computer are usually analog signals, it is necessary to perform A / D conversion to convert the signals into digital video signals in order to perform digital signal processing. To do this,
A sampling clock synchronized with the video signal is required, and usually a phase locked loop (hereinafter referred to as P
Called LL. ) Circuit is provided to generate a sampling clock synchronized with the synchronization signal.

[0003] Television signals and RGB video signals of personal computers have different systems, and various screen modes can be selected in personal computers. Here, if the video signal processing circuit can cope with video signals of a plurality of systems, the versatility is increased correspondingly and the video signal processing circuit becomes a useful circuit. However, if this PLL circuit is used as it is, there is a problem that the generated sampling clock has only a fixed phase relationship uniquely with the input synchronization signal, but does not have an optimal phase relationship for sampling a video signal. Was.

This is caused by, for example, differences in the frequency and timing of the pixel clock of the video signal depending on the type of personal computer, and differences such as dullness of the video signal due to the length of the connection cable. If the video signal cannot be sampled by the above method, the video quality after A / D conversion will be greatly deteriorated. FIG. 5 shows this state.
(A) is a video signal, and (B) and (C) are sampling clocks. In the case of a sampling clock having a phase as shown in FIG. 5C, the video quality after A / D conversion is good, and in the case of a sampling clock having a phase as shown in FIG. 5B, the video quality is poor. In order to solve such a problem, multiple stages of delay circuits for delaying the sampling clock generated by the PLL circuit for a predetermined time (2 to 3 ns) are provided, and a group of delayed sampling clocks is generated. There has been proposed a method of adjusting the phase by selecting a sampling clock having an optimal phase for sampling a signal.

[0005] This conventional method will be described with reference to FIGS. 6 to 9. FIG. 6 is a block diagram of a conventional video signal processing circuit, and FIG.
9 is a flowchart for explaining an automatic phase adjusting operation of the sampling clock. In FIG. 6, reference numeral 1 denotes a PLL circuit which generates a clock CLK synchronized with the input synchronization signal SYNC. 2 denotes a delay which delays the clock CLK from the clock generation unit 1 by 2 to 3 ns per stage and shifts the phase. A multi-stage clock delay circuit 21 having a multi-stage connection and a plurality of sampling clocks SCLK _{0 to} SCLK _n obtained therefrom, and a selection signal SEL.
Clock phase shifting unit consisting of the selection circuit 22 for selecting one of the sampling clock SCLK _i, the 3 A / D converter for A / D conversion by the input video signal sampling SCLK _i, the video signal digitally converted 4 A frame memory unit 5 for storing frames is a CPU unit for generating the selection signal SEL, reading video data from the frame memory 4, and performing various operations.

FIG. 7A shows an input video signal,
(B) to (N) are sampling clocks SCLK _{0 to} SCLK _n whose phases are sequentially shifted, respectively. Sampling clock SCLK ₀ ~SCLK _n is obtained by dividing the one period of time even digital video signal data in a personal computer is generating the original input video signal into a plurality of phase sampling clock.

A method of adjusting the phase of the sampling clock of the video signal processing circuit will be described with reference to the flowcharts of FIGS. In the adjustment, the input video signal is not a flat video signal, but a video signal including a large variation in the luminance (or saturation) of the video signal for each scanning line, such as a character signal, is suitable. It is assumed that a video signal (not shown) of the pattern is used.

[0008] First the sampling clock SCLK ₀ is described as selected by the selection signal SEL from the CPU unit 5 (201 in FIG. 8). This is a convenience of explanation, actually it is possible to select any of the sampling clock SCLK _i first. Input video signal VIDE
O is the sampling clock SCLK ₀ and the A / D converter 3
Are A / D converted (202 in FIG. 8) and stored in the frame memory unit 4 (203 in FIG. 8). Next, any scanning line H
The video data for one scanning line is read out from the frame memory unit 4 (204 in FIG. 8), a location where the data difference between adjacent pixels in the one scanning line is maximized is found, and the address AD at that time is found. _K and AD _{K + 1} are determined (205 in FIG. 8).

Next, a sampling clock SCLK ₁ is selected from the CPU section 5 (206 and 207 in FIG. 9), and the input video signal VIDEO is converted to the sampling clock SCLK _1.
A / D conversion (208 in FIG. 9)
(209 in FIG. 9). Next, the frame memory unit 4
The video data at the addresses AD _K and AD _{K + 1} is read out from the memory (210 in FIG. 9), and the difference of the video data between the pixels is calculated and stored (211 in FIG. 9). This procedure was performed until the sampling clock SCLK _n (21 in FIG. 9
2, 213, 207 to 211), and the addresses AD _K , A in each stored sampling clock.
The maximum value of the difference of _{DK + 1} is calculated and determined (21 in FIG. 9).
4), the sampling clock at that time is selected and held as the sampling clock of the optimum phase (21 in FIG. 9).
5).

[0010]

However, in this phase adjusting method, the phase of the sampling clock is sequentially changed, and each time the image data is stored in the frame memory, a specific address of the stored image data is stored. Since the CPU reads out the video data and determines the optimal phase of the sampling clock, the circuit size becomes large and complicated logic is required. SUMMARY OF THE INVENTION In order to solve the above problems, the present invention has been made by paying attention to the fact that the central part of a pixel unit represents an optimum level, and automatically adjusts the phase of a sampling clock with a simple configuration. It is an object of the present invention to provide a video signal processing circuit capable of reliably realizing the above.

[0011]

A video signal processing circuit according to the present invention includes a phase locked loop circuit for generating a sampling clock having a frequency N times (N is an integer) the synchronous signal based on the synchronous signal. A video signal processing circuit for processing a video signal based on the sampling clock; an edge detector for detecting an edge of the video signal; and an edge signal from the edge detector being delayed by a half cycle of the sampling clock. And a D-type flip-flop unit for latching the clock from the divide-by-2 unit with a signal from the delay waveform shaping unit. An integration circuit for integrating the signal from the D-type flip-flop; and a signal from the integration circuit and the synchronization signal. A phase-variable unit that compares the bells and generates a synchronization signal having a changed phase when the levels match, and supplies the synchronization signal with the changed phase to the phase-locked loop circuit. Thus, the phase of the sampling clock for video signal processing is automatically adjusted.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings. FIG. 1 shows a video signal processing circuit according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a PLL circuit unit that generates a sampling clock CLK having a frequency N times (N is an integer) the frequency of a synchronization signal serving as a reference of a video signal based on an external synchronization signal (not shown). Each time the signal becomes valid, the phase is kept constant, the sampling clock CLK is divided by two, and the frequency dividing unit 3 that generates the clock 1/2 CLK detects the edge of the video signal VIDEO,
An edge detector 4 for generating the edge signal S1 delays the edge signal S1 by substantially a half cycle of the sampling clock CLK and shapes the waveform to generate a delayed edge signal S2 in which only a portion corresponding to the front edge is generated. The shaping unit 5 converts the clock 1/2 CLK into the delayed edge signal S2.
, And clock 1 / 2CL for each edge of the video signal.
A D-type flip-flop circuit section that generates a determination signal S3 for determining the level of K, an integration circuit section 6 that integrates the determination signal S3 to generate an integration determination signal S4, for example, a sampling clock such as a frame period 7, which has a time constant sufficiently longer than CLK, for example, is constituted by a high-speed comparator or the like, compares the level of the synchronization signal HSYNC with the level of the integration determination signal S4, and samples the synchronization signal HSYNC when they match, A variable phase synchronization signal CHSYNC is generated at the timing phase, and the synchronization signal H is generated.
This is a phase variable unit that varies the phase of SYNC. For example, when the external video signal is a VGA of a personal computer, the sampling clock has a frequency 800 times the frequency of the synchronization signal based on the number of display pixels.

Next, the operation of adjusting the phase of the sampling clock of the video signal processing circuit will be described. FIG. 2 is a timing chart for explaining the sampling clock phase adjustment operation. In FIG. 2, HSY
NC is a synchronizing signal synchronized with a video signal supplied from outside (not shown), CLK is a sampling clock generated by the PLL circuit unit 1, and 1 / 2CLK is a clock generated by the divide-by-2 unit 2, as described above. , This clock 1/2
CLK always has a fixed phase with respect to the synchronization signal HSYNC. VIDEO is a video signal supplied from the outside, S1 is an edge detection signal, S2 is a delayed edge signal, and S3 is a determination signal. FIG. 3 shows clock 1 of FIG.
FIG. 3 is a timing chart diagram showing an enlarged time axis of / 2CLK, a delayed edge signal S2, and a determination signal S3. Also,
FIG. 4 shows the synchronization signal HS according to the level of the integration determination signal S4.
FIG. 9 is a schematic diagram showing a YNC sampling level determined and at which level a variable phase synchronization signal CHSYNC is generated.

For convenience of explanation, the operation will be described assuming that the D-type flip-flop unit 5 is initialized and the determination signal S3 is set to "0". Since the determination signal S3 is "0", the integral determination signal S4 is also "0", and the phase variable section 7 changes the phase as soon as the synchronization signal HSYNC rises as shown by the first sampling level in FIG. The synchronization signal CHSYNC is output and input to the PLL circuit unit 1. The PLL circuit section 1 operates as described above, generates the sampling clock CLK, and generates the clock ＣＬＫ CLK based on the sampling clock CLK. At this time, the influence of the cable of the video signal VIDEO is at least the same as that of the synchronization signal HSYNC, so that the phase of the sampling clock CLK is advanced from the video signal VIDEO.

Therefore, the phase of the delayed edge signal S2 of the edge signal S1 generated based on the video signal VIDEO is shown in FIG.
As shown in (A), the determination signal S3 becomes "1". However, since the time constant of the integration circuit section 6 is large, the level of the integration determination signal S4 increases only slightly. For this reason, the second sampling level in FIG. 4 rises by the rise, so that the variable phase synchronizing signal CHS inputted to the PLL circuit 1 is correspondingly increased.
Since the phase of YNC is delayed, the sampling clock CL
The phase of K is delayed by that amount, and the phases of the video signal VIDEO and the sampling clock CLK are relatively close. This approaching state continues until the determination signal S3 becomes "0" (FIG. 3B, n-th sampling level in FIG. 4).

When the judgment signal S3 becomes "0", the integration judgment signal S4 starts to fall, and the phases of the video signal VIDEO and the sampling clock CLK are relatively separated from each other, but this time the judgment signal S3 has just been inverted. The determination signal S3 is inverted to "1" with a slight change, and the inversion of the determination signal S3 is repeated. This repetition of the inversion is made gentle by the integration circuit section 6 having a large time constant, and the level of the integration determination signal S4 is stabilized at an appropriate level.

By doing so, finally the video signal V
The central part of the video in the pixel unit in IDEO coincides with the rising edge of the sampling clock CLK. Naturally, the image of the pixel unit in the video signal VIDEO is most likely to have the most accurate level at the center,
By sampling at this timing, the best sampling can be performed. Here, the rising time of the synchronization signal HSYNC is made to depend on the characteristics of the signal system without any particular processing, but it is also effective to provide a circuit for adjusting the rising time to be appropriately delayed. Means.

In this embodiment, the phase variable section 7 is configured to use a high-speed comparator or the like to generate the variable phase synchronization signal CHSYNC when the level of the synchronization signal HSYNC matches the level of the integration determination signal S4. A / D separately
A conversion unit and a phase variation amount setting unit according to the A / D conversion result are provided, the A / D conversion of the integration determination signal S4 is performed, and the variable phase synchronization signal CHSYNC having a predetermined phase variation amount according to the value is provided. May be generated.

[0019]

According to the present invention, as described above,
A sampling clock synchronized with the variable phase synchronizing signal is generated by using a PLL circuit, the sampling clock is frequency-divided by 2 to generate a clock, and this clock is generated by dividing the leading edge of the video signal by a half cycle of the sampling clock. The variable phase synchronization signal is generated by latching with the delayed edge signal delayed by an amount, integrating the latched determination signal, and sampling an external synchronization signal according to the level of the integrated determination signal. Since the rising edge of the sampling clock coincides with the center of the video of the video signal in pixel units, the best sampling is possible, and the video signal processing that can reliably realize the automatic adjustment of the phase of the sampling clock is ensured. Circuit can be provided. Therefore, since the phase relationship between the video signal and the sampling clock is appropriate, the video quality after A / D conversion is good, and a clear display video can be realized.

[Brief description of the drawings]

FIG. 1 is a video signal processing circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart illustrating a sampling clock phase adjusting operation of the video signal processing circuit of FIG. 1;

FIG. 3 is a timing chart showing an enlarged time axis of a clock 1/2 CLK, a delayed edge signal S2, and a determination signal S3 in FIG. 2;

FIG. 4 is a schematic diagram showing a generation phase of a variable phase synchronization signal CHSYNC according to a level of an integration determination signal S4.

FIG. 5 is a diagram showing a state of sampling a video signal;
(A) is a video signal, and (B) and (C) are sampling clocks.

FIG. 6 is a block diagram of a conventional video signal processing circuit.

FIG. 7 is a timing chart of a main part of a conventional video signal processing circuit.

FIG. 8 is a first flowchart illustrating an automatic phase adjustment operation in a conventional video signal processing circuit.

FIG. 9 is a second flowchart illustrating an automatic phase adjustment operation in the conventional video signal processing circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 PLL circuit part 2 2 frequency division part 3 Edge detection part 4 Delay waveform shaping part 5 DF / F part 6 Integrating circuit part 7 Phase variable part

Claims (1)

[Claims] 1. A synchronizing signal which is based on N times (N
A phase locked loop circuit that generates a sampling clock having a frequency of (integer), a video signal processing circuit that processes a video signal based on the sampling clock, an edge detection unit that detects an edge of the video signal, A delay waveform shaping section for delaying the edge signal from the edge detecting section by a half cycle of the sampling clock and shaping the waveform; a divide-by-2 section for dividing the sampling clock by 2; A D-type flip-flop unit for latching a clock with a signal from the delay waveform shaping unit; an integration circuit unit for integrating a signal from the D-type flip-flop unit; a signal from the integration circuit unit and a level of the synchronization signal And a phase variable section that generates a synchronization signal having a changed phase when the levels match. A video signal processing circuit which automatically adjusts the phase of a sampling clock for video signal processing by supplying a synchronization signal having this phase changed to the phase locked loop circuit.