JPH10340074A - Image signal processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent degradation in image quality after an A/D conversion. SOLUTION: Delay circuits are connected in a multistage to delay input synchronous signals by a predetermined delay time (2 to 3 ns). The delayed synchronous signals are inputted to a multistage synchronous signal delay circuit 1 which outputs the delayed synchronous signals for every delay circuit. Then, one delayed synchronous signal is successively selected by a CPU 6 and a selecting circuit 2 and the selected signal is supplied to a PLL circuit 3. The circuit 3 generates a sampling clock having N times frequency (where N is an integer) of the frequency of the delayed synchronous signal that is the reference of the image signal processing based on the delayed synchronous signal. Then, the clock is used to covert the image signals to digital video signals by an A/D converting circuit 4 and the signals are stored in a storage circuit 5. Every time when the delayed synchronous signal is selected, the CPU 6 reads the digital video signal at the time of the previous delayed synchronous signal from the storage circuit 5, computes the difference between the digital video signal at the current delayed synchronous signal and the digital video signal at the previous delayed synchronous signal. When the difference becomes a minimum, the selected signal at that time is held as the optimum delayed synchronous signal and the reference sampling clock for the video signal processing is determined by the above-mentioned synchronous signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing circuit, and more particularly to a video signal processing circuit which accepts a synchronizing signal of a video signal and automatically adjusts a phase of a sampling clock which is generated based on the synchronizing signal. To a circuit that adjusts to

[0002]

2. Description of the Related Art In the era of multimedia, digital signal processing is used in video signal processing, for example, when a television signal or an RGB video signal of a personal computer is taken into a projector and displayed on a large screen or printed out by a printer. Is being adopted. Since the television signal and the RGB video signal of a personal computer are usually analog signals, it is necessary to perform A / D conversion to convert the signals into digital video signals in order to perform digital signal processing. To do this,
A sampling clock synchronized with the video signal is required. In a normal case, a phase locked loop (hereinafter referred to as P
Called LL. ) Circuit is provided to generate a sampling clock synchronized with the synchronization signal.

[0003] Television signals and RGB video signals of personal computers have different systems, and various screen modes can be selected in personal computers. Here, if the video signal processing circuit can cope with video signals of a plurality of systems, the versatility is increased correspondingly and the video signal processing circuit becomes a useful circuit. However, if this PLL circuit is used as it is, there is a problem that the generated sampling clock has only a fixed phase relationship uniquely with the input synchronization signal, but does not have an optimal phase relationship for sampling a video signal. Was.

This is caused by, for example, differences in the frequency and timing of the pixel clock of the video signal depending on the type of personal computer, and differences such as dullness of the video signal due to the length of the connection cable. If the video signal cannot be sampled by the above method, the video quality after A / D conversion will be greatly deteriorated. FIG. 2 shows this state.
(A) is a video signal, and (B) and (C) are sampling clocks. In the case of the sampling clock having the phase as shown in FIG. 2C, the video quality after A / D conversion is good, and in the case of the sampling clock having the phase as shown in FIG. 2B, the video quality is poor. In order to solve such a problem, multiple stages of delay circuits for delaying the sampling clock generated by the PLL circuit for a predetermined time (2 to 3 ns) are provided, and a group of delayed sampling clocks is generated. There has been proposed a method of adjusting the phase by selecting a sampling clock having an optimal phase for sampling a signal.

[0005]

However, this phase adjustment method can be adjusted relatively easily by using dedicated equipment used for adjustment of an oscilloscope or the like. However, for example, it is assumed that this adjustment method is applied to a projector. Considering that, most buyers do not have this kind of adjustment equipment, so when adjusting the phase, there is no other way than to display the image and make adjustments while checking the image. There is a problem that it is not only complicated but also difficult to substantially adjust. The present invention
An object of the present invention is to provide a video signal processing circuit for automatically adjusting the phase of a sampling clock.

[0006]

The present invention provides the following means for solving the above-mentioned problems.

The video signal processing circuit according to the present invention includes a phase locked loop circuit for generating a sampling clock having a frequency N times (N is an integer) the synchronizing signal based on the synchronizing signal. In a video signal processing circuit for processing a video signal based on a multi-stage synchronous signal delay circuit for connecting a delay circuit for delaying a synchronization signal by a preset time and outputting a delay synchronization signal for each delay circuit, A selection circuit that receives a plurality of delay synchronization signals from the multi-stage synchronization signal delay circuit and selects and outputs one delay synchronization signal according to the selection signal; and the sampling clock based on the delay synchronization signal selected from the selection circuit. Generating said phase locked loop circuit;
An A / D conversion circuit that samples a video signal with a sampling clock from the phase locked loop circuit and converts it into a digital video signal, and a storage circuit that stores the digital video signal from the A / D conversion circuit are separately provided. Each time a phase adjustment instruction signal is received from the provided phase adjustment indicator, an arbitrary one of the plurality of delay synchronization signals is selected, and a selection signal for sequentially selecting the next delay synchronization signal is generated. Each time the delay synchronization signal is supplied to the selection circuit, the digital video signal at the time of the previous delay synchronization signal is read out from the storage circuit each time the delay synchronization signal is selected, and the difference from the digital video signal at the time of the current delay synchronization signal is read. And a selection control circuit that holds the output of the selection signal at that time as the optimum delay synchronization signal when the difference is minimized. And it is characterized in that for automatically adjusting the sampling clock phase of the video signal processing.

In the video signal processing circuit of the present invention, the video signal processing circuit uses a video signal set to repeat a maximum value and a minimum value for each pixel of the video signal, and Each time an adjustment instruction is received, an arbitrary one of the delay synchronization signals is selected, a selection signal for sequentially selecting the next delay synchronization signal is generated and supplied to the selection circuit. Each time a signal is selected, the difference between adjacent video data of the digital video signal from the A / D conversion circuit is obtained, and the delay synchronization signal when this difference is the maximum is determined as the optimal delay synchronization signal. And a selection control circuit for holding a selection signal, wherein a phase of a sampling clock for video signal processing is automatically adjusted.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 shows a video signal processing circuit according to a first embodiment of the present invention. In FIG. 1, reference numeral 1 denotes an external synchronization signal (not shown) having a predetermined delay time (2 to 3n).
s), a multi-stage synchronous signal delay circuit for connecting a plurality of delay circuits for delaying by delay and outputting a delayed synchronous signal for each of the delay circuits;
A selection circuit 2 receives a plurality of delay synchronization signals from the multi-stage synchronization signal delay circuit 1 and selects and outputs one delay synchronization signal according to the selection signal. A selection circuit 3 is based on the delay synchronization signal selected from the selection circuit 2. The PLL circuit 4 generates a sampling clock having a frequency N times (N is an integer) the frequency of a synchronization signal serving as a reference of the video signal processing, and the sampling circuit 4 samples the external video signal (not shown) with the sampling clock from the PLL circuit 3. An A / D conversion circuit for converting to a digital video signal, a storage circuit for storing the digital video signal from the A / D conversion circuit 4, and a phase adjustment instruction signal from a separately provided phase adjustment indicator (not shown). The selection circuit selects any one of the delay synchronization signals each time the signal is received, generates the selection signal for sequentially selecting the next delay synchronization signal, and selects the selection circuit. Supply, and each time a delay synchronization signal is selected, the digital video signal at the time of the previous delay synchronization signal is read from the storage circuit, and the difference between the digital synchronization signal and the digital video signal in the current delay synchronization signal is calculated. Is the CPU which is a selection control circuit that holds the output of the selection signal at that time as the optimum delay synchronization signal when the delay synchronization signal becomes minimum. The PLL circuit 3 includes a phase comparator 3a, an L.P. P. F. (Low-pass filter)
3b, V.I. C. O. (Voltage controlled oscillator) 3c, frequency divider 3
d. For example, when the external video signal is a VGA of a personal computer, the sampling clock has a frequency 800 times the frequency of the synchronization signal based on the number of display pixels.

Next, the operation of adjusting the phase of the sampling clock of the video signal processing circuit will be described. When the synchronization signal SYNC is input to the multi-stage synchronizing signal delay circuit 1, 2～3Ns delayed delayed synchronizing signal SYNC ₀ ~SYNC _n-phase is obtained successively by the respective delay circuits are supplied to the selection circuit 2 You. Here, when the phase adjustment instruction signal is received, a selection signal SEL = i for initial phase adjustment predetermined by the CPU 6 is supplied to the selection circuit. In response to the selection signal SEL = i, 1 single delayed synchronization signal SYNC _i is selected. This delay synchronization signal SYN
C _i is supplied to the PLL circuit 3, a sampling clock CLK _i as a reference for the video signal processing is generated. The sampling clock CLK _i is supplied to the A / D converter 4 samples the analog video signal input from the outside, converted A / D, converted to a digital video signal DV _i. The digital video signal DV _i is stored in the image storage area of the memory circuit 5.

[0011] Next, CPU6 is adjacent to SYNC _i S
A selection signal SEL = i + 1 for selecting YNC _{i + 1} is supplied to the selection circuit.
_{i + 1} is provided, where CLK _{i + 1} is generated.

[0012] As described above, the analog video signal with the sampling clock CLK i + ₁ is sampled and converted into digital video signal DV i _{+ 1.} In this case, CPU 6 has a digital video signal when the digital video signal DV _i and the sampling clock CLK _{i + 1} in the case of the sampling clock CLK _i from the memory circuit 5 DV
The difference from _{i + 1} is obtained for each corresponding pixel, and the average value and the selection signal SEL = i + 1 are stored. Repeat this procedure, obtained for each pixel corresponding to the difference between the image data in each of the neighboring sampling clock when the sampling clock CLK ₀ to CLK _n corresponding to the synchronization signal SYNC ₀ ~SYNC _n all delay, an average value If the average value is smaller than the previous average value, the average value and the selection signal are both updated. Thus, the time when the average value of the difference data is minimum is obtained, and the selection signal at that time is determined as the optimal selection signal,
Next, the selection signal is held until a phase adjustment instruction is received.

(Second Embodiment) The second embodiment is an embodiment in which a video signal for phase adjustment is supplied to the video signal processing circuit of FIG. 1 to facilitate the phase adjustment. In this case, the CPU 6 in FIG. 1 is a selection control circuit, which selects any one of the delay synchronization signals each time the phase adjustment instruction signal is received, and sequentially selects the next delay synchronization signal. A signal is generated and supplied to the selection circuit, and each time a delay synchronization signal is selected, a difference between adjacent video data of digital video signals from the A / D conversion circuit is obtained. The delay synchronization signal at that time is used as the optimal delay synchronization signal, and the selection signal at that time is held. The video signal for phase adjustment will be described.

The video signal for phase adjustment is preferably a signal of a pattern in which the maximum value and the minimum value of the luminance are repeated every pixel clock, for example, a pattern of a pattern in which white and black are repeated. Is sufficient if the difference is equal to or more than half of the difference between the upper and lower reference voltages of the A / D converter. The pattern in which white and black are repeated for each pixel in this manner is clear when a pattern in which all pixels are black or a pattern in which all pixels are white is input as a video signal and a difference is obtained. This is because such a difference cannot be detected, and a substantial phase adjustment cannot be realized.

Using such a video signal for phase adjustment,
As described in the first embodiment, a delay synchronization signal is sequentially selected, a sampling clock is generated in accordance with the delay synchronization signal, a digital video signal is obtained, and at the same time, adjacent video data of each delay synchronization signal is obtained. The maximum value of the difference is obtained, a selection signal for selecting the delay synchronization signal having the maximum value is obtained, the selection signal at that time is determined as the optimum selection signal, and this selection signal is determined until the next phase adjustment instruction is received. Hold.

[0016]

According to the first aspect of the present invention, as described above, the synchronization signal is delayed by a predetermined delay time (2 to 2).
3 ns), a delay circuit for delaying by 3 ns) is connected in multiple stages, and input to a multi-stage synchronization signal delay circuit 1 for outputting a delay synchronization signal for each delay circuit. A sampling clock having a frequency N times (N is an integer) the frequency of the delay synchronization signal serving as a reference of the video signal processing is generated based on the delay synchronization signal, and the video signal is converted by the sampling clock. A / D conversion circuit 4 converts the signal into a digital video signal,
Each time the delay synchronization signal is selected, the CPU 6 reads the digital video signal at the time of the previous delay synchronization signal from the storage circuit, and determines the difference between the digital synchronization signal and the digital synchronization signal in the current delay synchronization signal. By calculating the delay synchronization signal when the difference is minimized as the optimal delay synchronization signal, and holding the selection signal at that time, the reference sampling clock for video signal processing is determined by the synchronization signal. Since the sampling clock phase adjustment is automated, the user is free from the hassle of adjusting the sampling clock phase while actually displaying the video according to the model and equipment to be used and checking the video after purchasing. .

According to the second aspect of the present invention, since the difference of the video signal due to the phase difference of the sampling clock is clear, the phase of the sampling clock can be easily adjusted in a shorter time.

[Brief description of the drawings]

FIG. 1 is a video signal processing circuit according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a quality state of a video signal by A / D conversion.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Multi-stage synchronous signal delay circuit 2 Selection circuit 3 PLL circuit 4 A / D conversion circuit 5 Storage circuit 6 CPU

Claims (2)

[Claims] 1. A phase-locked loop circuit for generating a sampling clock having a frequency N times (N is an integer) the synchronizing signal based on the synchronizing signal, and processing a video signal based on the sampling clock. In a video signal processing circuit, a multi-stage delay circuit for delaying a synchronization signal by a preset time is connected in multiple stages, and a multi-stage synchronization signal delay circuit for outputting a delay synchronization signal for each delay circuit; A selection circuit that receives a plurality of delay synchronization signals and selects and outputs one delay synchronization signal according to the selection signal; and the phase locked loop that generates a sampling clock based on the delay synchronization signal selected from the selection circuit. Circuit and the sampling clock from this phase locked loop circuit An A / D conversion circuit for converting into an image signal, a storage circuit for storing a digital video signal from the A / D conversion circuit, and each time a phase adjustment instruction signal is received from a separately provided phase adjustment indicator, Select any one of the delay synchronization signals, generate a selection signal for sequentially selecting the next delay synchronization signal, and supply the selection signal to the selection circuit. Reading the digital video signal at the time of the delay synchronization signal from the storage circuit,
Selection control that calculates the difference from the digital video signal at the time of the current delay synchronization signal, sets the delay synchronization signal when this difference is minimized as the optimal delay synchronization signal, and holds the output of the selection signal at that time And a circuit for automatically adjusting the phase of a sampling clock for video signal processing. 2. The video signal processing circuit according to claim 1, wherein a video signal set to repeat a maximum value and a minimum value of luminance for each pixel of the video signal is used as the video signal, and the phase adjustment instruction is issued. Each time the signal is received, any one of the delay synchronization signals is selected, a selection signal for sequentially selecting the next delay synchronization signal is generated and supplied to the selection circuit, and each delay synchronization signal is selected. Each time, the difference between the adjacent video data of the digital video signal from the A / D conversion circuit is obtained, and the delay synchronization signal when the difference becomes the maximum is determined as the optimal delay synchronization signal, and the selection signal at that time is determined. 2. The video signal processing circuit according to claim 1, further comprising: a selection control circuit for holding.