JPH11338406A - Sampling phase adjusting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a sampling device by which a picture signal is sampled with a phase of the most suitable sampling clock and the picture thereof can be displayed on a fixed resolution display, even if a distortion of an overshoot or an undershoot occurs in a high resolution picture signal supplied from a computer apparatus. SOLUTION: Inputted picture signals are sampled sequentially with clock signals of different phases, to thereby form picture element data, and each differential absolute value between former and latter picture elements is added accumulatively, and stored in a first register group 11. The accumulative added data stored in each register of the register group 11 are added together with the accumulative added data from former and latter registers, and stored in a second register group 13, and then the maximum value among the data stored in each register of the second register group 13 is selected. The phase of the sampling clock is controlled so that it will become the most suitable by the selection result.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal generated by a computer device when sampling and reproducing and displaying an image generated by the computer device on a display device using a fixed resolution display element such as a liquid crystal device or a plasma device. The present invention relates to a sampling phase adjusting device for reproducing the data in accordance with the resolution of the fixed resolution display element.

[0002]

2. Description of the Related Art In recent years, display devices and projection devices using fixed resolution elements such as liquid crystal devices and plasma devices have been commercialized as video reproduction and display devices.

A display device or a projection device (hereinafter, referred to as a liquid crystal or a plasma) using a fixed resolution element is used.
When displaying and displaying images created on a computer device, the image from the computer device is sampled in accordance with the resolution or the number of pixels of the fixed resolution element, and an image adapted to the number of pixels of the fixed resolution element is displayed. It must be output as a signal.

For example, the resolution of a fixed resolution element is 80
When the video signal from the computer device is output at a resolution corresponding to the SVGA, the output video signal needs to be sampled at 800 in the horizontal effective area. Also, it is necessary to reproduce the sampling clock without causing a phase shift.

FIG. 3 shows a circuit configuration of a sampling device when a video signal generated by a computer device is reproduced and displayed on a display.

In FIG. 3, a video signal created by a computer device is converted into an analog signal,
1 is supplied. The video signal (hereinafter, referred to as a PC video signal) supplied to the input terminal 31 is supplied to the detection circuit 32. The detection circuit 32 includes an analog / digital converter (hereinafter, referred to as an AD converter) 33, a one-pixel delay unit 34,
It comprises a subtractor 35, an absolute value unit 36 and an accumulator 37. The AD converter 33 samples the PC video signal input from the input terminal 31 using a clock signal described later and converts it into a digital signal. This sampling generates a plurality of pixel data. The sampled PC video signal is delayed by one pixel in a one-pixel delay unit 34, and the delayed PC video signal and the non-delayed PC video signal are supplied to a subtracter 35, and the video signal of one pixel before and after one pixel is compared. Subtraction processing is performed. The output of the subtractor 35 is supplied to an absolute value device 36, where the absolute value of the subtraction value is extracted. The absolute value extracted by the absolute value device 36 is cumulatively added for one screen or one horizontal period by an accumulator 37. . This accumulator 3
7 are stored in a plurality of registers 38a to 38a.
38n. A maximum value selection circuit 39 is connected to the outputs of the registers 38a to 38n.

On the other hand, a horizontal synchronizing signal is supplied to a terminal 41, and the horizontal synchronizing signal is supplied to a PLL via a delay circuit 42.
It is supplied to one reference of a circuit 43. This PL
The L circuit 43 generates a sampling clock signal based on the delayed horizontal synchronization signal, and supplies the sampling clock signal to the AD converter 33. Further, the sampling clock signal from the PLL circuit 43 is frequency-divided by the frequency divider 44 and supplied to the other reference of the PLL circuit 43 to control the phase of the sampling clock signal. A signal from a selector 45 is supplied to the delay circuit 42,
The selector 45 controls the amount of delay in the delay circuit 42 under the control of the control circuit 46, and the amount of delay is determined using the output of the maximum value selection circuit 39.

The PC video signal sampled by the AD converter 33 is supplied from an output terminal 47 to a display via various video signal processing circuits.

The operation of the sampling device having such a configuration will be described with reference to FIG. For example, assuming that a PC video signal in which white and black video are alternately continued for each pixel as shown in FIG.
The converter 33 can reliably sample white and black for each pixel when sampling is performed with a clock having a phase coincident with the position of the arrow (X) in FIG.

However, as shown in FIG. 4B, when the phase of the sampling clock signal is shifted and does not coincide with the above-mentioned optimum phase, a gray portion which is an intermediate color between white and black is sampled and displayed. When the image is painted in gray, or when the image is a character or the like, the vertical line is reproduced in a jitter state (flickering state) on the display screen, or the vertical line of 1 pixel width is reproduced and displayed in a 2 pixel width. As a result, an image with reduced definition is reproduced and displayed on the display screen.

For this reason, the sampling phase adjusting device of FIG. 3 makes it possible to control the phase of the sampling clock and find the optimum phase. That is, when the operation of the sampling device is started, the control circuit 46 controls the delay circuit 42 via the selector 45,
The delay amount is changed little by little, and a temporary delay amount is set. For example, a sampling clock signal having a phase t0 with a delay amount of 0 as an initial delay amount is generated. This delay circuit 42
Under the control of the control circuit 46, the delay amount can be switched to N stages, and the time corresponding to the reproduction clock cycle obtained from the horizontal synchronizing signal (or a longer time) is set at intervals of about 1 / N. The phase of the clock signal can be sequentially changed from t0 to tn as shown in FIG.

When the sampling device starts up, first, the delay amount is set to the initial value phase t0 of zero, and the PLL circuit 43 generates a clock signal of the initial phase. As a result, the A / D converter 33 is configured as shown in FIG.
The video signal is sampled at the timing indicated by t0. The sampled PC video signal is delayed by one pixel by a one-pixel delay unit 34. The delayed PC video signal and the non-delayed PC video signal are subtracted by a subtractor 35, and the absolute value of the difference is calculated as an absolute value. It is extracted by the vessel 36. The accumulator 37 accumulatively adds the absolute value of the difference from the absolute value device 36 for one screen or one horizontal scanning period, and stores the result in the register 38a.

Next, under the control of the control circuit 46, the delay amount of the delay circuit 42 is changed and temporarily set to the phase t1, and the result of the detection circuit 32 is similarly stored in the register 38b. As described above, the process of sequentially changing the delay amount of the delay circuit 42 from the control circuit 46 through the selector 45
And the Nth result is stored in the register 38n.
The accumulated addition value data stored in the registers 38a to 38n is read into the maximum value selection circuit 39, and the respective registers 38a to 38n.
The accumulated addition value data of a to 38n is compared. FIG. 4C shows a graph of the data stored in each of the registers 38a to 38n. In this figure, the horizontal axis is the delay circuit 4
2, the vertical axis is the accumulated data stored in the registers 38a to 38n. The maximum value selection circuit 39
The phase at which the accumulated data is maximized is determined based on the data in each register, and the delay amount corresponding to the phase is determined by the control circuit 46.
Inform Accordingly, the control circuit 46 determines that the phase at which the accumulated data becomes maximum is the optimum phase value of the sampling, and controls the selector 45 to determine the delay amount of the delay circuit 42.

That is, when the sampling device is started up, the delay amount of the delay circuit 42 is temporarily set to 0, and then the delay amount of the delay circuit 42 is sequentially displaced, so that the delay amount of the delay circuit 42 is equal to the video signal sampled for each delay amount. An absolute value of a difference from a video signal delayed by a pixel is detected, a delay amount at which the accumulated value is maximized is obtained, and a sampling clock signal having an optimal phase is obtained.

As described above, the sampling apparatus described above easily adjusts the phase of the sampling clock signal to the optimum phase when the PC video signal has a waveform without distortion as shown in FIG. Can be. However, an actual PC video signal is distorted due to line characteristics and circuit characteristics between the computer device and the display, and if the line and circuit characteristics are not properly adjusted, the distortion as shown in FIG. PC video signal having
1 may be supplied. FIG. 5A shows an example of a PC video signal to which a preshoot (S) is added.
Such video signals are sequentially sampled at the sampling clock phases t0 to tn shown in FIG. 5B, and when detected by the detection circuit 32, the data stored in the registers 38a to 38b becomes the data shown in FIG. As a result, the accumulated value becomes maximum at the phase where sampling is performed in the vicinity of the preshoot portion (S), and the phase of the sampling clock is different from the optimal phase.

As a result, sampling is performed at the timing indicated by t2 in FIG. 5B, and the relative phases of the PC video signal and the sampling clock signal in the detection circuit 32 do not match. Therefore, similarly to the above, for example, jitter occurs in characters reproduced and displayed on the display, and a problem that a vertical line of one pixel width is reproduced and displayed by two pixels occurs.

Particularly, in recent years, the output of video signals from computer equipment having a resolution of 1024 × 768 pixels or more has been increasing, and the frequency of the reproduced sampling clock signal is also very high, such as 60 to 100 MHz (one cycle of 10 to 15 ns). It has become. For this reason, due to temperature changes in computer equipment and various circuits constituting the sampling device, a slight shift in the relative phase between the PC video signal and the sampling clock signal cannot be ignored, and the quality of the reproduced display image deteriorates. Becomes

[0018]

SUMMARY OF THE INVENTION When sampling a video signal supplied from a computer device and reproducing and displaying the same on a display using a fixed resolution element, a phase of a sampling clock is sequentially shifted to find an optimum phase. However, there is a disadvantage that when the video signal is distorted, sampling is performed with the phase of the sampling clock deviated from the optimum value, and the quality of the reproduced video is degraded. In particular, when the sampling clock becomes faster due to the higher resolution of the computer device, the conventional sampling device cannot be adapted sufficiently, and there is a problem that the video reproduced and displayed on the display is deteriorated.

An object of the present invention is to provide a sampling phase adjusting device which can sample the video signal at an optimum sampling clock phase even when unnecessary distortion is added to the video signal.

[0020]

According to the present invention, there is provided a sampling means for sampling an input video signal with a predetermined clock signal to generate a plurality of pixel data, and processing the pixel data from the sampling means to generate a plurality of pixel data. Detecting means for extracting a difference of pixel data to be added, accumulating and adding the absolute value of the difference for a predetermined period, and generating a clock signal to be supplied to the sampling means, and sequentially varying the phase of the clock signal by a predetermined amount. Sampling clock generation means including a phase variable means for performing, and cumulative addition data by the detection means when the phase of the clock signal is sequentially displaced by the phase variable means, from a plurality of registers for storing each phase displacement. Reading the data stored in each register of the first register means. And adds the data stored in the register of the data and before and after stored in each register,
Calculating means for sequentially outputting as the calculation data, second register means comprising a plurality of registers for respectively storing the calculation data from the calculation means, and of the calculation data stored in each register of the second register means A maximum value selecting means for selecting a maximum value, and controlling the phase variable means in response to a selection result by the maximum value selecting means, and a clock signal output from the sampling clock generating means corresponding to the maximum value. And a control means for setting the output so as to output in the adjusted phase state.

The arithmetic means reads the data stored in each register of the first register means, and adds the data stored in the registers before and after the data stored in each register, Outputting the operation data, further supplying the pixel data sampled by the sampling means to a display means having a fixed resolution, and the phase control means comprises a period of at least one cycle of the clock signal. Is a sampling phase adjustment device in which the phase amount is sequentially varied at intervals equally divided into a plurality.

[0022]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing a circuit configuration of an embodiment of a sampling phase adjusting device according to the present invention. The same parts as those in FIG. 3 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In FIG. 1, the feature of the present invention resides in that a first register group 11 including registers 11a to 11n, an arithmetic circuit 12, and a second register group 13 including registers 13a to 13n are provided. is there.

The registers 11a to 11n have the same functions as the registers 38a to 38n in FIG.
2 stores the cumulative addition data when the phase of the sampling clock is sequentially changed.

The arithmetic circuit 12 includes registers 11a to 11a.
11n is added to the data stored in the registers before and after the data stored in the register 11n.
Registers 11n and 11b before and after the data of 1a
Of the register 11b, and outputs the result of the first operation.
1c is added and the result is output as a second operation result, and the third to Nth operation results are output in the same manner.

The registers 13a to 13n store the results of each operation from the operation circuit 12, and the registers 13a to 13n store the first to Nth operation data, respectively.

The other circuits operate in the same manner as in FIG. 3, and each operation result of the second
And the data of each of the registers 13a to 13n are compared, and the register exhibiting the maximum value is selected. That is, the maximum value selection circuit 39 determines which of the registers in the second register group 13 has the maximum value, and notifies the control circuit 46 of the selection result. Control circuit 46
Controls the selector circuit 45 based on the selection result, and determines the delay amount of the delay circuit 42 so that the delay amount of the sampling clock signal becomes an optimum value.

The PLL circuit 43 generates a sampling clock signal according to the determined delay amount, and supplies the sampling clock signal to the A / D converter 33.

The operation of the sampling phase adjusting device of the present invention will be described with reference to FIG. FIG. 2 shows the accumulated data accumulated in the first register group 11 when the phase of the sampling signal from the PLL circuit 43 is sequentially changed from t0 to t7 by controlling the delay circuit 42, and the second accumulated data. And operation data stored in the register group 13 of FIG. Note that the PC input to the input terminal 31
The video signal is an example in which a video signal including a preshoot (S) is input as shown in FIG.

As shown in FIG. 5A, a video signal is input to the input terminal 31, and the delay amount (phase) of the delay circuit 42 is changed at intervals (T) obtained by equally dividing one cycle of the sampling clock into eight. Assuming that the detection circuit 3 is sequentially displaced, the detection circuit 3 corresponds to the displacement from the delay amount (phase) t0 to t7.
2 outputs the cumulative addition data, and the values are stored in the eight registers 11a to 11n of the first register group 11, respectively. In FIG. 2A, the delay amount 0
At t0, the accumulated absolute value stored in the register 11a is 1, and when the delay amount is t1, the accumulated absolute value stored in the register 11b is 3, and thereafter, when the delay amount is sequentially shifted from t2 to t7. , 4, 4, 4,
The accumulated absolute value data of 3, 2, and 1 is stored.

Each register 1 of the first register group 11
Looking at the cumulative addition values stored in 1a to 11n, it can be seen that the cumulative addition value 5 stored in the register 11c at the time of the delay amount t2 is the maximum value. This is the preshoot (S)
The phase t2 of the sampling clock at this time is not the optimum sampling phase.

Next, the arithmetic circuit 12 adds the data of the preceding and succeeding registers 11n and 11b to the data of the register 11a of the first register group 11, and adds the added value 5 to the register of the second register group 13. 13a. Further, the data in the registers 11a and 11c before and after the data in the register 11b are added, and the added value 9 is stored in the register 13b. Hereinafter, the first register group 1
The data of the preceding and succeeding registers is added to the data of one register 11c to 11n and stored in the registers 13c to 13n of the second register group 13. As a result, the addition value 13 at the time of the delay amount t3 becomes the maximum, and the maximum value selection circuit 39 selects the data of the register 13c. Therefore, the control circuit 46 determines that the sampling clock phase at this time is the optimal sampling phase of the video signal, controls the selector 45, and sets the delay amount of the delay circuit 42 to t3.

A graph of the added values stored in the second register group 13 in this manner is as shown in FIG. 2 (b), and is substantially at the center (1) of one cycle of the clock frequency.
/ 2fclk) becomes the maximum value, and it can be seen that it almost matches the optimum clock phase t3 of the video signal. .

In the above-described embodiment of the present invention, an example has been described in which the delay amount is changed at intervals obtained by dividing the period of the sampling clock into eight equal parts. Phase displacement can be controlled. Further, the first register group 11 to be added by the arithmetic circuit 12
From the corresponding register,
Although the cumulative addition values of the three registers including the preceding and succeeding registers are added, the cumulative adding values of the five registers including the preceding and succeeding two registers can be added around the corresponding register. The optimum clock phase of the video signal can be set more finely by increasing the number of registers to be added by the arithmetic circuit 12 in accordance with the increase of the fraction of the sampling clock cycle.

[0035]

According to the present invention, the optimum phase can be set even when a video signal having distortion is input, and the optimum phase can be maintained without being affected by a change in the temperature of a circuit element. Thus, there is an effect that the optimum phase can be automatically and promptly set even with respect to a sampling clock whose speed is further increased.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a circuit configuration of an embodiment of a sampling phase adjusting device according to the present invention.

FIG. 2 is an explanatory diagram and a waveform diagram for explaining the operation of the embodiment of the present invention.

FIG. 3 is a block diagram showing a circuit configuration of a conventional sampling device.

FIG. 4 is a waveform chart for explaining the operation of a conventional sampling device.

FIG. 5 is a waveform chart for explaining a problem of a conventional sampling device.

[Explanation of symbols]

11 first register group, 12 arithmetic circuit, 13 second
, An input terminal, 32 a detection circuit, 33
... Analog-to-digital converter, 34 ... One pixel delay device,
35: subtractor, 36: absolute value device, 37: accumulator, 39 ...
Maximum value selection circuit, 41 ... terminal, 42 ... delay circuit, 43 ...
PLL circuit, 44 divider circuit, 45 selector, 46 ...
Control circuit, 47 output terminal.

Claims (4)

[Claims] 1. A sampling means for sampling an input video signal with a predetermined clock signal to generate a plurality of pixel data, and processing pixel data from the sampling means to extract a difference between preceding and succeeding pixel data. A sampling means for accumulating and adding the absolute value of the difference for a predetermined period and outputting the clock signal; and a sampling clock including a phase variable means for generating a clock signal to be supplied to the sampling means and for sequentially changing the phase of the clock signal by a predetermined amount. Generating means; first register means comprising a plurality of registers for storing cumulative addition data by the detecting means when the phase of the clock signal is sequentially shifted by the phase changing means, for each phase shift; The data stored in each register of the first register means is read and stored in each register. Calculating means for adding the obtained data and the data stored in the registers before and after the calculated data and sequentially outputting the calculated data as calculation data; a second register means including a plurality of registers for respectively storing the calculation data from the calculation means; A maximum value selecting means for selecting a maximum value among operation data stored in each register of the second register means; and controlling the phase variable means in response to a selection result by the maximum value selecting means, Control means for setting a clock signal output from the sampling clock generation means to be output in a phase state corresponding to the maximum value. 2. The arithmetic means reads data stored in each register of the first register means, and adds data stored in registers before and after to data stored in each register. 2. The sampling phase adjusting device according to claim 1, wherein the calculating data is output. 3. The sampling phase adjusting device according to claim 1, wherein the pixel data sampled by said sampling means is supplied to a display means having a fixed resolution. 4. The phase control means according to claim 1, wherein said phase control means sequentially varies the phase amount at intervals obtained by equally dividing at least one period of said clock signal into a plurality of periods.
The sampling phase adjustment device according to any one of the preceding claims.