JP3018384B2 - Video signal processing circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing circuit for converting the number of scanning lines, and more particularly to a circuit for converting a digitized video signal into a number of scanning lines.

[Conventional technology]

At present, there are 525 horizontal scanning periods (hereinafter abbreviated as 1H) in one vertical scanning period (hereinafter abbreviated as 1 frame) in the NTSC system and PAL, S in which one frame consists of 625H.
There is an ECAM method (hereinafter, abbreviated as a PAL method as a representative). In a conventional matrix type display device, for example, considering a display device using a liquid crystal, as a method capable of displaying both the NTSC and the PAL method, two consecutive scanning lines are displayed on one line for 1H to 2H period. As a result, the overlap driving method that makes the display periods of both methods the same, and the thinning method of thinning one out of several lines by driving the scanning side of the matrix type display body are shown in FIG. As described above, there is a scanning line conversion method using an interpolation filter that exchanges the number of scanning lines by interpolating with an interpolation filter such as a digital filter.

[Problems to be solved by the invention]

However, the conventional technique has the following problems. In the case of the overlap driving method, there is a drawback that the resolution in the vertical direction for writing while overlapping several lines is reduced, it is applicable only in the simple matrix method, and in the case of the thinning method,
The resolution in the vertical (including diagonal) direction is reduced, although not as much as the overlap driving.

Further, in the scanning line conversion method using the interpolation filter, these degradations do not theoretically occur, but as can be seen from FIG. 5, since the scale of the hardware is increased, the circuit scale is increased and the cost is reduced. Rise is a problem.

An object of the present invention is to solve the above-described problems, and an object of the present invention is to achieve both NTSC and PAL display in a matrix type display device with a simple circuit configuration. Another object of the present invention is to provide a video signal processing circuit that performs high-quality scanning line conversion.

[Means for solving the problem]

In order to solve the above problem, the video signal processing circuit according to the present invention uses the n scanning lines as a set, and sets the i-th scanning line and the (i + 1) -th of the n scanning lines (i is 1 or more, n-
A correlation judging circuit for judging the degree of correlation with a scanning line of an integer of 1 or less) and a thinning circuit for thinning out the scanning line having the highest degree of correlation from n scanning lines based on the judgment result of the correlation judging circuit. Features. Further, a j-th (j is an integer of 2 or more and n or less) scanning line is thinned out. Alternatively (or further), it is characterized by having n delay circuits with a delay time of one horizontal scanning period.

(Operation)

By configuring the video signal processing circuit as described above, a position having the strongest correlation in the vertical direction of the screen within a certain range (within a certain number of scanning lines), in other words, a scanning line pair can be found. By storing this position (actually what scanning line it is) and thinning out the scanning line at the position stored by the thinning circuit, the correlation in the vertical direction of the screen within a certain range is obtained. Scan lines can be thinned.
As a result, even if a portion having a strong vertical correlation is thinned out, the image quality is little degraded. Therefore, a television broadcasting system in which one vertical scanning period is composed of different numbers of horizontal scanning lines is displayed on a matrix type display. Also, image degradation is small, and the same display rate can be achieved with the same display.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram for realizing a video signal processing circuit according to the present invention. In this embodiment, the input signal is a luminance signal in terms of simplification of the correlation detection circuit and effective use of the 1H delay circuit. However, the present invention can be applied to a composite video signal, for example. A shift register capable of delaying may be used, and naturally a 1H line memory may be used. Hereinafter, all 1H delay circuits may be considered as having the same configuration. The subtractor (102) calculates a difference between the current luminance signal and the luminance signal 1H before. The correlation judging circuit (103) judges the correlation between the scanning lines from the difference signal obtained by the subtracter (102), and its detailed configuration will be described later. The switch control circuit (104) controls the changeover switch (109) based on the output result of the correlation determination circuit (103). The changeover switch (109) selects the 1H delay circuit 4 (107), that is, the 4H delay signal (111). The 1H delay circuit 5 (108), that is, 5H
B to select the delay signal (112), C to select neither
3 switch. This may be a two-contact switch that selects any of ab if there is no problem even in the time axis conversion of the thinning signal.

Next, the operation of this embodiment will be described based on the timing chart of FIG. PAL → NTSC as an example of thinning out scanning lines
Consider a broadcasting system. Since PAL has 312.5 lines in one field and NTSC has 262.5 lines in one field, this conversion can be realized by thinning out one line into five lines (that is, 5 lines → 4 lines).

In FIG. 2, the numbers indicate the order of the scanning lines, for example, "1" indicates the first scanning line. When the scan lines are considered as a set of five scan lines, they are referred to as first to fifth scan lines.

The scanning lines to be thinned are determined based on the correlation between the scanning lines. For example, if the correlation between the first scanning line and the second scanning line is the largest, the second scanning line is thinned. That is, the thinning target is the second to fifth scanning lines in the set of five scanning lines. Now consider the thinning of the second scanning line. Since the correlation between the five scanning lines is examined, the result is known at a position where the luminance signal is delayed by 5H from the present. At a position delayed by 5H from the first scanning line, a signal of "2" is output from the correlation determination circuit (103).
The switch control circuit (104) controls so as to always select b, that is, a signal delayed by 5H during the first scanning line of the five scanning lines. Next, control is performed based on the output signal of the correlation determination circuit (103). Since the main power of the correlation judgment circuit (103) is now "2", the changeover switch (109) is switched to a, that is, a signal delayed by 4H at the second scanning line position so as to thin out the second scanning line. With this operation, the thinning signal is
A signal delayed by 5H appears on the first scanning line as it is, and a 4H delayed signal is selected from the next scanning line, so that the signal is skipped for 1H, and the second scanning line of the original luminance signal is skipped. At the fifth scanning line position, a thinning signal as shown in FIG. 2 can be obtained by setting the changeover switch to a state C in which none of the signals is selected. By switching the 4H delay signal and the 5H delay signal to the switches in this manner, thinning can be performed at an arbitrary position, so that the scanning line having the largest correlation can be thinned. In addition, the number of 1H delay circuits is determined by the number of sets at the time of thinning out. For example, one thinning out of eight scanning lines can be realized by having eight 1H delay circuits in the same configuration as in this embodiment.

Next, the correlation judgment circuit (103) will be described in detail. Second
The figure shows a block diagram for realizing the correlation determination. The absolute value conversion circuit (201) takes the absolute value of the difference signal. The adder (202) adds the signal of the absolute value conversion circuit (201) and its own output, and is reset by the input of the latch signal. This results in a cumulative addition of the latch signal period. Since the latch signal has a 1H period, it is a cumulative value of the absolute value of the difference during the 1H period. The output of the adder (202) is 1H
Each time, the value is taken into the latch circuit (203), and this value becomes a correlation value of 1H. That is, it can be said that the larger this value is, the smaller the correlation between the scanning lines is. The memory (204) stores the output data of the latch circuit (203) only when the read signal (207) is input, and resets the data when the reset signal is input to make the data the maximum value. The comparator (205) compares the output of the memory (204) with the output of the latch circuit (203), and outputs only when the output of the latch circuit (203) is smaller than the output of the memory (204). The counter (206) counts the number of changes in the output of the comparator (205). The operation of performing the correlation judgment by the configuration of FIG. 3 will be described with reference to the time chart of FIG. The difference signal of the scanning line is cumulatively added by the adder (202). This addition result is latched by a 1H cycle latch signal, and then the adder (20
2) Reset. The memory (204) is first set to the largest value by the reset signal. For example, if it is 4 bits, the data is set to "1111". Next, the latch circuit outputs the cumulative addition result, and this output is compared with the output of the memory by the comparator (205). Since the memory data is maximum, the output of the latch circuit is always smaller than the value, and the output appears in the comparator (205). Comparator (20
Since the output of (5) is a read signal (207) of the memory (204), the memory (204) stores the output value of the latch circuit (203). The output of the comparator (205) is
Further, it is counted by the counter (206). Note that the output is dropped halfway so that it can be counted by the counter (206). By repeating the same operation, for example, if an output smaller than the output of the previous latch circuit (203) is latched, the comparator (205) outputs and is counted by the counter (206), and the contents of the memory (204) Is updated, and if a large output is latched, the counter (206) and the memory (204) do not operate because the comparator (205) does not output. Therefore, if the switch control circuit (104) decides to thin out the second scanning line when the counter output is 0, the third scanning line when the output is 1, and the counter output + the second scanning line, the correlation is the largest. Scan lines can be determined.

〔The invention's effect〕

As described above, according to the present invention, by thinning out the scanning line having the largest correlation between the vertical scanning lines, the portion having a large correlation does not have much information amount in the vertical direction. Image quality degradation can be reduced. Further, since it can be realized with a simple circuit configuration, compatibility of different numbers of scanning line systems can be realized with a small circuit scale and at low cost in a matrix type display.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a video signal processing circuit according to the present invention. FIG. 2 is a time chart of the video signal processing circuit of FIG. FIG. 3 is a configuration diagram for realizing the correlation judging circuit in FIG. FIG. 4 is a time chart of FIG. FIG. 5 is a configuration diagram for performing scanning line conversion using a digital filter. 101 1H delay circuit 1 102 Subtractor 103 Correlation judgment circuit 104 Switch control circuit 105 1H delay circuit 2 106 1H delay circuit 3 107 1H delay circuit 4 108 1H delay Circuit 5 109 Changeover switch

Claims (2)

(57) [Claims] 1. A video signal processing circuit for converting the number of scanning lines, wherein n scanning lines are taken as a set, and an i-th scanning line and an i + 1-th (i is 1 or more, n A correlation judging circuit for judging the degree of correlation with a scanning line of (-1 or less), and a thinning circuit for thinning out the scanning line with the highest degree of correlation from the n scanning lines based on the judgment result of the correlation judging circuit. A video signal processing circuit comprising: 2. The video signal processing circuit according to claim 1, wherein the thinning circuit has n delay circuits each having a delay time of one horizontal scanning period for sequentially delaying the signals of the n scanning lines. Then, based on the determination result of the correlation determination circuit, among the scan line signals sequentially delayed by the n delay circuits, select a scan line signal excluding the scan line having the highest degree of correlation. A video signal processing circuit for outputting as a thinning signal.