JPH0865639A - Image processor - Google Patents

Abstract

PURPOSE: To convert an optional video signal into a desired video signal by providing an interlacing/noninterlacing converting circuit with a function which can process frame frequency conversion at the same time. CONSTITUTION: The interlacing/noninterlacing converting circuit N consists of a field thinning-out decision circuit 14 which decides a field thinning-out mode from an input-side vertical synchronizing signal (1) and an output-side vertical synchronizing signal (4) and performs a thinning-out process in frame units at all times, a writing control circuit 16 which writes a video signal on the basis of a writing acknowledgement signal outputted from the decision circuit 14, and a reading control circuit 17 which actualizes interlacing/ noninterlacing conversion on the basis of signals from a motion adapting circuit 20 and the writing control circuit 16.

Description

Detailed Description of the Invention

[0001]

The present invention relates to an HDTV (High Difini)
The present invention relates to an image processing circuit capable of interlaced / non-interlaced conversion for converting an interlaced signal such as an option television into a non-interlaced signal. Further, the present invention relates to an image processing circuit which converts a non-interlaced input video signal into a frame frequency and outputs the non-interlaced signal.

[0002]

2. Description of the Related Art In recent years, image display devices have been used for HDTV and EW.
Various signal sources such as S (Engneering Work Station) are used, and high definition images are being developed. In order to cope with such a situation, there have been proposed techniques such as a scanning line conversion technique, a technique for synthesizing a screen of a plurality of signals, a technique for improving image quality during enlarged display, and sharing of various signal sources. For example, in the interlaced / non-interlaced conversion, the odd field and the even field of the interlaced signal are captured in different field memories, and the captured data is read alternately for each horizontal synchronizing signal, or the scanning line is scanned. The basic idea is to perform read scanning line interpolation at double speed, but since high-quality display cannot be performed as it is, in the field between horizontal scanning lines disclosed in JP-A-3-57389. Interpolation techniques and techniques such as motion adaptive processing disclosed in Japanese Patent Laid-Open No. 1-60082 have been proposed to improve image quality during interlaced / non-interlaced conversion. Further, in terms of sharing a variety of signal sources, Japanese Patent Laid-Open No.
No. 235592, MUSE (Multiple Su
b ー nyquist Sampling Encoding) -NTSC (National T
Frequency conversion technology such as elevision sysytems commit (EE) conversion has been proposed and used for multi-screen output and image display device with single scanning speed.

When performing interlace / non-interlace conversion and frame frequency conversion, the interlace / non-interlace conversion circuit 5 first converts the interlaced signal into a non-interlaced signal as shown in FIG. 17 (a). A method of converting the frame frequency by the frequency converter 6 (Japanese Patent Laid-Open No. 2-281884). As shown in FIG. 17B, first, the frame frequency is converted by the frequency converter 6 and then the interlaced / non-interlaced conversion is performed. A method for converting into a non-interlaced signal in the circuit 5 (Japanese Patent Laid-Open No. 3-53688)
(Japanese Patent Laid-Open Publication No. 2003-242242), there is a method of performing field frequency conversion and non-interlace conversion by performing non-interlace conversion by inter-field interpolation at the time of reading the memory.

[0004]

When performing interlace / non-interlace conversion and frame frequency conversion, in the above-mentioned prior art, interlace / non-interlace conversion and frame frequency conversion are respectively performed by different devices. Alternatively, interlaced signals are interpolated in the field to perform interlaced / non-interlaced conversion and frame frequency conversion. However, the former requires a large circuit scale and uses a large amount of memory because the two signal processes are performed individually. The latter requires intra-field interpolation even in the case of a still image, and therefore interlace between fields. / The image quality was worse than non-interlaced conversion. The present invention
It is an invention to solve such a problem, and realizes interlace / non-interlace conversion by inter-field interpolation and frame frequency conversion at the same time, thereby reducing the scale of the memory and circuit and improving the image quality of the screen. With the goal.

[0005]

In an interlaced / non-interlaced conversion device having two systems of field memories for odd fields and even fields, field thinning or field thinning for determining field thinning or field duplicate reading is performed. A function to constantly thin out the input video signal on a frame-by-frame basis so as to thin out two consecutive fields when inputting an interlace signal and thinning out one field when inputting a non-interlaced signal. Field thinning circuit, a memory writing control circuit for writing image data based on the output of the thinning circuit, and the memory is alternately switched in the horizontal synchronizing frequency unit when reading the data of the memory to read the image data, and the interlaced signal To convert non-interlaced signals Configuring the memory read control circuit having.

[0006]

By using the field thinning circuit as a circuit for performing either one-field thinning or two-field thinning on the input signal, a frame can be generated for both interlaced signals and non-interlaced signals. Thinning can be performed in units, and frame frequency conversion can be performed for both input of interlaced signals and non-interlaced signals. Also, by performing frame thinning during memory writing and interlace / non-interlace conversion during memory reading, interlace / non-interlace conversion and frame frequency conversion can be performed simultaneously, and conversion processing is performed separately. It is possible to reduce the memory capacity and the circuit scale as compared with the conventional image processing apparatus.

[0007]

Embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a circuit configuration diagram of a first embodiment of an image processing apparatus according to the present invention. The image processing circuit of this embodiment includes a sync separation circuit 11 for extracting a horizontal sync signal (1) and a vertical sync signal (2) from an input video signal S1, and a pixel clock (3) for the horizontal sync signal (2) of the input signal. To play P
LL circuit 12, A / D conversion circuit 13 for converting an analog signal to a digital signal, and whether to thin out from the relationship between the phase and frequency of the input side vertical synchronizing signal (1) and the output side vertical synchronizing signal (4). Determine whether or not, thinning control signal (7)
A field thinning circuit 14 for generating a video signal, a memory group 15 in which a field memory for capturing a video signal is divided into two systems for an odd field and an even field, and a write control circuit for controlling writing of image data to the memory. 16, a read control circuit 17 for controlling reading of the pixel data written in the memory, and a PLL (Phased Locked Loop) circuit 18 for reproducing the pixel clock (6) from the horizontal synchronizing signal (5) on the output side. , D to convert digital signal to analog signal
The A / A conversion circuit 19, a moving image discriminating circuit for discriminating a moving image of an input signal, and a motion adaptive processing circuit 20 including a circuit for controlling reading of a memory based on the discrimination result. Here, the image processing apparatus includes the video signal S1, the vertical synchronizing signal (4) and the horizontal synchronizing signal (5) of the output side display.
Becomes the input signal.

The field thinning circuit 14 outputs a signal for thinning out continuous image data of two fields when the input signal is interlaced / non-interlaced when the field thinning is performed, and the input signal is input. It is a means for outputting a signal that thins out one field when the signal is a non-interlaced signal or when the interlaced / non-interlaced conversion is not performed with the interlaced signal. As shown in FIG. 2, the field thinning circuit 14 determines whether to thin a field based on the relationship between the frequency and the phase of the input side vertical synchronizing signal (1) and the output side vertical synchronizing signal (4). A circuit 141, a D flip-flop 142 that functions as a mask signal generation unit that regulates the generation of a write enable signal, and a latch 143 that functions as a phase adjustment unit,
144, a logical product 145, and a selector 146 that switches the write enable signal. An example of the field thinning decision circuit 141 is shown in FIG. The DFF1 is a D flip-flop that detects the output side vertical synchronizing signal. The D flip-flop DFF2 and the D flip-flop DFF3 generate the write enable signal, and the D flip-flop DFF4 and the D flip-flop DFF5 generate the thinning signal. To do.

Next, the operation of the field thinning circuit 14 will be described. The input side vertical synchronization signal (1) and the output side vertical synchronization signal (4) shown in FIG. 4 are input to the thinning-out determination circuit 141, and the thinning-out determination is performed based on the relationship between the phase and frequency of the synchronization signal. Pull signal (201) and write enable signal (7-
1) is output. The input side vertical synchronizing signal (1) is a D flip-flop (DFF) which functions as a mask signal generating means.
It is also input to 142 and a latch 143 which acts as a delay means. The D flip-flop 142 generates and outputs a mask signal (202) from the input side vertical synchronizing signal (1) and an inverted signal of the thinning signal (201) input to the clear terminal.
A logical product circuit 144 obtains a logical product of (202 ′) and (1 ′), which are the mask signal (202) and the input side vertical synchronizing signal (1) latched by the dot clock, and controls the field thinning. The write enable signal (thinning control signal) (7-2) is output.

If the output side vertical synchronizing signal (4) is present during one cycle of the input side vertical synchronizing signal (1), the field thinning decision circuit 141 permits the writing of the image data of the field, The pull signal (201) is not output. Therefore, the inversion signal "1" is applied to the clear terminal of the DFF142.
Is input and the mask signal (202) from the inverting output terminal
Holds "0". On the other hand, input side vertical sync signal (1)
If the output side vertical synchronizing signal (4) does not exist during one cycle period of, the inversion signal “0” of the thinning signal (201) from the field thinning circuit 14 is the clear terminal (C) of the DFF.
LR), the DFF 142 is cleared, and DF
The mask signal (202) which is the inverted output of F142 is "
1 ". Next, when the inverted signal of the vertical synchronizing signal (1) is input to the DFF 142, the mask signal (2
02) changes from "1" to "0".

As described above, when the input video signal is not interlaced / non-interlaced converted, only the fields determined to be thinned are thinned out, and when the input video signal is interlaced / non-interlaced converted, the fields determined to be thinned out. And the next field are thinned out, and one frame is always thinned out. In FIG. 4, the field write enable signal (7-1) is when the input signal is an interlaced signal, and the field write enable signal (7-2) is when the input signal is a non-interlaced signal. . Next, for the field thinning permission signal (7), the selector 146 selects one of the field write permission signal (7-1) and the field write permission signal (7-2) to perform interlaced / non-interlaced conversion. If not, the field write enable signal (7-1) is output, and if so, the field write enable signal (7-2) is output.

As shown in FIG. 5, the memory 15 includes odd field memories 150 and 151, even field memories 152 and 153, and a field selection switch 15.
4, 159 and the field memory selection switch 155,
It is composed of 156, 157 and 158.

Next, the operation of FIG. 1 will be described. The sync separation circuit 11 extracts the vertical sync signal (1) and the horizontal sync signal (2) from the input video signal S1, the vertical sync signal (1) to the field thinning circuit 14, and the horizontal sync signal (2) to the PLL. Output to the circuit 12. PLL circuit 1
In 2, the pixel clock (3) is reproduced based on the horizontal synchronizing signal (2), and the A / D converter 13 and the write control circuit 1 are reproduced.
Output to 06. The A / D converter 13 uses the pixel clock (3) as a sampling clock, converts the input video signal S1 into a digital signal, and outputs the digital signal to the memory 15 and the motion adaptive processing circuit 20. Field thinning circuit 14
Then, the field write enable signal (7) is generated from the relationship between the frequency and the phase of the input side vertical synchronizing signal (1) and the output vertical synchronizing signal (4) and is output to the write control circuit 16.
The write control circuit 16 sequentially writes the image data of each field of the video signal S1 into one of the field memories of the memory 15 based on the pixel clock (3) and the field write enable signal.

The writing of the image data to the memory 15 is 2
Image data of field signals that are permitted to be written are alternately written into each of the memories prepared for the system. Also, when performing field frequency conversion, in order to avoid overtaking write addresses and read addresses in the memory, image data of fields in which overtaking occurs is thinned out. As described above, the field thinning is performed by thinning out two fields when performing interlace / non-interlace conversion and thinning out one field when not performing interlace / non-interlace conversion. Here, when performing interlace / non-interlace conversion, two fields are continuously thinned out because the image data of the odd field is always stored in the field memory for the odd field and the image data of the even field is stored in the field memory for the even field. This is so that the image data can be written. Therefore, as described below,
It is possible to avoid errors that result in in-field interpolation.

FIG. 6 shows the relationship between an input field signal when converting an interlaced signal into a non-interlaced signal, image data written in each field, an output field signal and a non-interlaced read signal.
The figure shows the state when only one field is thinned out.

In the input field number (0), since the vertical sync signal of the output field number (0) is generated between the generation of the input side vertical sync signal and the generation of the next vertical sync signal, the writing is permitted. A signal is output and the image data (401) of the input field number (1) is written in the odd field memory. Next, since the vertical synchronizing signal of the output field number (1) is output during the period of the input field number (1), the image data (402) of the input field number (2) is written in the even field memory. Next, since the output side vertical synchronizing signal is not output during the period of the input field number (2), the thinning signal is output and the image data of the input field number (3) is not written. Then, since the vertical synchronizing signal of the output field number (2) is output during the period of the input field number (3), the image data (403) of the input field number (4) (even field) is stored in the odd field memory. Written. Further, since the vertical synchronization signal of the output field number (3) is output during the period of the input field number (4), the image data (404) of the input field number (5) (odd field) is written in the even field memory. Be done.

The image data written in this memory is read as follows. In the output field number (1), the image data of the input field number (0) written in the even field memory and the image data of the input field number (1) written in the odd field memory (4
05) is read. For this image data, inter-field interpolation is executed using image data of even fields and odd fields. Similarly, in the output field number (2), the image data of the input field number (1) written in the odd field memory and the image data of the input field number (2) written in the even field memory (406). ) Is read. Also for this image data, inter-field interpolation is executed using the image data of the odd field and the even field. Next, in the output field number (3), the image data of the input field number (2) (even field) written in the even field memory and the input field number (4) (written in the odd field memory) Image data of an even field (4
07) is read. This image data uses image data of even fields and even fields, and inter-field interpolation is performed, which causes an error.

The structure of the memory 15 will be described with reference to FIG. The memory 15 has an odd-field memory and an even-field memory, and the odd-field memory and the even-field memory each have a memory capacity of at least two fields for performing frequency conversion. For example, each field memory is arranged as shown in FIG. The memory 15 includes field memories 150 to 153 each capable of capturing at least one field,
A field selection switch 154 for switching between an odd field and an even field, and field memory selection switches 155, 15 for selecting a field memory to be written.
6, field selection switches 157 and 158 for selecting a field memory to be read, and a field selection switch 159 which is switched for each horizontal synchronizing signal described above or which is controlled by a moving image discrimination signal from the motion adaptive processing circuit 20. Composed of.

The operation control of these switches will be described. For example, when the video signal of the first field is input, the switch 154 and the switch 155 respectively select the contact a and write it in the first odd field memory 150. For the video signal of the second field, switch 1
54 selects the contact b, and the switch 156 selects the contact a and writes it in the first even field memory 152. Similarly, the video signal of the third field selects the second odd field memory 151, and the video signal of the next fourth field selects and writes the second field memory 153. In this way, the video signal of each field is sequentially circulated in the field memory, selected, and written. The selection of each switch is performed by the write control circuit 16.

Further, in reading of each field memory, a switch 157 for selecting one of the odd field memories.
Switch 1 for selecting one of the even and even field memories
59 is performed by selecting the field memory in which the writing of the video signal is not executed at the time of reading, and in the case of a still image, the switch 159 controls the read control circuit 17 shown in FIG. Depending on the signal, the odd-numbered field memory and the even-numbered field memory are alternately switched and read for each horizontal synchronizing signal, and non-interlaced conversion is performed.

In reading the memory, when the PLL circuit 18 generates the pixel clock (7) from the input side horizontal synchronizing signal (5) and the input signal source is a still image interlaced signal,
Non-interlaced conversion is enabled by reading out every horizontal synchronization signal (5), that is, alternately in units of horizontal lines.
On the other hand, in the case of the moving picture interlaced signal, the motion adaptive processing circuit (moving picture discriminating circuit) 20 makes a moving picture discrimination between the fields in which writing is permitted, and a portion which is a moving picture is detected by the control signal from the motion adaptive processing circuit 20. It is possible to perform high-quality processing such as detecting and performing non-interlace conversion on a part which is a moving image by inter-field interpolation, and non-interlace conversion between fields on a still image part. Various methods can be used as a method for improving the image quality such as motion adaptive processing, and a detailed description thereof will be omitted here.

The state of the series of writing and reading operations will be described with reference to FIG. In the figure, a vertical one-dot chain line indicates a vertical synchronizing signal on the input side, and its interval indicates one field of the input video signal (interlace). The vertical broken line indicates the vertical sync signal on the output side, and the interval thereof indicates one frame of the output video signal (non-interlace). Also, the diagonal solid line indicates the writing operation, and the attached numeral indicates the field number to be written. Further, the diagonal broken line indicates the reading operation, and the attached circled numbers are the field numbers stored in the field memory to be read. The numbers shown in the upper part of the figure indicate the field number of the input video signal and the frame number (with parentheses) of the read video signal.

First, the field 1 video signal of the input signal is written in the first memory 150 of the odd field memory. Then, the video signal of field 2 is written in the first memory 152 of the even field memory. Further, the video signal of field 3 is written in the second memory 151 of the odd field memory. Here, since the synchronizing signal on the output side is not detected in the field 3, the thinning signal (201) is output to the field 4, and the video signal of the field 4 is thinned and writing is not performed. The succeeding field 5 is also thinned out, and this video signal is not written and thinning out for 2 fields is performed. Then, the video signal of field 6 is written in the second memory 153 of the even field memory, and the video signal of field 7 is written in the first memory 150 of the odd field memory and previously written. The video signal of field 1 is rewritten to the video signal of field 7. Then, the video signal of field 8 is written in the memory 153, and the video signal of field 2 previously written is rewritten to this video signal. After that, the same thinning and rewriting are sequentially performed.

The read operation will be described below. The read operation is
This is performed by alternately reading the odd-numbered field memory and the even-numbered field memory for each vertical synchronization signal. When reading the first frame (1), the memory 150 and the memory 153 in which the writing operation is not performed within this reading period are selected, and the video signal of field 1 and an even number (0) one field before that are selected. The video signal of the field is read. Next, when reading the second frame (2), the memory 151 and the memory 152 in which the writing operation is not performed and the new video signal is written within this period are selected, and the video signal of the field 3 and the field 2 are selected. The video signal is read. Furthermore, when the third frame (3) is read, the memory 150 and the memory 153 are targets for writing within this period, so the memory 151 and the memory 152 are selected,
The video signal of field 3 and the video signal of field 2 are read out. When reading the fourth frame (4), since the memory 150 is being written and the memory 152 is being written within this period, the memory 151 and the memory 153 are selected, and the video signal of the field 3 and the field 6 The video signal is read. Thereafter, the video signal is similarly read out.

As described above, according to this embodiment, when the interlaced / non-interlaced conversion is performed, the input signal is thinned out continuously in two fields.
In this way, without causing memory overtaking,
It is possible to perform frame frequency conversion and non-interlaced conversion at the same time. Note that the switches 154 to 15
9 can be achieved by software by performing write control and read control of the memory. If a random access field memory is used as the memory, the number of memories is set to two for odd and even, and the write start address is switched to switch the switches 155 and 156 and switch 157 and switch 158. It is also possible to replace with.

Although not specifically mentioned in the present embodiment, by adding functions such as automatic interlaced / non-interlaced discrimination and automatic field discrimination of interlaced signals, an input signal can be automatically converted into a desired output signal. It is also possible to convert to.

As described above, the frame frequency conversion and the interlace / non-interlace conversion can be simultaneously performed by a series of operations. Further, if the frequencies of the input side vertical synchronization signal (1) and the output side vertical synchronization signal (4) are made equal, only interlace / non-interlace conversion can be performed, and interlace / non-interlace conversion is performed. If not provided, only the frame frequency conversion can be performed. Further, the capacity of the conventional memory requires at least an image memory for two fields for interlace / non-interlace conversion and an image memory for two frames for frame frequency conversion. As can be seen from the operation, the interlace / non-interlace conversion and the frame frequency conversion are performed at the same time, so that it can be realized by having a memory capacity of 2 frames.

Next, the second embodiment of the image processing apparatus according to the present invention.
FIG. 8 shows a configuration diagram of this embodiment. The image processing apparatus of this embodiment includes a sync separation circuit 11, a PLL circuit 12, an A / D
Conversion circuit 13, field thinning circuit 14, memory 1
5, a write control circuit 16, a read control circuit 17, and a PL
An L circuit 18, a DA conversion circuit 19, a motion adaptive processing circuit 20, an enlargement / reduction control circuit 21 for controlling enlargement / reduction processing at an arbitrary magnification, and a scanning line interpolation circuit 22 for performing scanning line interpolation and the like. It The circuit from the sync separation circuit 11 to the motion adaptive processing circuit 20 is substantially the same as the circuit of the first embodiment.

FIG. 9 is a block diagram showing an example of the configuration of the scanning line interpolation circuit 22 for performing scanning line interpolation. The scanning line interpolation circuit 22 includes a line memory 221 and a line memory 222, and a coefficient multiplication circuit 22 for weighting data.
3 and 224, an adder 225 for adding two data, a switch 226 for selecting a line memory to write a video signal, a write control circuit 227 for controlling writing in each line memory, and each line. It is composed of a read control circuit 228 which controls the reading of the memory. The scanning line interpolation device 22 first writes the data of two consecutive lines in the line memory 221 and the line memory 222,
The written data is weighted by the coefficient multiplication circuit 223 and the coefficient multiplication circuit 224.

FIG. 10 shows an example of the principle of weighting.
For example, when enlarging an image three times in the vertical direction,
An example in which two scanning lines m + 1 and m + 2 are interpolated between two continuous scanning lines of n and n + 1 of the input scanning lines to obtain read scanning lines of m to m + 3 will be described. The data of the input scanning line n is written in the line memory 221, and the input scanning line n
The +1 data is written in the line memory 222. The data written in the second line memory is read out simultaneously in synchronization with each pixel of each scanning line. Here, in the read scanning line m whose position coincides with the input scanning line n, the coefficient multiplier 223 multiplies the read data in the line memory 221 by a count a = 1, and the counting multiplier 224 in the line memory 222. The read data is multiplied by the count b = 0.
That is, the data of the input operation line n is read as it is from the read scanning line m. In the read scanning line m + 1 in which the input scanning line is internally divided into 1: 2, the coefficient multiplier 223 multiplies the read data of the line memory 221 by the count a = 2/3, and the counting multiplier 224 is the line memory. The read data of 222 is multiplied by the count b = 1/3. Similarly, input scan line is 2: 1
In the read scanning line m + 3 which is internally divided into
3 is a count of the read data of the line memory 221 a = 1/3
The count multiplier 224 multiplies the read data of the line memory 222 by the count b = 2/3. Input scan line n +
In the output scanning line m + 3 on the scanning line 1 of 1, the coefficient multiplier 223 counts the read data of the line memory 221 with a = 0.
The count multiplier 224 multiplies the read data of the line memory 222 by the count b = 1. That is, the read scanning line m
At +3, the data of the input operation line n + 1 is read as it is. Thus, the counting multiplier 223 and the counting multiplier 2
A predetermined count is set in 24, the read lines are weighted, and the adder 225 interpolates the scanning lines to realize enlargement. Interpolation between lines can be performed by changing the coefficient set in the coefficient multiplier according to the enlargement ratio.

In this embodiment, in order to enable the moving picture adaptive processing, the motion adaptive processing circuit 20 prepares at least three line memories as shown in FIG. The motion adaptive processing circuit 22 includes three line memories 201, 202, 20.
3 and the line memory selection switch 204 for writing data
And a line memory selection switch 205 for reading. The input data is the data written in the odd field memory 150 (151) and the even field memory 152 (153) of the memory 15, and is selected by the read control switch 206.

Image data to the line memories 201 to 203
As shown in FIG. 12, writing of data is performed by cyclically selecting and selecting three line memories for each output side horizontal synchronizing signal (5). That is, in the first output-side horizontal sync signal, the data of the nth line of the data written in the odd field memory 150 is written in the first line memory 201 and the data written in the even field memory 152. The data of the nth line is written in the second line memory 202, and the data of the n + 1th line of the data written in the odd field memory 150 is written in the third line memory 203. Next, with the second output-side horizontal synchronizing signal, the data written in the first line memory 201 is rewritten by writing the data of the (n + 1) th line of the data written in the even field memory 152. With the third output side horizontal synchronizing signal, the data written in the second line memory 202 is rewritten by writing the data of the (n + 2) th line of the data written in the odd field memory 150. With the fourth output-side horizontal sync signal, the data written in the third line memory 203 is rewritten by writing the data of the (n + 2) th line of the data written in the even field memory 152. In this way, the data in the three line memories is rewritten sequentially with the line data of the odd field or the even field for each output side horizontal synchronizing signal.

Next, when the still image interlace signal is input, the first line memory 201 is read by the first read horizontal synchronizing signal, and the second read horizontal synchronizing signal is read by the second line memory. The line memory 202 is selected by the third read horizontal synchronizing signal, and the third line memory 203 is selected.
After that, the line memories 201 to 203 are cycled and read for each read horizontal synchronizing signal. As a result, interlaced / non-interlaced conversion by inter-field interpolation becomes possible. When a moving image interlace signal is input, the moving image portion detected by the motion detection circuit is interlaced / non-interlaced by intra-field interpolation, and the still image portion is inter-field interpolated. That is, as shown in FIG. 13, the switch 205 is switched to read the data so that the portion determined to be a moving image becomes the same as the data one line before. Here, if the enlargement processing by weighting is performed, the enlargement can be performed at the same time. As described above, since the enlargement processing is performed between the fields as compared with the conventional enlargement processing circuit that has performed the enlargement processing in the field, it is possible to perform high-quality enlargement display.

FIG. 14 shows the third embodiment. This embodiment uses Pin P (Picture in P) by using a plurality of input video signals.
(icture) is an example of an inset synthesis circuit that performs inset synthesis of a screen. The embedded synthesis circuit of this embodiment is
The image processing circuit 1 according to the second embodiment shown in FIG. 8, a sync separation circuit 31, a clamp 32, and a selection switch 33 for switching between two system signal outputs. The video signals S1 and S2 of two systems are input to this synthesizing circuit. The first video signal S1 is input to the clamp 32, and the horizontal synchronizing signal and the vertical synchronizing signal thereof are separated by the sync separating circuit 31 and input as the output side synchronizing signal of the image processing circuit 1. The second video signal S2 is input as an input video signal of the image processing circuit 1.

The input image signal S2 is enlarged / reduced by the image processing circuit 1 by the method shown in the second embodiment and non-interleaved.
Input video signal S
Output in synchronization with 1. The selection switch 33 selectively switches between the input video signal S1 from the clamp 32 and the input video signal S2 processed by the image processing circuit 1 and outputs it.
Inset composition of screens such as P is performed. According to this embodiment, since the image processing circuit 1 is provided, the inset image can be output as a signal having the same property as the host image,
Even if the input video signals of the two systems are any combination of the video signals of the interlace signal or the non-interlace signal, the signals of the two systems can be synchronized to enable screen synthesis. It should be noted that any technique may be used for the technique such as inset synthesis, and the description of the synthesis method is omitted.

A fourth embodiment will be described with reference to FIG.
This embodiment is an example of a magnifier of a large-screen display system that magnifies and displays an input video signal on a four-sided display screen. The expander of this embodiment has a sync separation circuit 1
1, PLL circuit 12, AD conversion circuit 13, and
A field thinning discrimination circuit 14, an enlargement control circuit 21, a field memory 251-254, and a memory unit 25 including a circuit for controlling writing and reading of the field memory,
It is composed of a PLL circuit 18, DA conversion circuits 191-194, and displays 41-44.

The field memories 251 to 254 each have two systems of field memories as in the first embodiment, and are configured to perform interlace / non-interlace conversion.

Next, the operation of this embodiment will be described.
In the field memories 251 to 254, the upper left portion of the display is the memory 251 and the upper right portion is the memory 25.
2, the lower left part is the memory 253, and the lower right part is the memory 2
54. First, the input video signal S1 to be enlarged and displayed on each display is stored in each of the field memories 251-2.
54 captures only the portion to be enlarged and displayed. At this time, as in the first embodiment, the field thinning circuit 14 discriminates the field thinning according to the vertical synchronizing signal (1) of the input signal and the vertical synchronizing signal (4) from the display to determine the frame thinning.
Enable frequency conversion. Refer to the first embodiment for the detailed operation of the field thinning.

Further, the video signal taken into each memory is read out from the memory, and the enlargement control circuit 15 is used as in the second embodiment.
A large screen display is realized by performing enlargement processing, interlace / non-interlace conversion, etc., and displaying on each display. As a result, even for a single-scan display, regardless of the interlace or non-interlace, any video signal is enlarged and non-interlaced.
It becomes possible to convert and display.

FIG. 16 shows the fifth embodiment. The feature of this embodiment lies in that the control signal (7) from the thinning-out determination circuit does not control the write control circuit but controls the read control circuit. That is, the field thinning process is performed at the time of reading. The image processing apparatus according to the present exemplary embodiment includes a sync separation circuit 11, a PLL circuit 12, and an AD conversion circuit 13.
A field thinning circuit 14, a memory group 15 including a plurality of field memories, a write control circuit 16, a read control circuit 17, a PLL circuit 18, and a DA conversion circuit 1.
9 and a motion adaptive processing circuit (moving image discrimination circuit) 20. The output of the field thinning circuit 14 is input to the write control circuit 17. The operation of each circuit is substantially the same as each circuit of the image processing apparatus of the first embodiment.

Next, the operation of the memory group 15 will be described. The pixel data of the video signal S1 is circulated for each vertical synchronizing signal (1) of the input signal in the same manner as in FIG. 6 of the first embodiment, and the memory is selected and written. The reading of the data from the memory is performed by selecting a memory in which the writing operation is not performed from the field thinning circuit 14. In this memory selection control, a control signal for selecting a memory from which data is read receives information (8) of the memory that is writing from the write control circuit 16 and selects a memory from which data is read. Also, interlace / non-interlace conversion is performed when reading the memory.

In this way, by performing frame frequency conversion and interlace / non-interlace conversion on the reading side,
The same effect as in the first embodiment can be obtained.

[0043]

According to the present invention, frame frequency conversion and non-interlace conversion can be executed at the same time, and the required memory capacity and circuit scale can be reduced. It also makes it possible to convert any signal source into a desired signal source.

[Brief description of drawings]

FIG. 1 Interlace / Noninterlace conversion and frame
FIG. 3 is a block diagram showing the configuration of an image processing apparatus that enables simultaneous frequency conversion.

FIG. 2 is a block diagram showing a configuration of a field thinning circuit for thinning out two fields.

FIG. 3 shows an example of a field thinning decision circuit.

FIG. 4 is a timing chart of field thinning.

FIG. 5 is a block diagram showing a configuration of a memory.

FIG. 6 is an explanatory diagram of an error caused by field thinning during non-interlace conversion.

FIG. 7 is a timing diagram illustrating operation of a memory.

FIG. 8 is a block diagram showing a configuration of an image processing apparatus according to a second embodiment.

FIG. 9 is a block diagram showing a basic configuration of a scanning line interpolation circuit.

FIG. 10 is an algorithm explanatory diagram illustrating an operation of scanning line interpolation.

FIG. 11 is a block diagram showing the configuration of a motion adaptive processing circuit that enables non-interlace conversion according to the second embodiment.

FIG. 12 is a diagram showing a memory writing method of the motion adaptive processing circuit.

FIG. 13 is a diagram for explaining reading of memory data by motion adaptation.

FIG. 14 is a block diagram showing the configuration of a third embodiment of the image processing apparatus of the present invention.

FIG. 15 is a block diagram showing the configuration of a fourth embodiment of the image processing apparatus of the present invention.

FIG. 16 is a block diagram showing the arrangement of a fifth embodiment of the image processing apparatus of the present invention.

FIG. 17 is an explanatory diagram of a conventional technique for performing interlace / non-interlace conversion and frequency conversion.

[Explanation of symbols]

1 image processing circuit 5 interlace / non-interlace conversion circuit 6 frequency conversion circuit 11 sync separation circuit 12 PLL circuit 13 A / D conversion circuit 14 field thinning circuit 15 memory 16 write control circuit 17 read control circuit 18 PLL circuit 19 D / A conversion circuit 20 Motion adaptive processing circuit 21 Enlargement / reduction control circuit 22 Scan line interpolation circuit 25 Memory 31 Sync separation circuit 32 Clamp 33 Selection switch 41-44 Display 14 Field thinning circuit 401-404 Interlace signal file -Field information 405 to 407 Non-interlace signal field information 408 Input side vertical sync signal 409 Output side vertical sync signal 1203 Clamp circuit 1501 Frequency converter 1502 Interlace / Noninterlace converter

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Fumio Inoue, 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa, Ltd. Inside the Hitachi Media Visual Media Laboratory (72) Inventor, Osamu Ogino, 216, Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi, Ltd. Information & Video Media Division (72) Inventor Masao Iwanaga 216 Totsuka-cho, Totsuka-ku, Yokohama, Kanagawa Prefecture Hitachi's Information & Video Media Division

Claims (9)

[Claims] 1. Image processing for simultaneously realizing interlaced signals into non-interlaced signals by interpolating an input video signal between fields or by inter-field and intra-field motion adaptive processing and frequency conversion of the input video signal. In the device, two systems of field memory for taking in the image data of the input video signal, one for the odd field and one for the even field, the input and output vertical sync signal and horizontal sync signal input terminals, and the input video signal vertical sync signal and output Field thinning is determined from the relationship between the frequency and phase of the vertical sync signal for display, and when it is determined to perform field thinning, a write inhibit signal is generated to inhibit writing of image data of the input video signal to the field memory. The field thinning circuit and the image data of the input video signal A write control circuit that executes control for writing to a field memory based on a sync signal extracted from an input video signal and the presence or absence of a write inhibit signal output from the field thinning circuit, and control for reading image data from the field memory And a read control circuit for executing the above based on the output display synchronizing signal. 2. The field thinning circuit is a circuit for performing a thinning decision of a field when an output display vertical synchronizing signal is not generated within one cycle of a vertical synchronizing signal of an input video signal. Image processing device. 3. The field thinning circuit prohibits writing image data of two consecutive fields of the input video signal to the field memory when it is determined that the input video signal is an interlaced signal and the field is thinned out. 3. The image processing apparatus according to claim 1, wherein the image processing apparatus is a circuit that generates a write inhibit signal. 4. The field thinning circuit inhibits writing of image data of one field of the input video signal to the field memory when it is determined that the input video signal is a non-interlaced signal and the field is thinned. The image processing apparatus according to claim 1 or 2, which is a circuit that generates a write inhibit signal. 5. The image processing apparatus according to claim 1, wherein the read control circuit is a circuit for reading the image data stored in the same field memory in each of a plurality of consecutive fields. 6. Image processing for simultaneously implementing inter-interlaced signals into non-interlaced signals by interpolating an input video signal between fields or by inter-field and intra-field motion adaptive processing and frequency conversion of the input video signal. In the device, two systems of field memory for taking in the image data of the input video signal, one for the odd field and one for the even field, the input and output vertical sync signal and horizontal sync signal input terminals, and the input video signal vertical sync signal and output Field thinning is determined based on the relationship between the frequency and phase of the vertical sync signal for display, and when it is determined to perform field thinning, a write inhibit signal is generated to inhibit writing of image data of the input video signal to the field memory. Field thinning circuit, the sync signal extracted from the input video signal, and A write control circuit for controlling the image data of the input video signal to be written into the field memory for each field based on the write inhibit signal output from the field thinning circuit, and from the field memory based on the output display synchronizing signal. A read control circuit for controlling the reading of the image data, a means for switching the field memory for reading the image data for each output display horizontal synchronizing signal, and image data of an image area at an arbitrary position of the image data written in the field memory To a plurality of line memories and scan line interpolation circuits for performing inter-field and intra-field scanning line interpolation on the image data read from the line memories and a variable read frequency of the field memories, or a field memory Repeatedly read the data address of Details, by reading by skipping the data address of the field memory, image processing apparatus characterized by having a scaling circuit for enlarging process or reducing process of the image data. 7. A clamp circuit for aligning the color levels of the first input video signal for inset synthesis of the screen by using at least two or more input video signal systems, and for separating the synchronization signal from the first input video signal. An image processing device comprising a sync separation circuit, an image processing circuit for compressing and expanding image data of a second input video signal, and an image selection switch,
The image processing circuit includes a first input terminal to which a vertical synchronizing signal and a horizontal synchronizing signal of a first input video signal are input, a second input terminal to which a second input video signal is input, and a second input terminal. 2 field memories for the odd field and the even field, which capture the image data of the input video signal, and the frequency and phase of the vertical sync signal of the first input video signal and the vertical sync signal of the second input video signal. A field thinning circuit that generates a write inhibit signal that inhibits writing of image data of an input video signal to a memory when the field thinning determination is performed based on the relationship, and the first input The image data of the second input video signal is field-based on the basis of the sync signal extracted from the video signal and the write inhibit signal output from the field thinning circuit. A write control circuit for controlling writing in the field memory, a read control circuit for controlling reading of image data from the field memory based on a synchronization signal of a first input video signal, and a read control circuit for writing image data in the field memory. The image data of the image area at an arbitrary position is loaded into a plurality of line memories, and the image data read from the line memories is provided with a scanning line interpolation circuit for performing scanning line interpolation between fields and within fields, and a reading frequency of the field memory. An enlargement / reduction circuit that enlarges or reduces the image data by making it variable, repeatedly reading the data address of the field memory a plurality of times, or by skipping the data address of the field memory; Image data of the input video signal or the second input Inset synthesis image processing device capable of a screen, characterized by comprising a selection switch for selectively outputting one of the image data of the image signal. 8. An image processing apparatus for generating a video signal to be displayed on a display comprising a large-screen multi-display system in which a plurality of displays are combined, a means for extracting a sync signal from the input video signal, and a vertical sync signal for the input video signal. Field thinning is determined based on the relationship between the frequency and phase of the external vertical sync signal for synchronizing control of each display, and when it is determined that field thinning is performed, the image data of the input video signal is written to the memory. A field thinning circuit for generating a write inhibit signal for prohibiting, a field memory for writing image data to be displayed on each display, provided at least two corresponding to each display, and a vertical synchronizing signal from an input video signal. Based on the prohibition signal from the field thinning circuit, A write control circuit that controls the writing of image data to the read memory, and the read frequency of the field memory is made variable, or the data address of the field memory is read repeatedly multiple times to enlarge the image data. A control circuit, a read control circuit that controls the reading of the image data written in each field memory based on the output of the enlargement control circuit, and a scanning line interpolation circuit that performs scanning line interpolation of the image data read from the field memory. An image processing apparatus comprising: 9. An interlaced signal is converted into a non-interlaced signal by interpolating an input video signal by inter-field interpolation or inter-field and intra-field motion adaptive processing to convert a frame frequency and an interlaced signal into a non-interlaced signal. In an image processing apparatus that simultaneously realizes non-interlace conversion for conversion into two fields, there are two systems of field memories for odd field and even field that capture image data of an input video signal, and a vertical sync signal and a horizontal sync signal for output display. An input terminal, a write control circuit that controls writing of an input video signal consisting of an interlaced signal into two field memories alternately for each vertical sync signal of the input video signal, and a vertical sync signal for output display and an input video signal. Judgment of field thinning from the relationship between frequency and phase of vertical sync signal When a determination is made to perform field thinning, a field thinning circuit that generates a read inhibit signal that inhibits reading of image data written in the field memory, an output display synchronization signal, and a read from the field thinning circuit An image processing apparatus comprising: a read control circuit for controlling reading of image data from the field memory based on a prohibition signal; and a circuit for switching a field memory for reading image data for each output display horizontal synchronizing signal. .