JP2000020009A - Clock adjusting circuit, and picture display device using it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock adjusting circuit provided with a means for adjusting a frequency of a dot clock of a video signal to a frequency of a reproduced dot clock and a means for optimizing a phase of a reproduced dot clock. SOLUTION: This device is provided with a frame difference circuit 1 making frame difference between a first pixel and a second frame which is one frame before the first frame, an absolute value circuit 2 making an absolute value of frame difference data outputted from the frame difference circuit 1, an integral circuit 3 circularly adding absolute valued data outputted from the absolute value circuit 2 by several frames and integrating it, a register 4 storing integrated data obtained by the integral circuit 3, an arithmetic circuit inputting data stored in the register 4 and calculating it, a PLL(phase locked loop) circuit 5 inputting a detected result outputted from the arithmetic circuit to a frequency divider as a frequency dividing ratio, and an adjusting circuit 6 adjusting phase difference between a dot clock after adjustment outputted from the PLL circuit 5 and a video signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a personal computer and an EWS.
The present invention relates to a clock adjusting circuit of a display device using a lattice device such as a liquid crystal, a plasma, and an EL capable of displaying information such as (Engineering Workstation) and an image display device using the same.

[0002]

2. Description of the Related Art Since the signal level of a video signal from a personal computer or an EWS changes at a constant period shorter than the period of a horizontal synchronizing signal, it is difficult to display the image signal on a display using a lattice device such as a liquid crystal. A dot clock is required. Liquid crystal display devices generally use a PLL (Phase Locked L
oop) circuit, determines the dot period from the video signal input to the device, detects a fixed period shorter than the dot period and the horizontal synchronization signal period, and determines the ratio of the dot clock period to the horizontal synchronization signal period. Are input to the programmable divider. This input corresponds to the total number of dots in one horizontal scanning period, and the multiplication of the PLL circuit is used as the total number of dots to reproduce the dot clock.

[0003] As a liquid crystal display device, Japanese Patent Laid-Open Publication No.
No. 94 discloses this. FIG. 4 shows a liquid crystal drive circuit system of one embodiment of the liquid crystal display device of the publication.

In FIG. 1, reference numeral 11 denotes an input terminal to which a composite video signal from a television tuner is supplied,
12a and 12b are connected to, for example, a computer system, and are connected to an RGB video signal, a vertical synchronization signal V,
Indicates an input terminal to which is supplied.

[0005] The composite video signal input from the input terminal 11 is demodulated into RGB signals, while being supplied to a sync separation circuit 14 to extract a vertical sync signal V and a horizontal sync signal H.

Reference numeral 16 denotes a polarity inversion circuit, 17 denotes a timing controller, 18 denotes a video buffer, 19 denotes a signal line driver, 20 denotes a gate line driver, 21 denotes a liquid crystal panel, and R, B, and G signals are: In order to prevent the liquid crystal material from deteriorating due to the application of the DC voltage to the liquid crystal panel 21 for a long time, the polarity is supplied to the polarity reversing circuit 16 and the polarity is reversed based on a predetermined polarity switching timing signal supplied from the timing controller 17. . Then, the signal line driver 1 via the video buffer 18
9 is input.

According to a control signal from the timing controller 17, a signal line driver 19 and a gate line driver 20 apply pixel electrode voltages, that is, signal voltages to a liquid crystal panel 21 in which signal lines and gate lines are arranged in a matrix as shown in FIG. Then, a horizontal scanning voltage is applied.

That is, the gate lines G1 to Gm are sequentially
A horizontal scanning voltage is applied to turn on the active element T of each pixel in one horizontal period, and a signal voltage is applied from the signal lines S1 to Sn to drive the liquid crystal LC in each pixel. As described above, each pixel of the liquid crystal panel 21 is driven, and a liquid crystal display is performed by controlling the transmittance of light transmitted from a backlight (not shown) on a pixel basis.

Reference numeral 22 denotes a phase comparator, 23 denotes a voltage controlled oscillator, 24 denotes a 1 / N divider for dividing the output of 23 by 1 / N, and a horizontal synchronizing signal H is input to the phase comparator 22,
The phase is compared with the output signal of the 1 / N divider 24,
A phase voltage is output. Then, the voltage controlled oscillator 23 outputs an oscillation frequency controlled based on the supplied phase difference voltage.

That is, since N in the 1 / N frequency divider 24 is properly set, in this embodiment, a so-called N
When the PLL loop is locked, a dot clock synchronized with the horizontal synchronizing signal can be obtained as the output of the voltage controlled oscillator 23.

As described above, in order to generate a dot clock from the horizontal synchronizing signal in the input video signal, the phase comparator 22, the voltage controlled oscillator 23, the 1 / N divider 24,
, It is not necessary to provide a dot clock input means from a fixed dot clock generator for an NTSC video signal, for example. It is stated that a liquid crystal display device capable of selecting a video source can be realized.

[0012]

However, when displaying an image on a display, it is necessary to display the image in accordance with a video signal. For that purpose, the frequency of the reproduced dot clock must be adjusted to the frequency of the dot clock of the video signal. Further, even if the frequency of the dot clock of the video signal and the frequency of the reproduced dot clock match, if the phases of both signals are shifted, the image flickers.

In particular, when reproducing a dot clock,
The only information that can be known on the display is the horizontal synchronization signal. Therefore, there is no guarantee that the division ratio of the programmable divider of the PLL circuit is set correctly. If the division ratio is not set correctly, the reproduced dot clock cannot be generated at the same frequency as the dot clock frequency of the video signal. That is, a point occurs where a dot clock for taking in video data and a video signal are shifted.

In a dot clock reproducing circuit using a PLL circuit, fluctuations (jitter) on the time axis occur in the reproduced dot clock. Jitter is determined by a time constant circuit such as a loop filter of a PLL circuit and generally cannot be reduced to zero because of a trade-off relationship with response speed. Therefore, even if a reproduced dot clock having a frequency equivalent to the frequency of the dot clock of the video signal is generated, it is difficult to display a stable image if the phase is not correct.

Furthermore, if the frequency of the dot clock of the video signal and the frequency of the reproduced dot clock do not match, when an inversion signal for inverting black and white for each dot is added as an adjustment signal, moire having a vertical stripe pattern on the screen. A pattern occurs. Specifically, since the number of pixels of the display device and the number of dots of the video signal do not match, moire having a vertical stripe pattern is generated by the number of differences between the two. That is, there is a problem such as flickering of an image.

(Object of the present invention) In order to solve the above problems,
SUMMARY OF THE INVENTION It is an object of the present invention to provide a clock adjusting circuit including means for adjusting the frequency of a reproduced dot clock to the frequency of the dot clock of a video signal and means for optimizing the phase of the reproduced dot clock.

[0017]

A clock adjustment circuit according to the present invention comprises a first pixel and a second pixel one frame before the first pixel.
A frame difference circuit for taking an inter-frame difference with the pixel of
An absolute value circuit for converting the frame difference data output from the frame difference circuit into an absolute value, an integration circuit for cyclically adding and integrating the absolute value data output from the absolute value circuit for several frames, and the integration circuit A register for storing the integrated data obtained in step (a), an arithmetic circuit for inputting the stored data stored in the register and calculating the difference between the frequency of the dot clock of the video signal and the frequency of the reproduced dot clock; A PLL circuit for inputting the detected result to a programmable divider as a frequency division ratio;
An adjusting circuit for adjusting a phase difference between the adjusted dot clock output from the LL circuit and the video signal is provided.

Further, the clock adjusting circuit of the present invention is characterized in that it comprises means for adjusting the frequency of the reproduced dot clock to the frequency of the dot clock of the video signal, and means for optimizing the phase of the reproduced dot clock.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A clock adjusting circuit according to an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram illustrating a pixel column of an arbitrary horizontal line and a clock adjustment circuit according to the present embodiment. The clock adjustment circuit includes: a frame difference circuit 1 that calculates a frame difference between an arbitrary pixel and a pixel one frame before the pixel; an absolute value circuit 2 that converts frame difference data output from the frame difference circuit 1 into an absolute value; An integration circuit 3 for cyclically adding and integrating the absolute value data output from the absolute value circuit 2 for several frames
And a register 4 for storing the integrated data obtained by the integrating circuit 3, and a CPU as an arithmetic circuit for inputting the stored data output from the register 4 and calculating the difference between the frequency of the dot clock of the input signal and the frequency of the reproduced dot clock. And a PLL circuit 5 for inputting a detection result output from the CPU as a dividing ratio to the programmable divider, and an adjusting circuit 6 for adjusting a phase difference between the adjusted dot clock and the video data.

Next, the operation of this embodiment will be described with reference to FIG. First, a predetermined dividing ratio W according to the frequency of the horizontal synchronizing signal is set in advance in the programmable divider of the PLL circuit 5.

As in the above-mentioned prior art, the video data and the dot clock are separately written on one line on the display.
The data is output to a line having the number of pixels, and is sequentially input in real time from the first pixel of one line to the Nth pixel.

Next, the video data output from the pixel m and the video data output from the pixel n are input to the frame difference circuit 1n, and the frame difference data obtained by calculating the difference between the pixel frames is output. . In addition, the input video data is applied by applying a vertical synchronization pulse (V pulse).
The data is held and output for one frame.

Next, the frame difference data obtained by the frame difference circuit 1 is input to the absolute value circuit 2,
The absolute-valued data that has been converted into the absolute value is output. The absolute value data is input to an integration circuit 3 for cyclically adding and integrating several frames. Further, the data obtained by the integration circuit 3 is stored in the register 4.

The data stored in each register 4 is shifted by a shift register to a CPU or the like. The CPU calculates each stored data in order from the first to the n-th, and calculates the number of local maxima occurring in one horizontal period.

Specifically, for example, 1024 lines per line
102 per line for displays with pixels
Consider a case where four dot clocks have been reproduced. Then, the relationship between all of the arbitrary pixels on one line and the dot clock is as shown in FIG. Therefore, one of the pixels
The frame difference data from the pixel before the frame becomes zero. That is, the data stored in each register 4 is all zero.

Here, FIG. 2 is a diagram showing a state in which the rising edge of the dot clock of the video signal is located substantially at the center of the video data, and the hatched portion indicates the jitter component.

On the other hand, for example, consider a case where 1023 dot clocks are reproduced per line for a display having 1024 pixels per line. Then 1
The relationship between the dot pixel or the 1024th pixel and the dot clock is as shown in FIG. Therefore, the frame difference data between the pixel and the pixel one frame before is zero. That is, the data stored in each register 4 is zero. FIG. 2 also shows the relationship between the dot clock and the pixels around the first pixel or the pixels around the 1024th pixel.

However, the pixel at the 512th pixel at the center of one line and its peripheral pixels are in a dot-inverted state. Therefore, in the 512th peripheral pixel, the relationship between the video data and the dot clock is as shown in FIG.
In the state of FIG. 3, the frame difference data of the pixel has a large value. That is, the data stored in the register 4 also has a large value.

Here, FIG. 3 is a diagram showing a state where the rising edge of the dot clock of the video signal straddles the video data, and the hatched portion indicates the jitter component existing area.

That is, when the frequency of the dot clock of the video signal does not match the frequency of the reproduced dot clock, the states of the video data and the dot clock of the video signal shown in FIG. 2 and the video data and the video signal shown in FIG. The state of the dot clock appears as a mixture.

In the state shown in FIG. 2, the frame difference data of each pixel is substantially zero, and the result of integration by the integration circuit 3 is also substantially zero. The result of this integration is stored in the register 4. In the state of FIG. 3, data may not be read for each frame due to the jitter component of the clock. More specifically, the n-th data may be fetched in a certain frame, and the (m + 1) -th data may be fetched in the next frame. In the case of the state shown in FIG. 3, the frame difference data has a large value. Therefore, the data is integrated by the integration circuit 3 and the integration result is stored in the register 4.

When the frequency of the dot clock of the video signal does not match the frequency of the reproduced dot clock, the relationship between the video data and the dot clock becomes larger as the pixel goes from the first pixel to the n-th pixel. The state gradually changes from the state of FIG. 2 to the state of FIG. 3, and further returns to the state of FIG.

Therefore, the CPU sequentially checks the value of the data stored in the register 4 from the end and calculates the number of local maxima appearing in one horizontal scanning period, whereby the dot clock of the video signal and the PLL circuit 5 can be programmed. The frequency division ratio set in the divider, that is, the calculation result Q can be obtained. In the case of the above specific example, the number of the maximum value is one.

The frequency division ratio is input to the programmable divider of the PLL circuit 5 so that the operation result calculated as described above, that is, the difference data between the dot clock of the video signal and the reproduced dot clock becomes zero, Perform the above process again. For example, assuming that the division ratio previously input to the programmable divider is W and the calculation result is Q, W + Q is input to the programmable divider, and again,
Difference data between the dot clock of the video signal and the reproduced dot clock is obtained.

If the result of the second calculation is zero, it means that the frequency of the dot clock of the video signal is equal to the frequency of the reproduced dot clock. On the other hand, if the second detection result is larger than the first detection result,
WQ is input to the programmable divider.

Next, while operating the adjustment circuit 6, the frame difference data at an arbitrary pixel is calculated by the same calculation method as the above-described calculation of the frame difference data. As described above, the frequency of the dot clock of the video signal and the frequency of the reproduced dot clock were adjusted. Therefore, the phase relationship between the dot clock of the video signal and the reproduced dot clock in all the pixels is a mixture of the state of FIG. 2 and the state of FIG.

Accordingly, the frame difference data is calculated while changing the phase difference between the adjusted dot clock and the video signal, and the phase is adjusted so that the calculated data becomes the minimum, that is, the state shown in FIG. I do.

Therefore, by this series of operations, adjustment is made so that the frequency of the dot clock of the video signal matches the frequency of the reproduced dot clock. Further, by adjusting the frequency, the phase of the reproduced dot clock can be matched with the phase of the dot clock of the video signal.

Further, an image display system can be formed together with an image display device such as a liquid crystal display using the clock adjusting circuit. The image display system
For example, it can be formed by combining the liquid crystal panel 21 shown in FIG. 4 as a conventional technique with the clock adjustment circuit according to the present embodiment.

That is, a dot clock is reproduced by the clock adjusting circuit according to the present embodiment, and the reproduced dot clock is input to the liquid crystal panel 21 together with the video signal and the synchronization signals H and V to perform a desired display. Can also.

[0041]

The clock adjusting circuit according to the present invention sets a general frequency division ratio according to the frequency of the horizontal synchronizing signal in the programmable divider, and sets the frequency of the reproduced dot clock from the data stored in the register. An image can be displayed according to the video signal of the display.

Further, the clock adjusting circuit of the present invention sets the frequency of the reproduced dot clock, and then changes the phase comparison circuit according to the result obtained from an arbitrary register, so that the reproduced dot clock is minimized. The clock phase can be optimized by adjusting the clock phase comparison circuit. Therefore, it is possible to prevent the flicker occurring in the image.

Further, since the frequency of the dot clock of the video signal and the frequency of the reproduced dot clock can be made to match, when an inversion signal for inverting black and white for each dot is added as an adjustment signal, the prior art is displayed on the screen. Therefore, it is possible to suppress the occurrence of a moire pattern of a vertical stripe pattern that may occur.

[Brief description of the drawings]

FIG. 1 is a clock adjustment circuit according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a state of dot clocks of video data and a video signal according to the embodiment of the present invention.

FIG. 3 is a diagram illustrating a state of a dot clock of video data and a video signal according to the embodiment of the present invention.

FIG. 4 is a block diagram showing a conventional liquid crystal display device.

FIG. 5 is an internal configuration diagram of a liquid crystal panel of a conventional liquid crystal display device.

[Explanation of symbols]

Reference Signs List 1 frame difference circuit 2 absolute value circuit 3 integration circuit 4 register 5 PLL circuit 6 adjustment circuit 11 video signal input terminal 12a, 12b RGB video signal, vertical synchronization signal V, horizontal synchronization signal H input terminal 14 synchronization separation circuit 16 polarity inversion Circuit 17 Timing controller 18 Video buffer 19 Signal line driver 20 Gate line driver 21 Liquid crystal panel 22 Phase comparator 23 Voltage controlled oscillator 24 1 / N frequency divider

Continued on front page F-term (reference) 5C006 AA01 AA22 AC28 AF44 AF50 AF52 AF53 AF61 AF72 BB11 BC03 BC12 BC16 BF02 BF03 BF14 BF15 BF23 BF28 BF49 FA16 FA23 FA27 FA29 5C020 AA11 AA40 CA11 CA15 5C058 AA06 AA10A12 A12A10A12A10A12 CC03 DD05 DD06 EE19 EE30 GG08 GG09 JJ02 JJ03 JJ04

Claims (7)

[Claims] 1. A frame difference circuit for calculating an inter-frame difference between a first pixel and a second pixel one frame before the first pixel, and a frame difference data output from the frame difference circuit as an absolute value. An absolute value circuit, an integration circuit for cyclically adding and integrating the absolute value data output from the absolute value circuit for several frames, a register storing integrated data obtained by the integration circuit, An arithmetic circuit for inputting the stored data to be stored and calculating the difference between the frequency of the dot clock of the video signal and the frequency of the reproduced dot clock; and inputting the arithmetic result output from the arithmetic circuit to the programmable divider as a dividing ratio A PLL circuit, and an adjustment circuit that adjusts a phase difference between the adjusted dot clock output from the PLL circuit and the video signal. Clock adjustment circuit. 2. A method of calculating and inputting stored data output from the register to the programmable divider set in advance to a predetermined frequency division ratio, thereby obtaining a dot clock of an input signal and a dot clock of a reproduced signal. 2. The clock adjusting circuit according to claim 1, further comprising an arithmetic circuit for calculating a difference between the frequencies. 3. The clock adjustment circuit according to claim 1, further comprising the frame difference circuit that inputs a video signal and outputs the frame difference data. 4. An apparatus according to claim 1, further comprising an absolute value circuit for inputting said frame difference data and outputting absolute value data converted into absolute values.
Clock adjustment circuit according to the paragraph. 5. An apparatus according to claim 1, further comprising an integration circuit for inputting said absolute value data, cyclically adding said absolute value data for several frames, and integrating. Clock adjustment circuit. 6. A clock adjustment circuit comprising: means for adjusting the frequency of a reproduced dot clock to the frequency of a dot clock of a video signal; and means for optimizing the phase of the reproduced dot clock. 7. An image display device comprising the clock adjustment circuit according to claim 1. Description: