JP2714302B2 - Pixel synchronizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION This invention divides a reference clock PLL circuit is output in synchronization with it in the input horizontal synchronizing signal, based on a pixel display clock created by dividing
The present invention relates to a pixel synchronizer that displays pixels .

[0002]

2. Description of the Related Art A liquid crystal projection television receives a video signal in a television broadcast.
An image is displayed on the liquid crystal panel based on the video signal.
Then, light is projected onto a screen based on the image displayed on the liquid crystal panel, and the image displayed on the liquid crystal panel is reproduced on the screen.

[0003]

By the way, this type of liquid crystal projection television receives a video signal corresponding to each pixel having a frequency different from the frequency of the video signal in the television broadcast from, for example, a personal computer. When a computer graphic is reproduced on a screen, a video signal corresponding to each pixel from a personal computer is not synchronized with a pixel display clock for displaying pixels on a liquid crystal panel. In addition, the input capacitance of the video signal input terminal of the liquid crystal panel is large, and the rising and falling edges of the video signal corresponding to each pixel may be slowed down. Therefore, when reproducing computer graphics,
There is a problem that the outline of the displayed image flickers or is blurred, and the image becomes unclear. The present invention has been made in view of the above problems, and an object of the present invention is to provide a pixel synchronization device capable of clearly displaying an image when reproducing computer graphics.

[0004]

A pixel synchronization device according to the present invention.
The pixel synchronizer divides the reference clock output from the PLL circuit in synchronization with the horizontal synchronization signal input thereto, and displays an image based on the pixel display clock generated by dividing the frequency. , Which detects the leading edge of the video signal corresponding to the pixel to be displayed,
An edge detection circuit for outputting a pulse at a time delayed by a predetermined time from the time of detection of the leading edge is provided, and the video signal and the pixel display clock are synchronized by the pulse.

[0005]

[Action] by dividing the reference clock synchronized with the horizontal synchronizing signal from the PLL circuit outputs the divider to create a pixel display clock that displays the pixels. A leading edge of a video signal corresponding to each pixel is detected, and a pulse delayed by a predetermined time from the leading edge detection point is created. The generated pulse synchronizes the video signal and the pixel display clock. Thereby, the video signal corresponding to each pixel and the pixel display clock are synchronized, and the outline of the displayed image becomes clear.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings showing the embodiments. FIG. 1 is a block diagram showing a main configuration of a liquid crystal projection television which is a pixel synchronization device according to the present invention. The liquid crystal projection television has an edge detection circuit 18 for detecting a rising edge and a falling edge of a video signal input thereto, and a PLL (phase lock loop) circuit for generating a reference clock synchronized with the input horizontal synchronization signal 9.
16 and a frequency divider that divides the clock generated by the PLL circuit 16
23. The edge detecting circuit 18 includes a differentiating circuit 2,
It comprises a comparator 3 and a set pulse generating circuit 6.

The PLL circuit 16 includes a phase comparator 10, a 400 frequency divider 12, an 8 frequency divider 13, a VCO (voltage controlled oscillation) circuit 14, and a low-pass filter 15. Divider 23
It is composed of four-frequency dividing circuits 17 and 18 and a D flip-flop 19. Video signal 1 corresponding to each pixel of the liquid crystal memory
Is input to the differentiating circuit 2 of the edge detecting circuit 18, and the differentiating circuit 2 outputs a trigger pulse when the video signal 1 rises and falls.

The trigger pulse 3 output from the differentiating circuit 2 is input to a comparator 4, which compares the input voltage of the trigger pulse 3 with a reference voltage and outputs a video signal 1
One-shot pulse 5 in synchronization with rising and falling edges of
Is output. The one-shot pulse 5 is input to a set pulse generation circuit 6, and the set pulse generation circuit 6 synchronizes once every horizontal synchronization period from the output time of the one-shot pulse synchronized with the rising time of the video signal 1 to the falling time. The one-shot set pulse 7 is output at substantially the center of the period up to the output of the one-shot pulse. The set pulse 7 output from the set pulse generation circuit 6 is divided by four in the frequency divider 23.
17,18 Given to each.

On the other hand, an externally input horizontal synchronizing signal 9
Is input to the phase comparator 10 of the PLL circuit 16. The signal output from the phase comparator 10 after phase comparison is a low-pass filter 15.
Is input to a VCO (voltage controlled oscillation) circuit 14 via the. VCO
The reference clock output from the circuit 14 is input to the ８ frequency divider 13 and the ４ frequency divider 17 in the frequency divider 23. The reference clock output from the VCO circuit 14 is input to the ８ frequency divider 13 and the ４ frequency divider 17 in the frequency divider 23. The reference clock output from the divide-by-8 circuit 13 after dividing the input reference clock by 8 is input to the 400-divider circuit 12.

A reference clock f _{H, which} is obtained by dividing the reference clock inputted by the 400 divider circuit 12 by 400, is outputted to the phase comparator 10. The phase comparator 10 phase compares a reference clock f _H of the horizontal synchronizing signal 9 and 400 dividing circuit 12, thereby controlling the oscillation frequency of the reference clock VCO circuit 14 outputs in response to the phase difference I have.

The reference clock 22 output from the divide-by-4 circuit 17 of the divider 23 is output to the clock terminal CLK of the divide-by-4 circuit 18 and the D flip-flop 19. The pixel display clock CKH1 output from the divide-by-4 circuit 18 by dividing the input reference clock by 4 is applied to the D flip-flop 19
And an odd-numbered pixel display position in the horizontal direction of a liquid crystal panel (not shown). The pixel display clock CKH2 output from the output terminal Q of the D flip-flop 19 and having a phase delayed by 90 ° from the pixel display clock CKH1 is supplied to an even-numbered pixel display position in the horizontal direction of the liquid crystal panel (not shown).

Next, the operation of the liquid crystal projection television having the above-described configuration is described by referring to the reference clock output from the PLL circuit 16 and the pixel display clock CKH1, output from the frequency divider 23.
2 showing CKH2 and FIG. 3 showing the pixel display clocks CKH1 and CKH2 output from the frequency divider 23 and the signals of the respective parts in the edge detection circuit 8.

The frequency of the video signal 1 input from the outside is, for example, 25.175 MHz. Now, the frequency is, for example, 31.47k
When Hz of the horizontal synchronization signal 9 is input to the PLL circuit 16, a phase comparator 10 compares the phase of the horizontal synchronizing signal 9, the reference clock f _H input from 400 frequency divider 12 and a phase, the The phase difference signal is applied to the VCO circuit 14 via the low-pass filter 15.
Enter As a result, the frequency of the reference clock output from the VCO circuit 14 is controlled, and the controlled reference clock becomes 8
After being divided by 8 by the frequency divider 13, the frequency is further divided by 40 by the 400 frequency divider 12.
Divided by 0.

[0014] and is inputted to the phase comparator 10 outputs a reference clock f _H of the VCO circuit 14 is 3200 divided frequency of the reference clock output from the 400 divider 12. In this manner, the phase comparator 10 repeats the comparison of the phase of the reference clock f _H of the horizontal synchronizing signal 9. And VCO
The circuit 14 is four times the frequency of the video signal 1 of 25.175 MHz and is 100.
The reference clock shown in FIG. 2 (a) having a frequency of 7 MHz and a duty of 50% is stably output. Arrows shown in FIG. 2A indicate rising edges of the reference clock.

The reference clock output from the VCO circuit 14 is input to a divide-by-4 circuit 17 and divides the frequency by four.
17 is a reference clock 22 with a frequency of 25.175 MHz shown in FIG.
And input it to the clock terminal CLK of the divide-by-4 circuit 18 and the D flip-flop 19. The divide-by-4 circuit 18 is a 4
The reference clock 22 from the frequency divider 17 is further divided by four. As a result, the divide-by-4 circuit 18 outputs the pixel display clock CKH1 as the reference clock shown in FIG. 2C and gives it to the odd-numbered pixel display positions of the liquid crystal panel (not shown).

The D flip-flop 19 captures the data of the pixel display clock CKH1 when the reference clock 22 rises, and outputs the data captured when the reference clock 22 rises next time to the output terminal Q. Output to As a result, the D flip-flop 19 outputs a pixel display clock CKH2 delayed by one cycle of the reference signal 22 from the pixel display clock CKH1 as shown in FIG. . As a result, the pixel display clock CKH
1, Display pixels on the LCD panel according to CKH2.

On the other hand, when a digital video signal 1 shown in FIG. 3A, which is created in synchronization with an analog video signal corresponding to a pixel input from the outside, is input to a differentiating circuit 2,
The differentiating circuit 2 outputs a trigger pulse as shown in FIG. 3B at each rising and falling time of the video signal 1, and inputs the trigger pulse to the comparator 4. Then the comparator 4 compares the voltage with a reference voltage of the trigger pulse generated at the rising time of the video signal 1, and outputs a one-shot pulse P ₁ as shown in FIG. 3 (c) when it exceeds the reference voltage, comparing the voltage with a reference voltage of the trigger pulse generated at the falling time of the video signal 1, and outputs a one-shot pulse P ₂ as shown in FIG. 3 (c) when it exceeds the reference voltage.
Further set pulse generating circuit 6 in substantially the center of the period from the time of outputting the one-shot pulse P ₁ to the point which outputs the one-shot pulse P ₂ outputs a set pulse 7 shown in Figure 3 (d). As a result, the set pulse 7 is synchronized with the time when the voltage of the video signal 1 is stabilized as shown in FIG.

The set pulse 7 output from the set pulse generating circuit 6 is supplied to frequency dividing circuits 17 and 18,
The reference clock from the divide-by-4 circuit 17 input to the divide-by-4 circuit 18 is synchronized with the set pulse 7 as shown in FIG.
The pixel display clock output from the D flip-flop 19
CKH2 is output in synchronization with the pixel display clock CKH1, as shown in FIG.

Therefore, the pixel display clocks CKH1, CKH2
Rises in synchronization with the time point when the voltage level of the video signal 1 is stable, and the video signal 1 and the pixel display clocks CKH1 and CKH2
And always be in sync. Thereby, in synchronization with the point in time when the voltage of the video signal corresponding to each pixel is stable,
Since the pixel display clocks CKH1 and CKH2 rise, no pixel is displayed when the voltage of the video signal is unstable. Even if the rise of the video signal 1 is slowed down, no pixel is displayed during the rise. Therefore, when a video signal corresponding to each pixel is input from a personal computer, which is not a video signal in a television broadcast, for example,
Alternatively, even when the rising of the video signal 1 is slowed down,
An image based on the input video signal is displayed on the liquid crystal panel with a sharp outline. Therefore, computer graphics can be reproduced on the screen with a sharp outline.

In this embodiment, the frequency of the video signal 1 is
25.175MHz and the frequency of horizontal sync signal 9 is 31.47kHz
However, it is an example, and the frequency is not limited in any way. Further, in this embodiment, the liquid crystal projection television has been described, but the invention is not limited thereto.
LCD, TV, LCD, plasma, EL, etc.
Of course, the same effect can be obtained with the display . Further, the video signal input to the edge detection circuit is not limited to a digital video signal, but may be an analog video signal.

[0021]

As described in detail above, the present invention synchronizes the time when the voltage of the video signal corresponding to each pixel is stable with the pixel display clock for displaying the pixel. Therefore, even when video signals having different frequencies are input, the pixel display clock is inverted and the pixels are displayed when the voltage of the video signal is stabilized. Therefore, it is possible to display an image having a sharp outline irrespective of the frequency of a video signal, and to provide an excellent effect of providing a pixel synchronizer capable of reproducing computer graphics by a personal computer with a sharp outline.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main configuration of a pixel synchronizer according to the present invention.

FIG. 2 is a timing chart of a reference clock of a VCO circuit and a pixel display clock.

FIG. 3 is a timing chart of signals of various parts of the edge detection circuit and a pixel display clock.

[Explanation of symbols]

 4 Comparator 6 Set pulse generation circuit 8 Edge detection circuit 10 Phase comparison circuit 12 400 frequency divider 13 8 frequency divider 14 VCO circuit 16 PLL circuit 17,18 4 frequency divider 19 D flip-flop 23 frequency divider

Claims (1)

(57) [Claims] 1. A in synchronization with the input horizontal synchronizing signal thereto divides the reference clock PLL circuit outputs a pixel is to display an image based on a pixel display clock created by dividing synchronously In the apparatus , an edge detection circuit which detects a leading edge of a video signal corresponding to a pixel to be displayed, which is input thereto, and outputs a pulse at a time delayed by a predetermined time from the leading edge detection time, wherein the pulse pixel synchronization apparatus characterized by being configured to synchronize with the pixel display clock and the video signal by.