JPS63142455A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To simplify memory management and quickly transfer data by managing information bits of a mask register by a MPU. CONSTITUTION:A dual port memory circuit which can be arbitrarily accessed by processors MPUa and MPUb through two signal paths and has plural storage areas is provided with an occupation register R3 and a release register R4 which indicate the occupation and release of each storage area respectively, an interruption source register R2, and an interruption mask register R1. An interruption request signal is generated in accordance with corresponding information bits of the interruption source register R2 and the interruption mask register R1, and information bits of the interruption source register R1 which refer to an interruption mask signal are taken out correspondingly to this interruption request signal.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device, for example, a dual port RAM (random RAM) that can be accessed arbitrarily by two processors via two signal paths.・It relates to effective technology that can be used for (access/memory).

[Conventional technology]

In a multiprocessor system that operates asynchronously with each other, a dual port RAM (hereinafter referred to as a DRAM in a car) that can be accessed arbitrarily by both microprocessors is used for data communication between the two microprocessors.
It is called P-RAM.

) is provided. This dual port RAM has a function of generating an interrupt to one processor based on a request from the other processor.

An example of generating an interrupt in a dual port RAM is, for example, the United States' Ingrated Device Technology Inc.
Grated Device Technology
There is a method developed by nc, ). Figure 3 shows
Product name from the company: ID T7130S/ID
T7130L CMOS DUAL PORT
This is an interrupt control circuit in a dual port RAM commercially available as RAM8K (IKX8BIT)J. The figure was created according to the functions described in the data book. In the figure, for example, when processor MPUa interrupts processor MPUb, processor MPUa
It is generated by performing a write operation to the RAM address "3FE" (in hexadecimal notation; the same applies hereinafter). That is, the control circuit CTL of the dual boat RAM monitors the address signals supplied from both processors MPUa and MPUb, and when the processor MPUa writes the status such as the cause of an interrupt to the address @3FF'' of the memory circuit RAM. , and generates the signal wa.As a result, the flip-flop FFb for interrupt display is set, and the interrupt request signal I is sent to the processor MPUb.
RQb is output. When processor MPUb accepts the interrupt request, processor MPUb writes the address "
3FE" interrupt status is read.

The control circuit CTL thereby forms a signal rb and resets the interrupt display flip-flop FFb. Such an operation also occurs when processor MPUb interrupts processor MPUa at address “3F
The same is done via F''.

[Problem that the invention seeks to solve]

As mentioned above, in P-RAM, it is necessary to exchange address information for specifying the memory area where the data to be transmitted is stored and additional information such as the number of data.
Management of the memory area becomes complicated. Therefore,
The inventors of the present invention have considered dividing a memory space into a plurality of memory areas, and writing data to be transmitted using each memory area as a unit. This makes it easy to manage memory areas.

However, in this case, it is necessary to sequentially check which memory area among the plurality of memory areas divided in the processor that received the interrupt stores the data that caused the interrupt.

An object of the present invention is to provide a semiconductor memory device that simplifies memory management and speeds up data transfer.

The above and other objects and novel features of this invention include:
It will become clear from the description of this document 1i[11g and the accompanying drawings.

[Means for solving problems]

A brief summary of typical inventions disclosed in this application is as follows. That is,
A dual-port computer with a small storage area (both of which can be arbitrarily accessed by two processors, and has multiple storage areas configured by dividing them) through two signal paths.
In the memory circuit, an occupancy register and a release register each having information bits instructing the occupation and release of each of the divided storage areas, respectively, and an interrupt information bit is formed from each information bit of the occupancy register and the release register. An interrupt source register and an interrupt mask register having information bits for controlling the mask are provided,
An interrupt request signal is generated from the corresponding information bits of the interrupt source register and the interrupt mask register, and in response to the interrupt request signal, the information bits of the interrupt source register are taken out with reference to the interrupt mask signal.

[For production]

According to the above-mentioned means, the information bits of the mask register are managed by the MPU, so that the information bits of the interrupt source register that are not masked can be quickly found. In other words, the memory area that caused the interrupt can be quickly searched. It can be carried out.

〔Example〕

FIG. 1 shows a block diagram of an embodiment in which the present invention is applied to a dual port RAM. Each circuit block in the figure is formed on a single semiconductor substrate, such as single crystal silicon, by a known semiconductor integrated circuit manufacturing technique.

The dual boat RAM in this embodiment is connected to two microprocessors MPUa and MPUb via two left and right buses (signal paths). The memory circuit in this dual boat RAM has the following memory array M-ARY.The memory array M-ARY is not particularly limited, but is connected to each processor MPUa, MPU
Two sets of address decoders and column switches are provided corresponding to b. That is, the X address signal AXa supplied from one microprocessor MPUa is sent to the X decoder XDCR via an address buffer (not shown).
A is supplied to the input terminal of A.

This X decoder XDCRA receives the address signal AXa.
is decoded to form a selection signal for a corresponding one word line of memory array M-ARY. The X address signal AXb supplied from the other microprocessor MPUb is sent to the X decoder XDCR via an address buffer (not shown).
It is coupled to the input terminal of B. This X decoder XDCRB
decodes the address signal AXb and forms a selection signal for each word line of memory array M-ARY.

Similarly, the selection terminal of the column switch CWA to which the data line of the memory array M-ARY is coupled is coupled to the output terminal of the Y decoder YDCRA that decodes the Y address signal AYa from the microprocessor MPUa.
The selection terminal of the column switch CWB to which the data line is coupled is coupled to the output terminal of a Y decoder YDCRB that decodes the Y address signal AYb from the microprocessor MPUb.

Column switch CWA connects the data line of memory array M-ARY specified by Y address signal AYa to a common data line pair. The common data line is connected to an external data bus Da via a data buffer DBA.

The data buffer DBA sends read data from a selected memory cell of the memory array M-ARY to the data bus Da in a read mode, and sends write data supplied via the data bus Da to the memory array M-ARY in a write operation. ARY to the selected memory cell. The operation of the peripheral circuit of such memory array M-ARY is as follows.
The same process is performed for the X decoder XDCRB, Y decoder YDCRB, column switch CWB, and data buffer DBB provided corresponding to the microprocessor MPUb.

In this embodiment, the address space of the memory array M-ARY is divided into eight memory blocks (memory areas) MO to M7, although this is not particularly limited. Each of these memory blocks MO to M7 is provided with an interrupt factor. In other words, writing/reading is performed in accordance with the type of data to be transmitted from both processors MPUa and MPUb using the memory blocks MO to M7 as units.

The control circuit CTL is connected to each microprocessor MP.
Selection signal C3aSC3b supplied from Ua and MPUb
, and form various internal operation mode signals and timing signals based on the write enable signals WEa and WEb.

In addition, each of the above address buses AXa, AYa, AX
In response to address signals and data signals supplied from data buses Da, AYb and data buses Da and Db, register selection and write/read control, etc., as described later, are performed. Further, the control circuit CT L includes a logic circuit ABT, which controls generation of an interrupt request signal and reception of a selection signal from the information bits of the register REG.

The register REG is composed of, but not limited to, an interrupt mask register R1, an interrupt source register R2, an occupation register R3, and a release register R4.

Each bit (bit O to bit 7) of each of these registers R1 to R4 has an information bit corresponding to the divided memory blocks MO to M7, respectively.

FIG. 2 shows the information bit configuration of the registers R1 to R4 and a circuit diagram of the interrupt generation circuit included in the logic circuit ABT.

The release register R4 and the occupation register R3 are used as a so-called semaphore to mutually exclude simultaneous accesses to the same memory plotter (memory area) by the two microprocessors MPUa and MPUb. For example, when writing data from the microprocessor MPU a to the memory block MO, on the condition that the information bit LBO of the release register R4 is logic "1", the logic "
1” can be written, and at the same time the information bit of the release register R4 changes from logic “1” to logic “0”.
”.As a result, while the microprocessor MPUa is accessing the memory block MO, the other microprocessor MPUb
Access to the memory block MO is prohibited.

The above microprocessor MPUa is the memory block MO
When the access to the microprocessor M is completed, the microprocessor M
PUa writes logic "1" to the information bit LBO of the release register R4. This makes the occupied register R
The corresponding information focus TBO of No. 3 is automatically rewritten from logic "1" to logic "0".

The interrupt source register R2 is the release register R4.
logic “ depending on the write to a specific information bit for
1" is set to generate an interrupt factor. In this embodiment, each of the eight memory blocks MO to M7 is configured to have an interrupt factor, so a mask bit is added to each. That is, The interrupt mask register R1 is the memory block MO
In other words, information bits RQO to RQ7 of interrupt source register R2
It has mask bits ENO and EN7 corresponding to .

Therefore, the interrupt generation circuit included in the logic circuit ABT is an AND gate circuit GO or an AND gate circuit receiving each of the information bits RQO to RQ7 of the interrupt source register R2 and the corresponding information bits ENO to EN7 of the interrupt mask register R1, respectively. G7 and a NOR gate circuit G8 which receives the output signals of these AND gate circuits Go through G7, and generates one interrupt request signal IRQ. Note that the interrupt request signal IRQ is transmitted to the other microprocessor according to stored information (not shown) indicating from which microprocessor MPUa or MPUb the interrupt request was made, corresponding to each information bit of the release register R4. The operation of this embodiment of the interrupt request body supplied to processor MPUb or MPUa will now be described.

For example, when transmitting data from the microprocessor MPUa to the microprocessor MPUb, the microprocessor MPUa sets the chip selection signal C3a to a low level and accesses the dual port RAM. If the memory block used to write the data to be transmitted is M5, refer to the information bit RQ5 of the corresponding interrupt source register R2, and set the logic to “1”.
', and the corresponding information bit LB5 of the release register R4 is logic "1", the occupied register R
Logic "1" is written to the information bit TB5 of No.3. This enables writing to memory block M5. As mentioned above, by writing the logic "1" to the information bit TB5 of the occupied register R3, the logic "1" is automatically written to the information bit LB5 of the release register R4.
O" is written. As a result, while the microprocessor MPUa is writing the above data, access from the other microprocessor MPUb to the same memory block M5 is prohibited.

The reason why the information bit of the interrupt source register R2 is referred to is as follows. For example, the corresponding information bit EN5 of the interrupt mask register R1 is set to logic "θ'"
(Masked state B), the interrupt request signal TRQ is not output, the corresponding memory block enters a read waiting state from the other MPU after writing is completed, and data previously written to memory block M5 cannot be received. This is because the data has not been passed yet, so if the above write is performed, the data will be destroyed.

When the microprocessor MPUa finishes writing the data to be transmitted to the memory block M5, it sets the information bit in the release register R4 and sets the logic "I" in B5.
" is written. As a result, the information bit TB5 of the occupancy register R3 is automatically rewritten from logic "1" to logic "O".

Logic °1 to information bit LB5 of the above release register R4
By writing ", logic "1" is written to the information bit RQ5 of the interrupt source register R2. In response, the information bit E of the interrupt mask register R1 is written to the information bit RQ5 of the interrupt source register R2.
If N5 is logic "1", an interrupt request signal IRQb is generated for the other microprocessor MPUb. If the microprocessor CPυb is performing information processing with a higher priority than the data transfer operation using the memory block M5, the microprocessor MPUb will process the information in the interrupt mask register R1.
By writing logic “0” to EN5 and leaving it as is,
Generation of the interrupt request signal IRQb can be prohibited.

゛When the interrupt request signal IRQb is generated by writing the mask bit EN5 to logic "1" in the microprocessor MPLib or by setting the mask bit EN5 to logic "1" as described above, the microprocessor MPUb refers to each information bit of the interrupt mask register R1 and sequentially reads out the information bits of the interrupt source register R2 corresponding to the information bits set to logic "1". By this reading, reading from the memory block M5 corresponding to the information bit to which logic "1" is written can be performed at high speed. That is, for example, when reading information bits RQO of interrupt source register R2 sequentially, the reading of the information bits of interrupt source register R2 corresponding to the information bits to which logic "0" is written in interrupt mask register R1 is skipped and the next step is performed. This is because information bits can be read.

The microprocessor MPUb has the memory block M
When the read operation for 5 is completed, logic "0" is written to the information bit RQ5 of the interrupt source register R2 to reset the interrupt cause.

This also applies to data transfer operations using other memory blocks. Also, microprocessor M
The same applies when data is transferred from PUb to microprocessor MPUa.

In this embodiment, as described above, the memory space in the DP-RAM is divided into a plurality of memory blocks, an interrupt factor is given to each block, and an occupation/release register having an information focus corresponding to each memory block is used. By providing an interrupt source/mask register, the memory area can be easily managed, and when an interrupt is accepted, the data that caused the interrupt can be transferred, or in other words, the memory block can be read out at high speed. becomes.

The effects obtained from the above examples are as follows. In other words, each of the divided storage areas is made into a dual-port memory circuit having a plurality of storage areas that are each divided and made arbitrarily accessible by at least two processors through <1 signal path. Occupation/release registers each having information bits that instruct their occupation/release, an interrupt source register that forms interrupt information bits from the information bits of the aforementioned occupation registers and release registers, and information bits for mask control thereof. By providing an interrupt mask register having a function, the memory area used for data transfer can be managed from each information bit, so that the effect of simplifying the management of the memory area can be obtained.

(2) Generate an interrupt request signal from the corresponding information bits of the interrupt source register and interrupt mask register, and extract the information bits of the interrupt source register that refer to the interrupt mask signal in response to the interrupt request signal. This has the effect that by referring to the information bits of the mask register, the information focus of the unmasked interrupt source register can be quickly found, or in other words, the memory area that caused the interrupt can be searched at high speed. is obtained.

(3) By providing a w-information bit in the interrupt source register and interrupt mask register for each memory block, each interrupt factor can be selectively masked. As a result, priority can be set according to the urgency (urgency) of data transfer, and a rational data transfer operation is possible.

Hereinafter, the invention made by the present inventor has been specifically explained based on examples, but this invention is not limited to the above-mentioned examples, and various changes can be made without departing from the gist thereof. Needless to say. For example, each register R1 to R4 may be provided corresponding to each microprocessor. Further, various additional functions may be added, such as providing a word register corresponding to each memory block to store the number of transferred words when reading each memory block.

Further, the X address signal and the Y address signal may be supplied through a common signal line by a multiplex method. Furthermore, the address signal and the data signal may be transmitted using a multiplex method.

The above explanation has mainly been about the application of the invention made by the present inventor to dual port RAM in a multiprocessor system, which is the background field of application, but the present invention is not limited to this, for example. , a dual port RAM installed between a host computer and an intelligent terminal device having a processor.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. In other words, each of the above-mentioned divided sections is connected to a dual-port memory circuit having a plurality of storage areas, each of which can be arbitrarily accessed by two processors, by two signal paths. Occupation registers and release registers each having information bits for instructing the occupation and release of storage areas, an interrupt source register for forming interrupt information bits from the information bits of the aforementioned occupation registers and release registers, and mask control thereof. An interrupt mask register having information bits is provided to generate an interrupt request signal from the corresponding information bits of the interrupt source register and the interrupt mask register, and refer to the interrupt mask signal corresponding to the interrupt request signal. By extracting the information bits of the interrupted interrupt source register, memory area management becomes easy, and by referring to the information bits of the mask register, the memory area that caused the interrupt can be searched at high speed.

[Brief explanation of the drawing]

Figure 1 shows a dual boat R to which this invention is applied.
FIG. 2 is a block diagram showing an example of an AM. FIG. 2 is a circuit diagram of the information bit configuration and interrupt request signal generation circuit corresponding to each register, and FIG. 3 is a block diagram of a conventional dual port. FIG. 2 is a circuit diagram showing an example of a control circuit of a RAM. M-ARY...Memory array, XDCRA, XDCRB
・・X decoder, YDCRA, YDCRB・・Y decoder, CWA, CWB・・Column switch, DBA, D
BB...Data buffer, CTL...Control circuit, ABT
・Logic circuit, R1 ・Interrupt mask register, R2
...Interrupt source register, R3...Occupied register,
R4...Release register, Go-G7...AND gate circuit, G8...Nor gate circuit, MPUa, MPUb...
Microprocessor diagram 1

Claims (1)

[Claims] 1. A dual port memory circuit having a plurality of divided storage areas which can be arbitrarily accessed by at least two processors through two signal paths; an occupancy register and a release register having information bits for instructing the occupancy and release of each storage area corresponding to each storage area; and an interrupt source register and its mask that form interrupt information bits from the information bits of the occupancy register and the release register. an interrupt mask register with information bits for control;
an interrupt generation circuit that generates an interrupt request signal from the corresponding information bits of the interrupt source register and the interrupt mask register; A semiconductor memory device characterized in that it can be taken out. 2. The above-mentioned interrupt generation circuit has a plurality of AND gate circuits each receiving corresponding information bits of the interrupt source register and interrupt mask register, and one OR gate circuit receiving output signals from the plurality of AND gate circuits. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device generates an interrupt request signal.