JPS59206972A - Shared memory - Google Patents

Abstract

PURPOSE:To eliminate interruption of processors at the time of data transfer between processors by providing plural write-only memories in the input port of a public memory and plural read-only memories in the output port. CONSTITUTION:Write-only memories 51, 52 that write data from a processor 10 are provided in the input port of a shared memory 100, and read-only memories 61, 62 that read data to processors 21-2N are provided in output ports. Gates 81, 82 that determine transfer mode of data are provided in an A port 100A and a B port 100B. The gate 81 is connected to a change-over signal generating circuit 86, and the gate 82 is connected to a mode changing signal generating circuit 86 through a controlling line 84 and an invertor 85 for inverting signals. By this way, transfer mode of the A port 100A and B port 100B become reverse.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a shared memory, and more particularly to a shared memory used for data transfer between a plurality of processes operating asynchronously in a distributed processing system.

[Technical review of the invention]

Conventionally, when data is transferred from one of multiple processors operating asynchronously to any N processors in a distributed processing system, one or N memories are installed as shared memory between the processors, and this is transferred between the processors. Data was transferred as an intermediary.

FIG. 1 is a diagram showing a conventional configuration between processors when one memory is used as a shared memory. In the same figure, the processor 10 is connected to the memory 30 via the node 41, and is connected to the memory 30 through the node 41, and is connected to the memory 30 through the node 41, and stores arbitrary N gross data. ...
, 2N (however, N=1.2, 3...) is path 42
It is connected to the memory 30 via. That is, in this case, data from the processor 10 is partially written into the memory 30 via the arm 41 and transferred to the processors 21 to 2N via the arm 42.

Next, FIG. 2 is a diagram showing a conventional configuration between processors when N memories are used as shared memories, in which the same parts as in FIG. 1 are given the same reference numerals. In this case, the processor 10 sends N notes IJ s via a path 41.
1. s2. ....

The processors 21 to 2N are connected to the memories 31 to 3N via paths 42, respectively.

Therefore, in this case, data from the processor 10 is partially written into the memories 31'-3N via the path 41, and transferred to the processors 21-2N via the path 42.

[Problems with background technology]

However, when data is transferred between processors using one or N memories as a shared memory, the following problems occur. That is, when one memory is used as a shared memory, while the processor 10 is writing data to the memory 30, the processors 21 to 21
2N cannot read data from memory 30, and while processors 21-2N are reading data from memory 30, processor 10 cannot write data to memory 30. Similarly, when N memories are used, the processors 21 to 2N cannot read data to the memories 31 to 3N while the processor 10 is writing data to the memories 31 to 3N. While processor 2N was reading data from memories 31-3N, processor 10 could not write data to memories 31-3N.

Therefore, conventionally, when one processor is accessing (writing or reading data), the other processor cannot access the memory.
Processing must be interrupted until access by one processor is completed, and it cannot be applied to the field of real-time processing.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and its purpose is to prevent the processing of each processor from being interrupted when data is transferred from one of a plurality of processors operating asynchronously to N processors. There is no shared memory to provide.

[Summary of the invention]

In order to achieve the above object, the present invention is characterized by having the following configuration. That is, the shared memory of the present invention has an input port that receives data from one of a plurality of processors that operate asynchronously, and an output that transfers the data input to this input port to any N of the processors. - the input state includes a plurality of write-only memories for selectively writing data to the processor, and the output state includes a plurality of write-only memories for selectively writing data to the processor. The configuration is such that each device is equipped with a read-only memory.

[Embodiments of the invention]

Hereinafter, the present invention will be described in detail based on embodiments shown in the drawings.

3 and 4 are diagrams each showing an embodiment of the present invention, and FIG. 3 is a diagram showing a configuration between processors when shared memory is used as an embodiment of the present invention. Figure 4 is a diagram showing the configuration of the shared memory. In each figure, the same parts as in FIG. 1 are given the same reference numerals.

In Figures 3 and 4, Zorose, Su10 is path 41
The processors 21 to 2N are connected to the N output ports 100b of the shared memory 100 via paths 42, respectively. The input capacity of this shared memory 100) 100
As shown in FIG.
Each output port 100b of 00 has processors 21 to 2N.
First and second read-only memories (hereinafter referred to as ROMs) 61 and 62 are provided for reading data into the memory.

The WOM 51 of this human powered vehicle 100h is connected to the ROM 61 of each output port 100b via a path 21A, and the WOM 52 is connected to each output port 100 via a path 7JB.
It is connected to the ROM 62 of 0b.

In addition, WOM 51, ROM 61 and WOM 52
and 6-ROM 62 form an A port 100A and a B port 1ooB, respectively. This A port 100A and B
For the date 1ooB, darts 81.82 for determining the data transfer mode are provided on each bus 41.42 and 711.71B.

The gate 81 is connected to a mode switching signal generation circuit 86 via a control a83, and the dart 82 is connected to the mode switching signal generation circuit 86 via a control line 84 and an inverter 85 for signal inversion. Therefore, the open/close states of the darts are reversed between the gates 81 and 82, and the transfer modes of the A port 100A and the B port 100B are reversed due to the crack.

Next, the operation will be explained. FIG. 5 is a timing chart showing the operation of the shared memory of the present invention.
m 1θ2 is A port 100A and B of shared memory 1θθ
Indicates the transfer mode of port 1ooB, and indicates the low-level sections tehafuo*yt10, 21~
This is an access mode that allows access (data writing and reading) from 2N, and prohibits access from processors 10.21 to 2N in the section where the level is high.
This is a copy mode in which all bits of data written in the OMs 51 and 52 are transferred to the ROMs 61 and 62. Note that 1o3 indicates the write timing of the processors 1o, and 104 and 105 indicate the read timings of the processors 21 to 2N.

As shown in the figure, A port 10oAI! :B port 1
The access mode of 00B is the mode switching signal generation circuit 86.
They are periodically and alternately switched by a switching signal (not shown) generated by. Therefore, the write timing 103 of the processor 1o is, for example, the A port 1o as shown in the figure.
If oA were to operate in access mode, data from processor 10 would be written to WOM 51;
The data is transferred to the ROM 61 during the next copy mode period. Here, even if data is read from one of the processors 21 to 2N while the A port JooA is in the copy mode, the data can be read because the B port 1ooB is in the access mode. Note that the data read here is the data stored in the ROM 62, and is the data previously written into the WOM 52. Therefore, the data transferred to the ROM 61 can be read from the ROM 61 after the next access mode with a one-cycle delay. Also,! processor 10 and processors 21-2
Even if there is access from port N at the same time, each port 1
00IL.

J 00BCI WOM51.52 and ROM 61
.

62 can be dealt with simultaneously.

In this way, according to this embodiment, A port 1ooA and B/
Since either one of - and
Even if access is made from both N processors, one processor is not placed in a waiting state, so real-time processing is possible.

Note that in the above embodiment, there are two WOMs 51, 5! for access from the processor. Although data is written and read using the ROMs 61 and 62, the same effect can be obtained using two or more.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, it operates asynchronously! It has an input port that receives data from one of the jI number of processors, and N output ports that transfer the data input to this input port to any N of said processors, and the input port receives data from one of the processors. Equipped with multiple write-only memories for selectively writing data, output, j? -) has a configuration including a plurality of read-only memories that selectively read data to the processor, so that any N processors from one of the plurality of processors operating asynchronously can be used.

It is possible to provide a shared memory without interrupting the processing of each processor when transferring data.

[Brief explanation of drawings]

Figures 1 and 2 are configuration diagrams between processors when conventional shared memory is used. Figure 1 is a configuration diagram showing the case where one memory is used as shared memory, and Figure 2 is FIGS. 3 to 5 are diagrams showing an embodiment of the present invention, and FIG. 3 is a block diagram showing a case where two memories are used as a shared memory. FIG. 4 is a block diagram of a shared memory according to an embodiment of the present invention, and FIG. 5 is a timing diagram showing the operation of the shared memory. 10.21~2N...Processor, 51.52-WO
M, 61, 62-ROM, 100a''-Manual date, 100b...Output port. Applicant's agent Patent attorney Takehiko Suzue 11- Fig. 1 0 Fig. 3 00 N

Claims (1)

[Claims] An input, f?, that receives data from one of multiple processors operating asynchronously. -) and an output port that transfers the data input to the input port to any N of the processors, and the input port has a plurality of N processors that selectively write data from the processor. A shared memory comprising: a write-only memory, and each of the output ports comprising a plurality of read-only memories for selectively reading data to a processor.