JPH08235054A - Shared memory - Google Patents

Abstract

PURPOSE: To provide a shared memory which can receive accesses from the data processing units with no use of an arbiter. CONSTITUTION: A memory area which is shared by two data processing units 2 and 3 consists of the memories 8 and 9. In such a constitution of a shared memory, at least a single memory block of both memories 6 and 9 is set in a read or write state by the OR logic circuits 10 and 11 against only one of both units 2 and 3 in response to the read/write signal that is outputted from the unit 2 or 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shared memory in which one memory can be accessed, that is, shared by a plurality of data processing units.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing a conventional shared memory. The data processing unit 2, the data processing unit 3, and the memory 4 are connected to the arbiter 1 that arbitrates the access source to the memory via one via each of the buses 5a, 5b, and 5c. That is, data transmission among the data processing unit 2, the data processing unit 3, and the memory 4 is always performed via the arbiter 1. The buses 5a, 5b and 5c are each composed of an address bus, a data bus and a control bus.

In this configuration, the data processing unit 2
When the memory 4 accesses the memory 4, the arbiter 1 performs bus arbitration, then disables access to the bus 5b, and enables access from the data processing unit 2 to the memory 4 via the buses 5a and 5c. When accessing the memory 4 from the data processing unit 3, the arbiter 1 performs bus arbitration to disable access to the bus 5a, and then the data processing unit 2 transfers data from the data processing unit 2 to the memory 4 via the buses 5b and 5c. Allow access.
As described above, the memory 4 can be shared by the data processing units 2 and 3.

[0004]

However, in the above-mentioned prior art, when the memory is shared by a plurality of data processing units, it is necessary to pass the arbiter without fail, which increases the circuit scale and the development cost. There is the problem of becoming expensive. Therefore, an object of the present invention is to provide a shared memory that does not require an arbiter at the time of access.

Another object of the present invention is to provide a shared memory capable of simultaneous writing and reading from each data processing unit.

[0006]

In order to achieve the above object, the present invention provides a shared memory in which one memory area shared by two data processing units comprises a plurality of memory blocks. Depending on the read / write signal output from the processing unit,
Only one of the data processing units is provided with logic means for putting at least one of the plurality of memory blocks into a read or write state.

Further, a buffer capable of individually blocking the address bus and the data bus may be provided in the middle of each of the address bus and the data bus connected to each of the data processing units and each of the memory blocks. .

[0008]

According to the above means, when the read signal is sent from one of the two data processing units, the logic of the read / write signal of the other data processing unit is determined based on this signal, and the read request is issued. According to
Only one memory block is selected, and access is possible from the data processing unit that has issued a read request to this memory block. As a result, a shared memory that does not overwrite can be constructed without using an arbiter. Moreover, the development cost can be reduced.

Further, a buffer is provided in the middle of each of the address bus and the data bus which connect each of the data processing units and each of the memories, and each of the plurality of buffers has a predetermined combination corresponding to writing and reading. By turning on or off, each memory can be associated with each data processing unit. This enables simultaneous writing and simultaneous reading from each of the data processing units without using an arbiter while reducing the circuit scale and development cost.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. [Embodiment 1] FIG. 1 is a block diagram showing an embodiment of a shared memory according to the present invention. The data processing unit 2 and the data processing unit 3 are connected by an address bus 6 and a data bus 7, and memories 8 and 9 are connected to the address bus 6 and the data bus 7. Further, each chip select terminal of each of the memories 8 and 9 (which is a memory block that constitutes one memory area by one or more memory chips, but is simply referred to as a memory here) serves as a logical means. OR logic circuit 10, 1
Each of the output terminals 1 is connected.

One input terminal of the OR logic circuit 10 is connected to the R / W (bar) terminal (read / write terminal) of the data processing unit 2, and the other input terminal is the R / W (bar) of the data processing unit 3. ) Is connected to the terminal. Similarly, one input terminal of the OR logic circuit 11 is connected to the R / W (bar) terminal of the data processing unit 2, and the other input terminal is the R / W of the data processing unit 3.
It is connected to the (bar) terminal.

In the above configuration, for example, when the data processing unit 2 performs memory reading, its R / W
The output signal of the (bar) terminal becomes "H" level, the chip select signal 12 output from the OR logic circuit 10 becomes "H" level, the memory 8 is selected, and the data processing unit 2 reads it. . At this time, since the input terminal of the OR logic circuit 11 connected to the R / W (bar) terminal of the data processing unit 2 is inverting the signal, the output of the chip select signal 13 is at "L" level. , The memory 9 is not selected.

On the other hand, when the data processing unit 2 performs memory writing, the output signal of its R / W (bar) terminal becomes "L" level. As a result, the OR logic circuit 1
The chip select signal 12 of 0 becomes "L" level, and O
The chip select signal 13 of the R logic circuit 11 is "H"
Become a level. As a result, the memory 9 is selected and writing is performed by the data processing unit 2.

As described above, the OR logic circuits 10 and 1
By performing the chip select using 1, the memory can be accessed without using the arbiter.
As a result of eliminating the need for an arbiter, development costs can be reduced. Further, since the data written by one data processing unit is not overwritten by the other data processing unit, it is possible to prevent a failure at the time of exchanging messages between the data processing units.

[Second Embodiment] FIG. 2 is a block diagram showing another embodiment of the shared memory according to the present invention. In FIG. 2, the same reference numerals are used for the same members as those used in FIG. The embodiment shown in FIG. 1 has the advantage of not requiring an arbiter, but because the data processing unit shares the address and data buses,
There is a drawback in that the memory cannot be accessed from multiple data processing units at the same time. The embodiment shown in FIG. 2 has improved this drawback.

As shown in FIG. 2, the data processing unit 2
Two buffers 15 and 16 are connected to the address bus 14 of the data processing unit 2 and the data bus 17 of the data processing unit 2.
Two buffers 18 and 19 are connected to. Further, two buffers 21 and 22 are connected to the address bus 20 of the data processing unit 3 and the unit 3
Two buffers 24 and 25 are connected to the data bus 23 of FIG.

The buffer 15 and the buffer 21 are connected by an address bus 26a, the buffer 16 and the buffer 22 are connected by an address bus 26b, and the address terminal of the memory 8 is connected to the address bus 26. The buffer 18 and the buffer 25 are connected by a data bus 27, and the data input / output terminal of the memory 9 is connected to the data bus 27. Further, the buffer 19 and the buffer 24 are connected by a data bus 28, and the data input / output terminal of the memory 8 is connected to the data bus 28.

FIG. 3 shows the logic showing the operation of each buffer when two data processing units access the memory. According to the reading / writing of the data processing unit 2 and the data processing unit 3, the eight buffers are turned on (ON) / off (OF) according to the combination shown in FIG.
F) is carried out. This on / off control is performed by C (not shown).
It is done by the PU. First, when the data processing unit 2 performs a memory read, as described above, the output signal of the R / W (bar) terminal becomes "H" level, the chip select signal 12 becomes "H" level, and the chip select signal becomes 13 becomes "L" level, the memory 8 is selected and the memory 9 is deselected.

At this time, as shown in FIG.
And the buffer 18 is turned off and the buffer 16 and the buffer 19 are turned on (in this case, the buffers 21 to 2).
5 are all turned off, or only buffers 22 and 24 are turned off). With this setting, the data processing unit 2 can read data from the memory 8.

On the other hand, in the case of writing by the data processing unit 2, the output signal of the R / W (bar) terminal becomes "L" level, the chip select signal 12 becomes "L" level and the chip select signal 13 becomes "L". Since it becomes the "H" level, the memory 9 is selected and the memory 8 is unselected. In this mode, as shown in FIG.
5, 18 are turned on and buffers 16, 19 are turned off. This allows the data processing unit 2 to write to the memory 9.

As is apparent from FIG. 3, since the buffers 16 and 19 are on in the read mode of the data processing unit 2, the memory 8 is used for reading, and the buffers 15 and 18 are on in the write mode. The memory 9 is used for writing. On the contrary, in the data processing unit 3, the memory 9 is used for reading and the memory 8 is used.
Is used for writing.

This read / write setting can be performed only by reversing ON / OFF of each buffer, and the memory 8 can be written in and the memory 9 can be read in the data processing unit 2. Similarly, for the data processing unit 3, the memory 8 can be read and the memory 9 can be written. However, both the data processing units 2 and 3 cannot share one memory with the same usage content. If this is allowed, the data will be erased because the other data processing unit overwrites it.

However, in order to avoid the interference between the data processing unit 2 and the data processing unit 3 and the simultaneous stoppage of the functions of the memories 8 and 9, the buffer 15, the buffer 21, and the buffer 18 are provided.
It is necessary to avoid the control of turning on the buffer 25, the buffer 19 and the buffer 24 at the same time, or turning them off at the same time. According to the embodiment shown in FIG. 2, the arbiter is not required and the data written by one data processing unit is not overwritten by the other data processing unit. Obstacles can be prevented. Further, the response message can be written in the address from which the message has been read out, and the software processing can be reduced. Furthermore, when accessing the shared memory, writing and reading can be performed simultaneously from the two data processing units.

In the above embodiments, the number of memories is two, but the number of memories is not limited to this.
It can be any number of memories. In this case, the chip select means and the buffer control means are added according to the number of memories.

[0025]

As described above, according to the present invention, one memory block is set to the read or write state for only one data processing unit according to the read / write signal output from the data processing unit. Therefore, it is possible to construct a shared memory without overwriting without using an arbiter and to reduce the development cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a shared memory according to the present invention.

FIG. 2 is a block diagram showing another embodiment of a shared memory according to the present invention.

FIG. 3 is a logic table showing an operation of a buffer when a data processing unit accesses a memory.

FIG. 4 is a block diagram showing a conventional shared memory.

[Explanation of symbols]

 2, 3 Data processing unit 8, 9 Memory 10, 11 OR logic circuit 14, 20, 26a, 26b Address bus 17, 23, 27, 28 Data bus

Claims (2)

[Claims] 1. A shared memory in which one memory area shared by two data processing units is composed of a plurality of memory blocks, wherein one of the data is responsive to a read / write signal output from the data processing unit. A shared memory, characterized in that it comprises a logic means for putting at least one of the plurality of memory blocks into a read or write state only for the processing unit. 2. A buffer capable of individually shutting off the address bus and the data bus is provided in the middle of each of the address bus and the data bus connected to each of the data processing units and each of the memory blocks. The shared memory according to claim 1, wherein: