JPS635460A - Parallel computer - Google Patents

Abstract

PURPOSE:To eliminate an access competition on a network and to reduce the deterioration in a processing speed by making the respective buffer memories for plural computers a shared memory and providing an effectiveness/ ineffectiveness flag and a copy presence/absence flag. CONSTITUTION:There are provided buffer memories BM21, 22,... which can be used as the shared memory in the computers 1, 2,... and connected by the network 60. With respect to the contents of the respective BMs, the effectiveness/ineffectiveness flags 41, 42,... and the copy presence and absence flags 31, 32,... from other computer are provided and the respective BMs are used as the shared memory by control circuits 11, 12,.... When the effectiveness/ ineffectiveness flag is effective, the data of one's own BM is directly read and when other computer does not copy the data of one's own BM, it is directly written. Thereby, the access competition of the reading and the writing in the respective BMs is removed.

Description

[Detailed description of the invention] [Required] The buffer memory of each of a plurality of computers is shared memory,
A valid/invalid flag indicating whether the contents of these buffer memories are valid or invalid and a copy presence/absence flag indicating whether the contents have been copied from another computer are provided, and when the valid/invalid flag is valid, the data is not passed through the network. By reading directly from the own breadthreader memory, access conflicts on the network are eliminated, and when the copy presence/absence flag is set to "no copy", since the buffer memory of another computer does not hold data at the same address, the own breadthreader By writing directly to memory, access contention on the network is eliminated, reducing opportunities for access contention and decreasing processing speed due to access contention.

[Industrial application field]

The present invention relates to a parallel computer with a shared memory configuration.

The purpose of parallel computers is to obtain faster processing performance than a single computer by dividing the processing of one large piece of data into multiple parts and processing them in parallel by multiple computers.

When multiple computers perform processing in parallel, it is necessary to perform intercomputer communication such as sending and receiving data between the computers, but this intercomputer communication generally uses shared memory (memory that can be accessed by multiple computers). It is done using

Since each computer operates independently, accesses to the shared memory may compete, and in this case arbitration (ordering) is required, which can result in extremely slow access speeds.

As a result, the overhead for arbitration of inter-computer communication increases, resulting in a decrease in processing speed.

Therefore, it is desired to provide a parallel computer with a shared memory configuration that has low overhead due to access contention.

[Conventional technology]

As a conventional example, see rBr on page 505 of the following document.

There is a method that has been introduced as the adcast WriteJ method, which will be explained using figures.

rcache MemoriesJ Alan Jay Sm1th Source rACM Computing 5urvey
s Vol. 14 No. 3 1982" FIG. 5 is a block diagram of a conventional parallel computer.

In the figure, 1 2.3 is a computer (calculator), 11',
12°, 13° are control circuits, 21, 22°, 23 are buffer memories, 41 42. 43 are valid/invalid flags that are valid when there is valid data in the buffer memory and invalid when there is no valid data, 60゛ is a network, 61 ” indicates a control line within the network, and 90 indicates a shared memory.

FIG. 5 shows a cache memory which is faster than the shared memory 90 and a buffer memory 21. 221 and 23, and is configured with three computers 11', 12'', and 13''.

In this case, access is performed as follows under the control of the control circuit (11', 12°, 13').

(1) Read access. For example, when there is valid data in the buffer memory 21 and the valid/invalid flag 41 is valid, the buffer memory 21 is read.

Data in buffer memory 21 is invalid and valid/invalid flag 4
1 is invalid, the shared memory 90 is accessed via the network 60'. (At this time, there is an access conflict.) (2) Write access. Perform the following actions simultaneously.

(b) Write data to the buffer memory, for example 21.

(b) Write data to the shared memory 90 via the network 60'. (There is an access conflict) (c) Buffer memory 22, 23 of another computer via the control line 61"
The valid/invalid flags 42 and 43 are invalidated.

In this way, the shared memory 90 is used to exchange data between the computers 1, 2.3.

[Problem that the invention seeks to solve]

However, in the above-mentioned conventional parallel computer, as long as there is valid data in the buffer memory during read access, the network 60' is not accessed, so there is no access contention at this time, but during write access, the network 60' is always accessed. Since the shared memory 90 and the valid/invalid flags of other computers must be accessed, there is always the possibility of access conflict, which poses a problem of slowing down the processing speed.

[Means for solving problems]

The above problem is caused by multiple computers 1 and 2 as shown in Figure 1.
,3. . . . Buffer memories 21, 22, 23 . . . are respectively used as shared memory. Equipped with...
Connected via network 60, the plurality of calculations ml, 2, 3
．． . . . Valid/invalid flags 41, 42, 43, which indicate whether the contents of the buffer memory are valid or invalid, respectively. ...
and copy presence/absence flags 31, 32, 33, which indicate whether the contents have been copied from another computer. ...and the buffer memories 21, 22, via the network 60.
23. ...and valid/invalid flags 41, 42, 43
．． ... and copy presence/absence flags 31, 32, 33.
Control circuits 11, 12, 13 .
... are provided, and the control circuits 11, 12, 13 . ...When accessing the own buffer memory for reading, if the valid/invalid flag is valid, the read is performed, and if it is invalid, the data is copied from the buffer memory of another computer and stored in the own buffer memory, and then the other computer's buffer memory is read. A means of reading by simultaneously setting the copy presence flag of the computer to copy presence, setting the copy presence flag of the own computer to copy presence, and validating the valid/invalid flag, and when writing access to the own buffer memory, the copy presence flag. If there is no copy, write it, and if there is a copy, invalidate the valid/invalid flag of the other computer, set the copy presence/absence flag to copy, and enable the valid/invalid flag of the own computer.

This problem is solved by the parallel computer of the present invention, which has means for simultaneously setting and writing the copy flag to indicate no copy.

[Effect]

According to the present invention, valid/invalid flags 41, 42, 43°, etc. indicating whether the contents of the buffer memory are valid or invalid, and copy presence flags 31, 32, 33°... are provided, and the buffer memory of each computer is 11°, 12.13. ..., the control circuit 11. 12. 13. It is used as a shared memory under the control of..., but when the valid/invalid flag is valid, the chances of read access contention can be reduced by reading the data in the own buffer memory without going through the network. Similarly, focusing on the fact that data in the own buffer memory may be written while it is not being copied by another computer, the copy presence/absence flags 31, 32, 33°, etc., which indicate whether or not the data is copied, are set as follows. By writing to the buffer memory without going through the network 60 when there is no copying, it is possible to eliminate the chance of write access contention while there is no copying, reduce the chance of access contention as a whole, and reduce the reduction in processing speed. It was made possible.

〔Example〕

FIG. 2 is a block diagram centered on the control circuit of the embodiment of the present invention, FIG. 3 is a diagram showing the processing flow of read access and write access of the control circuit of the embodiment of the present invention, and FIG. 4 is the read access , is a diagram illustrating an example of a state change of a flag before and after a write access.

In the figure, 11 is a control circuit, 31 is a copy presence/absence flag, 91 is a control unit, SWI, SW2 are switches, and the same reference numerals indicate the same functions throughout the figures.

FIG. 2 shows an embodiment centering on the control circuit engineer 1 as a representative of one computer part. When set to the solid line side, the address from the computer 1 is given to the own buffer memory 21 for read/write operations, and when set to the dotted line side, the address from the computer 1 is given to the buffer memory of another computer for control and read/write operations. It reads and writes the copy presence/absence flag 31 and the valid/invalid flag 41, controls the sending of the valid/invalid flag and the copy presence/absence flag of other computers, and performs read access and write access as shown in the processing flow of FIG. 3. It is something.

An address is necessary for data access, but for the sake of clarity, the following explanation will exclude this address and also exclude the explanation of the operations of the switches SWI and SW2.

Note that this operation can be realized using conventional cache memory technology.

Furthermore, in Fig. 3 and Fig. 4, the valid/invalid flag is indicated by VF, the copy presence/absence flag is indicated by CF, and the buffer memory is indicated by BM.
- in the figure indicates that any state is acceptable.

During read access, the control unit 91 sets the valid/invalid flag 41
As shown in FIG. 3(A), if the data is valid, it is read from the buffer memory 21, and if it is invalid, the valid data is copied from the buffer memory of another computer via the network 60 shown in FIG. , buffer memory 2
1, and set the copy flag of other computers to copy status unconditionally. When another computer writes, it executes the Yes side of the write access in FIG. At the same time, the copy presence/absence flag 31 is set to indicate copying, and the valid/invalid flag 41 is set to valid, and the data is read from the buffer memory 21.

The state of the flag before and after this read access is shown in the fourth
The result is as shown in Figure (A).

At the time of write access, the control unit 91 reads the copy presence/absence flag 41, and as shown in FIG. 3(B), if there is no copy, writes it to the buffer memory 21, and if there is,
Disabling the valid/invalid flag of another computer, prohibiting read access, setting the copy presence/absence flag to indicate copying and disabling direct writing, and setting the valid/invalid flag 41 of the own computer L to be valid and the copy presence/absence flag 31 to indicate no copy. are performed at the same time and written to the buffer memory 21, and thereafter the own buffer memory 21 can be accessed unless another computer reads it or writes it to another buffer memory.

The states before and after this write access are shown in FIG. 4(B).

If multiple computers write write access to their own expansion memory at the same time, with the copy presence/absence flag indicating copy, each computer can access the valid/invalid flag of the other computers via the control line 61 of the network 60 in FIG. I'm trying to set the flag to disable and the no copy flag to the copy flag at the same time, but they can't be done at the same time and are ordered, so
The flag setting is never undefined.

Note that the network 60 in FIG. 1 can be realized by a common bus, a data exchange network, a local area network, or the like.

〔Effect of the invention〕

As explained in detail above, according to the present invention, during write access, the network is not accessed while the data in the own breadthreader memory is not being copied to another computer, so opportunities for access conflicts are eliminated during this time, and processing This has the effect of reducing the decrease in speed.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram centered on the control circuit of the embodiment of the present invention, and Fig. 3 is a read access of the control circuit of the embodiment of the present invention.
FIG. 4 is a diagram showing a processing flow of a write access, FIG. 4 is a diagram showing changes in the state of flags before and after read access and write access, and FIG. 5 is a block diagram of a conventional parallel computer. In the figure, 1.2.3 is a computer (calculator), 11.12, 1
3.11', 12', 13" are control wholesale circuits, 21.22.23 is buffer memory, 31.32.33 is copy presence/absence flag, 41.42.4
3 is a valid/invalid flag, 60.60' is a network, 61.61' is a control line in the network, 90 is a shared memory, and 91 is a control unit. The disaster prevention of ν8 and the sealing of GJ are provided, and t14 and tr
=7UJ-v 7 figure 12 sf! If'J /) 70 Tsufu to I column 8 Shisan 5
K

Claims (1)

[Claims] Buffer memories (21, 22, 23) are provided to be used as shared memory for a plurality of computers (1, 2, 3, . . . ).
,...) connected via a network (60), and each of the plurality of computers (1, 2, 3,...) is provided with a valid/invalid flag (41) indicating whether the contents of the buffer memory are valid or invalid.
, 42, 43, ...) and a copy existence flag (31, 32, . . . ) indicating whether the content has been copied from another computer.
) and the buffer memory (21, 22, 23,...), the valid/invalid flag (41, 42, 43,...) and the copy presence/absence flag (31,...) via the network (60). A control circuit (11, 12, 13,...) is provided to control the buffer memory (11, 12, 13,...), and the control circuit (11, 12, 13,...) has read access to its own buffer memory. When doing so, read if the valid/invalid flag is valid, and if invalid, copy the data from the buffer memory of another computer and store it in its own buffer memory, and set the copy presence/absence flag of the other computer to copy. In addition, the copy presence/absence flag of the own computer is set to copy,
A means of simultaneously validating and reading the valid/invalid flag, and when writing access to the own buffer memory, writes if the copy flag indicates that there is no copy, and if there is a copy, sets the valid/invalid flag of another computer. A parallel computer is provided with a means for simultaneously invalidating and writing a copy presence/absence flag to indicate copying, validating a valid/invalid flag of its own computer, and setting a copy presence/absence flag to non-copying.