JPH04291642A - Cache control system - Google Patents

Abstract

PURPOSE:To reduce the operation ratio of a common bus to be accessed to a main storage device and to improve the performance of a cache control system for multiprocessor system. CONSTITUTION:In the multiprocessor system constituted so that plural processors 21 to 2n are connected to the main storage device 1 through the common bus 3 and each processor is provided with an exclusive cache memory 5, reads out objective data from its own cache memory 5 when the data concerned are stored in its own cache memory 5, or reads out the data concerned from the device 1 when the data are not stored in the cache memory 5, the cache memories 5 in respective processors 21 to 2n are connected through a cache bus 8 independent of the common bus 3 so that when data not stored in the cache memory of a certain processor are stored in another cache memory, the data are read out from the other cache memory through the bus 8.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache control method for a multiprocessor system.

In an information processing system using a main memory device and a processor, a cache memory is attached to the processor in order to substantially speed up access to the main memory device. This cache memory is configured using a small-capacity, relatively high-speed memory, and the related data in the main memory is copied and held in the cache memory in blocks in advance, and the data is transferred from the processor to the main memory. When accessing, first search whether the corresponding data is stored in the cache memory,
If the relevant data is present, the relevant data is read from the cache memory, and only when the relevant data is not stored in the cache memory, the main storage device is accessed and the relevant data is read.

0003

2. Description of the Related Art In recent years, in order to further increase the speed of information processing systems as described above, so-called multi-processor configuration systems using a plurality of processors have become mainstream. FIG. 1 shows an example of this conventional multiprocessor system.

In the figure, 1 is a main memory, 21 to 2n are processors, and 3 is a common bus connecting the main memory and each processor. Each of the n processors 21 to 2n has the same internal structure, and includes an instruction processing unit (IPU) 4 that executes a program, a cache memory 5,
It is composed of a tag 6 that stores address information of data stored in its own cache memory 5, and an interface (I/F) converter 7 for a common bus.

For example, in order to read predetermined data from the main memory device 1 in the #1 processor 21,
When the address information of the data is output from the instruction processing unit 4 to the common bus I/F converter 7, the common bus I/F converter 7 searches whether or not the address information is stored in the tag 6. . If the corresponding address information exists, the data at the address position is read from the cache memory 5 and sent to the processor 4. On the other hand, if the address information corresponding to the tag 6 does not exist, the main storage device 1 is accessed through the common bus 3, the corresponding data is read out, and the data is sent to the instruction processing unit 4.

[0006]

Problem to be Solved by the Invention In the case of the above-mentioned conventional multiprocessor system, multiplexed processors 2
The larger the number of processors 21 to 2n, the higher the frequency of access to the main storage device 1, and the busier the common bus 3 connecting the main storage device 1 and each processor 21 to 2n is.
The rate increases accordingly. Therefore, as the operating rate of the common bus 3 increases, it takes longer to access the main storage device 1, making it impossible to obtain the expected performance. In this manner, in a multiprocessor system, the maximum number of processors in the system is determined by the operating rate of the common bus, so how to reduce the operating rate of the common bus becomes an important issue.

The present invention has been made based on the above circumstances, and its object is to provide a cache control method that improves system performance by reducing the operating rate of a common bus that accesses the main storage device as much as possible. It is to provide.

[0008]

[Means for Solving the Problems] The cache control method of the present invention, as shown in its principle in FIG. Each processor is provided with its own dedicated cache memory 5, and when the desired data exists in its own cache memory, the corresponding data is read from the cache memory, and when the desired data does not exist, it is read from the common bus. In a multiprocessor system in which the corresponding data is read from the main memory via When data that does not exist on the above cache memory exists on another cache memory, the corresponding data is read from the other cache memory through the cache dedicated bus.

[0009]

[Operation] Even if the target data does not exist in its own cache memory, as long as the target data exists in the cache memory of another processor, it can be read and used through the cache dedicated bus 8. can. Therefore, the apparent hit rate of the cache memory in each processor is improved accordingly, and the number of accesses to the main storage device 1 can be reduced. As a result, the operating rate of the common bus 3 can be reduced accordingly.

0010

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 2 shows an embodiment of a multiprocessor system configured by applying the method of the present invention. This embodiment is an example of a multiprocessor system using two processors 21 and 22, and in the figure, 8 is the processor 2.
A cache dedicated bus connecting each cache memory 5 of 1 and 22, 9 an interface (I/F) converter for the cache dedicated bus, and 10 copying address information of data stored in the cache memory 5 of another processor. This is a tag that is stored as Note that circuits that are the same as those in FIG. 3 are given the same reference numerals and their explanations will be omitted.

#1 and #2 processors 21 and 22
Necessary data is read out from the main storage device 1 in block units via the common bus 3 and held in the cache memory 5 during the execution of each program. The address information of each piece of data held in this cache memory 4 is stored in each tag 6 paired with each cache memory 5.

The tag 10 of the #1 processor 21 has the following information:
The address information stored in the tag 6 of processor 22 #2 is copied and stored. In addition, the tag 10 of the #2 processor 22 includes the #1 processor 21
The address information stored in the tag 6 of is copied and stored. The writing of the address information of the cache memory of the other processor to each tag 9 is performed by, for example, constantly monitoring the common bus 3 for each processor.
When predetermined data and its address information are output from the main memory 1 to the cache memory 5 and tag 6 of the other processor, the address information is read through the common bus 3 and written to its own tag 10. This is realized by

Next, the operation of the above embodiment will be explained. When the #1 processor 21 starts read access of predetermined data to the main memory 1, the address information is sent to the common bus I/F converter 7 and the cache dedicated bus I/F converter 9, respectively. It will be done. Based on this address information, the common bus I/F converter 7
searches the tag 6 and determines whether data of the address information exists on its own cache memory 5. At the same time, the cache dedicated bus I/F converter 9 searches the tag 10 and determines whether data of the address information exists on the cache memory 5 of the other processor 22.

[0014] If the address information is hit in the tag 6, this indicates that the corresponding data exists in the own cache memory 5. Therefore, in this case, data at the corresponding address position is read from its own cache memory 5.

[0015]Also, tag 6 could not hit the address information, but if tag 10 hit,
This indicates that the corresponding data does not exist on its own cache memory 5, but exists on the cache memory 5 of processor 22 #2. Therefore, in this case, the cache-only bus I/F converter 9 accesses the cache memory 5 of the #2 processor 22 via the cache-only bus 8 and reads the data at the corresponding address position.

Furthermore, if the address information cannot be hit in either tag 6 or tag 10, it is determined that the corresponding data does not exist in either its own cache memory 5 or the cache memory 5 of the other processor 22. It shows. Therefore, in this case, for the first time, the cache dedicated bus I/F converter 9 accesses the main storage device 1 via the common bus 3, and
Read the corresponding data from.

In this way, even if the target data does not exist in its own cache memory, if the corresponding data exists in the cache memory of another processor, the data is retrieved from the cache memory of that processor. It can be read and used.

In the above embodiment, a tag 10 for copying and storing address information of other cache memories is attached to each processor, and data contents of other cache memories can be indirectly searched using this tag 10. However,
It is also possible to configure the tags 6 of other processors to be directly accessed and searched through a cache dedicated bus 8 that connects each cache memory.

[0019]

[Effect of the invention] As is clear from the above,
When using the cache control method of the present invention, the cache memories of each processor are connected by a cache dedicated bus independent of the common bus, and when data that does not exist in the own cache memory exists in another cache memory, Since the corresponding data is read from other cache memories through the cache-dedicated bus, the apparent hit rate of the cache memory in each processor can be improved, and the utilization rate of the common bus connecting the main storage device and each processor can be improved. It is possible to reduce the amount by that amount and improve the performance of the multiprocessor system.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the present invention.

FIG. 2 is a diagram showing an embodiment of a multiprocessor system configured by applying the method of the present invention.

FIG. 3 is a diagram showing a conventional example of a multiprocessor system.

[Explanation of symbols]

1 Main storage device 21 to 2n Processor 3 Common bus 4 Instruction processing unit 5
Cache memory 6 Tag 7 for own cache memory
Common bus interface converter 8
Cache dedicated bus 9 Cache dedicated bus interface converter

Claims (2)

[Claims] [Claim 1] A multiprocessor system in which a plurality of processors are connected to a main storage device via a common bus, where each processor is provided with its own dedicated cache memory and the desired data is stored in its own cache memory. In a multiprocessor system, the corresponding data is read from the cache memory when the target data does not exist, and when the target data does not exist, the corresponding data is read from the main storage device via a common bus. It is characterized in that it is connected by a cache dedicated bus independent of the bus, and when data that does not exist in its own cache memory exists in another cache memory, the corresponding data is read from the other cache memory through the cache dedicated bus. cache control method. 2. Each processor is provided with a tag that stores address information of data stored in the cache memory of another processor, and the data is stored in the other cache memory by referring to the address information of the tag. 2. The cache control method according to claim 1, wherein data is searched.