JPS63122248A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63122248A JPS63122248A JP61270147A JP27014786A JPS63122248A JP S63122248 A JPS63122248 A JP S63122248A JP 61270147 A JP61270147 A JP 61270147A JP 27014786 A JP27014786 A JP 27014786A JP S63122248 A JPS63122248 A JP S63122248A
- Authority
- JP
- Japan
- Prior art keywords
- bump
- metal
- opening
- insulating film
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000002184 metal Substances 0.000 claims abstract description 54
- 229910052751 metal Inorganic materials 0.000 claims abstract description 54
- 238000000034 method Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 239000011347 resin Substances 0.000 abstract description 13
- 229920005989 resin Polymers 0.000 abstract description 13
- 238000007772 electroless plating Methods 0.000 abstract description 4
- 229910052802 copper Inorganic materials 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 abstract 1
- 238000006731 degradation reaction Methods 0.000 abstract 1
- 238000010301 surface-oxidation reaction Methods 0.000 abstract 1
- 239000010949 copper Substances 0.000 description 12
- 230000006866 deterioration Effects 0.000 description 8
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 6
- 238000005530 etching Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 229910000831 Steel Inorganic materials 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 238000009832 plasma treatment Methods 0.000 description 3
- 239000010959 steel Substances 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910018885 Pt—Au Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000002203 pretreatment Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明に半導体装置の製造方法に係シ、特に金属バンプ
を有する半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device having metal bumps.
第２図（峠乃至第２ 因（、ｃ）は従来の半導体装置を
工程順に示す断面口である。従来のこの種の半導体装置
は、第２図（Ｃ）に示すようにバンプ６の上衣面のみ、
バリアメタルとなる金ｉ４膜ａ ／ 、 ４ ／を介
して、外部リード線との密着性をよくするための金属ｊ
ｉ７ 、８を形成し次構造を呈していた。FIG. 2 (pass to second factor (,c) is a cross-sectional view showing a conventional semiconductor device in the order of steps.A conventional semiconductor device of this type has an upper layer of bump 6 as shown in FIG. 2(C). Face only,
Metal j to improve adhesion with external lead wires through gold i4 films a / , 4 / which serve as barrier metals.
i7 and 8 were formed and exhibited the following structure.
さて、この種（第２図（Ｃ））の半導体装置の製造方法
として線、第２■（ａ）に示すように半導体基板１およ
びパッド電極３の上部に絶縁膜２を形成し、この絶縁膜
２のうち電極３の上方に第１の開口を形成し、電極３お
よび絶縁膜２上に、複数の金属膜３１ 、 ４１ 、
ｔ−形成し、これら複数の金１！４膜３−４′上に第２
図（ｂ）に示すように、感元性街脂９ｔ−付着させた後
、この感光性樹脂９のうち電極３の上方に、前記第１の
開口より大きい第２の開口を形成し、複数の金属膜３
／ 、 ４ ／上に、メッキ法により選択的に、バン
プ６を形成した後、第１及び第２の金属膜７，８を順次
メッキ形成し、感光性樹脂９を除去し念後、バンプ６を
マスクとして、前記複数の金属膜３／、４／を除去して
、第２幽（Ｃ） Ｋ示す半導体装置を形成していた。Now, as a manufacturing method of this type of semiconductor device (FIG. 2(C)), as shown in line 2(a), an insulating film 2 is formed on the semiconductor substrate 1 and the pad electrode 3, and this insulating film 2 is formed on the top of the semiconductor substrate 1 and the pad electrode 3. A first opening is formed above the electrode 3 in the film 2, and on the electrode 3 and the insulating film 2, a plurality of metal films 31, 41,
A second layer is formed on the plurality of gold 1!4 films 3-4'.
As shown in Figure (b), after the photosensitive street oil 9t is deposited, a second opening larger than the first opening is formed in the photosensitive resin 9 above the electrode 3. metal film 3
After selectively forming bumps 6 on /, 4/ by a plating method, first and second metal films 7 and 8 are sequentially plated, and after removing the photosensitive resin 9, bumps 6 are formed. Using this as a mask, the plurality of metal films 3/ and 4/ were removed to form a semiconductor device shown in the second figure (C)K.
前述した従来の半導体装置の＆遣方法によればバンプの
上表面以外はバンプの材質そのものが露出しておシ、バ
ンプ材として、特にＣｕはんだを使用する場合に酸化さ
れやすい構造を呈していた。According to the conventional semiconductor device and usage method described above, the bump material itself is exposed except for the upper surface of the bump, and the bump material has a structure that is particularly susceptible to oxidation when Cu solder is used. .
その念め、酸化その他による表面の変質を生じ、それが
電気的特性の劣化およびバンプ強度の劣化また耐湿性等
の信頼性の低下を招くという欠点があった。As a result, surface deterioration occurs due to oxidation or other factors, which leads to deterioration of electrical characteristics, deterioration of bump strength, and deterioration of reliability such as moisture resistance.
本発明の目的は、前記欠点を解決し、バンプの全面を酸
化されにくい金属膜で覆ってバンプの材質そのものの露
出部分をなくすことができ、酸化その他によるバンプ表
面の変質を防ぎ、バンプの電気的特性の劣化やバンプ強
度の劣化をなくし、信頼性の向上を図シ、安定なバンプ
構造を有する半導体装置の製造方法を提供することにあ
る。An object of the present invention is to solve the above-mentioned drawbacks, cover the entire surface of the bump with a metal film that is difficult to oxidize, eliminate exposed parts of the bump material itself, prevent deterioration of the bump surface due to oxidation and other causes, and improve the electrical performance of the bump. It is an object of the present invention to provide a method for manufacturing a semiconductor device having a stable bump structure, which eliminates deterioration of physical characteristics and bump strength, and improves reliability.
本発明の半導体装置の製造方法の構成は、半導体基板上
の絶縁膜の所定位置に設けられ次間口部からバンプが形
成され、前記絶縁膜を除去した後に、前記バンプの露出
表面に金属膜を形成することを特徴とする。The structure of the method for manufacturing a semiconductor device of the present invention is that a bump is formed at a predetermined position of an insulating film on a semiconductor substrate from the next opening, and after removing the insulating film, a metal film is formed on the exposed surface of the bump. It is characterized by forming.
次に本発明について図面を参照しながら詳細に説明する
。Next, the present invention will be explained in detail with reference to the drawings.
第１図（ａ）乃至第１図（ｅｌは本発明の一実施例の半
導体装置の製造方法を工程順に示す断面図である。FIGS. 1(a) to 1(el) are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.
まず、第１図（ａｌにおいて半導体素子を形成した半導
体基板ｌ上に全面にアルミニウム層を蒸着法またはスパ
ッタ法によシ、約１μｍ程度形成し、このアルミニウム
層の全面に感光性樹脂を形成し、半導体基板に形成し九
半導体素子に接続するためのパッド電極３の領域のみを
残して選択的にエツチングを行なう。その後、感光性樹
脂を除去し、前記電極を含む全面に絶縁膜２としてＣＶ
Ｄ酸化膜またはＣＶＤ窒化膜を形成する。次に感光性樹
脂を用いて選択的に前記絶縁膜２をエツチングし、パッ
ド電極３の上刃に第１の開口を形成する。First, an aluminum layer with a thickness of about 1 μm is formed on the entire surface of the semiconductor substrate l on which a semiconductor element is formed by vapor deposition or sputtering as shown in FIG. Then, selective etching is performed leaving only the region of the pad electrode 3 formed on the semiconductor substrate and connected to the semiconductor element.Then, the photosensitive resin is removed and a CV film is formed as an insulating film 2 on the entire surface including the electrode.
Form a D oxide film or a CVD nitride film. Next, the insulating film 2 is selectively etched using a photosensitive resin to form a first opening in the upper blade of the pad electrode 3.
次に第１図（ｂ）に示すように、前記電極３および前記
絶縁膜２上に、複数の金属膜３／、４／１例えばＴｉ／
Ｃｕ＝ １０００Ｘ／／１０００又程度を、スパッタ法
により形成し、バリアメタル４とする。次に第１図（Ｃ
）に示すように、複数の金属膜３／ 、 ４／上に、感
光性樹脂９を付着形成し、感光性樹脂９の前記電極３の
上刃に、前記第１の開口よシ大きい第２の開口を形成す
る。次いで、複数の金属膜３／、４／上に、約１８ｆｉ
ｍ程度の銅（Ｃｕ）バンプ６を電解メッキで形成する。Next, as shown in FIG. 1(b), on the electrode 3 and the insulating film 2, a plurality of metal films 3/, 4/1, for example, Ti/
Cu=1000X//1000 or so is formed by sputtering to form barrier metal 4. Next, Figure 1 (C
), a photosensitive resin 9 is adhered and formed on the plurality of metal films 3/ and 4/, and a second opening larger than the first opening is formed on the upper blade of the electrode 3 of the photosensitive resin 9. form an opening. Next, about 18 fi is applied on the plurality of metal films 3/, 4/.
Copper (Cu) bumps 6 having a thickness of about m are formed by electrolytic plating.
その後、第１図（ｄ）に示すように、感光性樹脂９を全
面除去し、複数の金属１ｘ３’ｔ４’のうち露出し次金
属膜４′２本実施例ではＣｕをエツチング除去して、Ｔ
ｉの金属膜３′を露出させる。この場合、Ｃｕのバンプ
６表面も少し工、チングされるが、これが約１８μｍに
対して、金属膜４′は０．１μｍであるから何ら問題は
ない。次に、第１図（ｅ）に示すように、Ｃｕバンプ６
の表面のみに、選択的に第１の金属層７としてＮ１−Ｐ
金属膜を形成する。ここで、バンプ６以外の表面に露出
したＴｉは、自然酸化されやすく、更に０．プラズマ処
理等を行なえば、Ｔｉ表面をきわめてメッキされにくく
することができる。この時、鋼上にも酸化物が形成され
るが、希硫酸などの前処理を行ない選択的に除去できる
ので選択的にメッキされやすくなる。したがって、Ｃｕ
バンプ６表面のみに選択的に、第１の金属Ｒ１７を形成
することが可能となる。Thereafter, as shown in FIG. 1(d), the photosensitive resin 9 is completely removed, and the exposed metal film 4'2 of the plurality of metals 1x3't4' is etched and removed, in this example, Cu. T
The metal film 3' of i is exposed. In this case, the surface of the Cu bump 6 is also slightly etched, but this is about 18 .mu.m, whereas the metal film 4' has a thickness of 0.1 .mu.m, so there is no problem. Next, as shown in FIG. 1(e), the Cu bump 6
N1-P is selectively applied as the first metal layer 7 only on the surface of
Form a metal film. Here, Ti exposed on the surface other than the bumps 6 is easily oxidized naturally, and furthermore, the Ti exposed on the surface other than the bumps 6 is easily oxidized naturally. By performing plasma treatment or the like, the Ti surface can be made extremely difficult to be plated. At this time, oxides are also formed on the steel, but they can be selectively removed by pretreatment with dilute sulfuric acid, making it easier to selectively plate the steel. Therefore, Cu
It becomes possible to selectively form the first metal R17 only on the surface of the bump 6.
次に、０．プラズマ処理等の前処理を行なうことにより
、第１の金属Ｉ？１７上のみをきわめてメッキされやす
くシ、第１の金属１１７上にのみに選択的に第２の金属
層８を無電解メッキにより形成する。例えばこの第２の
金属膜８として、１μｍ程度のＡｕを用いる。その後、
金属膜３′をエツチング除去する。本実施例では、Ｔｉ
エツチング液を用いて、エツチング除去する。Next, 0. By performing pre-treatment such as plasma treatment, the first metal I? The second metal layer 8 is selectively formed only on the first metal 117 by electroless plating, so that only the first metal 117 is easily plated. For example, this second metal film 8 is made of Au with a thickness of about 1 μm. after that,
The metal film 3' is removed by etching. In this example, Ti
Remove by etching using an etching solution.
以上により、本実施例の半導体装置が得られる。Through the above steps, the semiconductor device of this example is obtained.
尚、本実施例ではバンプ上層の金属の種類としてＮ１−
Ｐ金属等を用いたが、この他にＰｔ−Ａｕ。In this example, the type of metal on the upper layer of the bump is N1-
P metal etc. were used, but in addition to this, Pt-Au.
Ｎ ｌ −８ｎ 、 Ｐ ｔ −８ｎ でｈｖてよい
。N l -8n, P t -8n may be hv.
本実施例の半導体装置の製造方法は、半導体素子を形成
した半導体基板１上に前記半導体素子に接続するパッド
電極３を形成する工程と、前記半導体基板ｌおよび前記
パッド電極３を被覆するように絶縁膜２ｔ−形成する工
程と、前記絶縁膜２の前記パッド電極３の上刃に第１の
開口を形成する工程と、前記パッド電極３および前記絶
縁膜２上に複数の金属膜３ ／ 、 ４ ／を形成す
る工程と、前記複数の金属膜３１．４１上に感光性樹脂
９會付着形成し、前記感光性樹脂９のうち前記パッド電
極３の上方に選択的に前記第１の開口より大きい第２の
開口を形成する工程と、前記露出した複数の金属膜ａ
／ 、 ４ ／上にバンプメ；キ形成する工程と、前
記感光性樹脂９を除去し、前記複数の金属膜３′、４′
のうち露出し次金属膜４′を除去し、前記形成したバン
プ６の金属表面のみに第１の金属ＦｉＩ７を無電解メッ
キで形成する工程と、さらに前記形成した第１の金属層
７上のみ全面に第２の金属層８を無電解メッキで形成す
る工程と。The method for manufacturing a semiconductor device of this embodiment includes the steps of forming a pad electrode 3 connected to the semiconductor element on a semiconductor substrate 1 on which a semiconductor element is formed, and a step of covering the semiconductor substrate l and the pad electrode 3. a step of forming an insulating film 2t; a step of forming a first opening in the upper edge of the pad electrode 3 of the insulating film 2; a plurality of metal films 3/3 on the pad electrode 3 and the insulating film 2; 4) and forming a photosensitive resin 9 on the plurality of metal films 31.41, selectively opening the first opening above the pad electrode 3 in the photosensitive resin 9. a step of forming a large second opening; and a step of forming a plurality of exposed metal films a.
/ , 4 / A step of forming a bump plate on /, removing the photosensitive resin 9, and removing the plurality of metal films 3', 4'.
A step of removing the exposed metal film 4' and forming a first metal FiI 7 only on the metal surface of the bump 6 formed above by electroless plating, and further only on the first metal layer 7 formed above. A step of forming a second metal layer 8 on the entire surface by electroless plating.
バンプ６をマスクとして前記金属膜３′を除去する工程
とを含むことを特徴とする。The method is characterized in that it includes a step of removing the metal film 3' using the bump 6 as a mask.
例えば、前記複数の金属Ｍ３’ｅ ４’として、Ｔｔ／
Ｃｕを形成し、Ｃｕバンプを形成した場合、Ｃｕ。For example, as the plurality of metals M3'e 4', Tt/
When Cu is formed and a Cu bump is formed, Cu.
Ｔｉは共に自然酸化膜を形成するが、′希硫酸などの前
処理により、鋼上の酸化膜は除去され、Ｃｕパンツ表面
は非常にメッキしやすい状態なるのに対し、Ｔｉ上の酸
化膜は除去されないので、Ｔｉ上にメッキされｋ＜−６
このたみ、ＣｕＪｃＫのみ選択的にメッキされる現象を
利用した点に特徴がある。Both Ti forms a natural oxide film, but the oxide film on the steel is removed by pretreatment with dilute sulfuric acid, leaving the surface of the Cu pant in a state that is very easy to plate, whereas the oxide film on Ti is Since it is not removed, it is plated on Ti and k<-6
In addition, the method is characterized by utilizing the phenomenon in which only CuJcK is selectively plated.
以上説明したように、本発明によれば特に無電解メッキ
を行なう２８１類の金ＭＫ対して自然際化膜あるいは０
．プラズマ処理と希硫酸などの前処理による選択的除去
を利用して、バンプまわシにメッキしやすい状態をつく
９だした場合、酸化されにくい金属でバンプ全表面を橿
い、Ｍ酸化性金属でバンプを被覆することができるから
酸化その他によるバンプ表面の変質を防ぎ、電気的特性
の劣化やバンプ強度の劣化をなくシ、信頼性の向上を図
ることかできるという効果が得られる。As explained above, according to the present invention, it is possible to apply a natural borderline film or zero
．． If a condition is created in which the bump area is easily plated using selective removal through plasma treatment and pretreatment such as dilute sulfuric acid, the entire surface of the bump is coated with a metal that is difficult to oxidize, and then the entire surface of the bump is coated with a metal that is oxidizable. Since the bumps can be coated, it is possible to prevent deterioration of the bump surface due to oxidation or other causes, eliminate deterioration of electrical characteristics and bump strength, and improve reliability.
第１図（ａ）乃至！１ｍ（ｅ）は本発明の一実施例の半
導体装置の製造方法を工程順に示す断面図、第２図（ａ
）乃至第２図（Ｃ）は従来の半導体装置の製造方法を工
程順に示す断面図である。
１・・・・・・半導体基板、２・・・・・・絶縁膜、３
・・・・・・パッド電極、３’、４’・・・・・・バリ
アメタルとなる金属膜、６・・・・・・バンプ、７・・
・・・・第１の金属層、８・・・・・・第２の金属層、
９・・・・・・感光性樹脂。Figure 1 (a) to ! 1m(e) is a sectional view showing the manufacturing method of a semiconductor device according to an embodiment of the present invention in the order of steps, and FIG.
) to FIG. 2(C) are cross-sectional views showing the conventional method for manufacturing a semiconductor device in the order of steps. 1... Semiconductor substrate, 2... Insulating film, 3
...Pad electrode, 3', 4'...Metal film serving as barrier metal, 6...Bump, 7...
...First metal layer, 8...Second metal layer,
9...Photosensitive resin.
Claims (1)
からバンプを形成し、前記絶縁膜を除去した後に、前記
バンプの露出表面に金属膜を形成することを特徴とする
半導体装置の製造方法。A method for manufacturing a semiconductor device, comprising forming a bump through an opening provided at a predetermined position in an insulating film on a semiconductor substrate, removing the insulating film, and then forming a metal film on the exposed surface of the bump. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61270147A JPS63122248A (en) | 1986-11-12 | 1986-11-12 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61270147A JPS63122248A (en) | 1986-11-12 | 1986-11-12 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63122248A true JPS63122248A (en) | 1988-05-26 |
Family
ID=17482196
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61270147A Pending JPS63122248A (en) | 1986-11-12 | 1986-11-12 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63122248A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5266519A (en) * | 1991-11-12 | 1993-11-30 | Nec Corporation | Method for forming a metal conductor in semiconductor device |
| KR100392498B1 (en) * | 1999-08-30 | 2003-07-22 | 한국과학기술원 | Method for Formation of Bump for conductive polymer flip chip interconnects using electroless plating |
| KR20030095688A (en) * | 2002-06-14 | 2003-12-24 | 삼성전기주식회사 | Printed circuit board and plating method thereof |
| JP2008270816A (en) * | 2007-04-20 | 2008-11-06 | Samsung Electronics Co Ltd | Manufacturing method for semiconductor element capable of obtaining uniform electroless plating thickness |
| JP2019114786A (en) * | 2017-12-21 | 2019-07-11 | 東京エレクトロン株式会社 | Removal method and processing method |
| CN112242222A (en) * | 2019-07-18 | 2021-01-19 | 株式会社村田制作所 | Base body |
-
1986
- 1986-11-12 JP JP61270147A patent/JPS63122248A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5266519A (en) * | 1991-11-12 | 1993-11-30 | Nec Corporation | Method for forming a metal conductor in semiconductor device |
| KR100392498B1 (en) * | 1999-08-30 | 2003-07-22 | 한국과학기술원 | Method for Formation of Bump for conductive polymer flip chip interconnects using electroless plating |
| KR20030095688A (en) * | 2002-06-14 | 2003-12-24 | 삼성전기주식회사 | Printed circuit board and plating method thereof |
| JP2008270816A (en) * | 2007-04-20 | 2008-11-06 | Samsung Electronics Co Ltd | Manufacturing method for semiconductor element capable of obtaining uniform electroless plating thickness |
| JP2019114786A (en) * | 2017-12-21 | 2019-07-11 | 東京エレクトロン株式会社 | Removal method and processing method |
| CN112242222A (en) * | 2019-07-18 | 2021-01-19 | 株式会社村田制作所 | Base body |
| US20210020326A1 (en) * | 2019-07-18 | 2021-01-21 | Murata Manufacturing Co., Ltd. | Base |
| JP2021019043A (en) * | 2019-07-18 | 2021-02-15 | 株式会社村田製作所 | Base substance |
| CN112242222B (en) * | 2019-07-18 | 2022-11-29 | 株式会社村田制作所 | Substrate |
| US11694839B2 (en) * | 2019-07-18 | 2023-07-04 | Murata Manufacturing Co., Ltd. | Base configured as an electronic component or a circuit board |
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