JPS6336548A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS6336548A JPS6336548A JP61178838A JP17883886A JPS6336548A JP S6336548 A JPS6336548 A JP S6336548A JP 61178838 A JP61178838 A JP 61178838A JP 17883886 A JP17883886 A JP 17883886A JP S6336548 A JPS6336548 A JP S6336548A
- Authority
- JP
- Japan
- Prior art keywords
- film
- metal
- metal film
- insulating film
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title description 12
- 229910052751 metal Inorganic materials 0.000 claims abstract description 116
- 239000002184 metal Substances 0.000 claims abstract description 116
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims description 11
- 238000007747 plating Methods 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 8
- 150000002739 metals Chemical class 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 29
- 239000004642 Polyimide Substances 0.000 abstract description 3
- 229920001721 polyimide Polymers 0.000 abstract description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 2
- 239000010931 gold Substances 0.000 abstract description 2
- 229910052737 gold Inorganic materials 0.000 abstract description 2
- 230000001681 protective effect Effects 0.000 description 5
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- KRKNYBCHXYNGOX-UHFFFAOYSA-N citric acid Chemical compound OC(=O)CC(O)(C(O)=O)CC(O)=O KRKNYBCHXYNGOX-UHFFFAOYSA-N 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- UUWCBFKLGFQDME-UHFFFAOYSA-N platinum titanium Chemical compound [Ti].[Pt] UUWCBFKLGFQDME-UHFFFAOYSA-N 0.000 description 2
- 238000002203 pretreatment Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- XFXPMWWXUTWYJX-UHFFFAOYSA-N Cyanide Chemical compound N#[C-] XFXPMWWXUTWYJX-UHFFFAOYSA-N 0.000 description 1
- 230000002378 acidificating effect Effects 0.000 description 1
- 210000000988 bone and bone Anatomy 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は金属バンプを有する半導体装置及びその製造方
法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device having metal bumps and a method for manufacturing the same.
従来、回路素子が形成された半導体基板上に金属バンプ
を形成して外部回路との接続を行う半導体装置が提案さ
れているが、この金属バンプは大略第３図（ａ）〜（ｆ
）に示す工程で製造されている。Conventionally, a semiconductor device has been proposed that connects to an external circuit by forming metal bumps on a semiconductor substrate on which circuit elements are formed.
) is manufactured using the process shown in
先ず、同図（ａ）のように、半導体基板２１上の第１の
絶縁膜２２に形成した回路素子間を接続するための第１
の金属膜としてアルミニウム配線を形成し、その一部を
パッド電極２３として構成する。この上には第２の絶縁
膜２４を全面に被着し、更に図示を省略する第１のフォ
トレジストを用いて前記第２の絶縁膜２４を選択的に除
去してパッド電極２３を露出させる。そして、この上に
アルミニウム等の第２の金属膜２５を全面に形成し、更
にパッド電極２３近傍のみに開孔部を設けた第２のフォ
トレジスト膜２６をパターン形成する。First, as shown in FIG.
An aluminum wiring is formed as a metal film, and a part thereof is configured as a pad electrode 23. A second insulating film 24 is deposited on the entire surface, and the second insulating film 24 is selectively removed using a first photoresist (not shown) to expose the pad electrode 23. . Then, a second metal film 25 made of aluminum or the like is formed on the entire surface, and a second photoresist film 26 having openings only in the vicinity of the pad electrode 23 is further patterned.
次いで、同図（ｂ）のように、チタン−白金等の二重膜
構造の第３の金属膜２７を全面に被着させ、前記フォト
レジスト膜２６を利用したリフトオフ法によって同図（
ｃ）のようにパッド電極２３上にのみ第３の金属膜２７
を残存形成する。その後、改めて第３のフォトレジスト
膜２８を形成し、パッド電極２３上を開孔する。Next, as shown in FIG. 2(b), a third metal film 27 having a double film structure such as titanium-platinum is deposited on the entire surface, and a lift-off method using the photoresist film 26 is applied to the third metal film 27 as shown in FIG.
As shown in c), the third metal film 27 is formed only on the pad electrode 23.
form a residual. Thereafter, a third photoresist film 28 is formed again, and a hole is formed on the pad electrode 23.
続いて、同図（ｄ）のように前記第３の金属膜２７上に
メッキ法により金属バンブ２９を形成する。その後、同
図（ｅ）のように第３のフォトレジスト膜２８を除去し
、次いで第３の金属膜２７をマスクとして第２の金属膜
２５をエツチングする。Subsequently, as shown in FIG. 2D, metal bumps 29 are formed on the third metal film 27 by plating. Thereafter, as shown in FIG. 3(e), the third photoresist film 28 is removed, and then the second metal film 25 is etched using the third metal film 27 as a mask.
しかる上で、同図（ｆ） のように素子の保護膜とし
てのポリイミド等の膜３０を付着させ、図外の第４のフ
ォトレジストにより選択的にバターニ′ングして金属バ
ンブ２９上のみを除去して製造を完成する。Then, as shown in FIG. 2(f), a film 30 of polyimide or the like is deposited as a protective film for the element, and selective buttering is performed using a fourth photoresist (not shown) to cover only the metal bumps 29. Remove to complete manufacturing.
上述した製造方法で形成された金属バンブは、第２の絶
縁膜２４の段差が金属バンブ２９の下側に位置されるた
め、この段差がそのまま金属バンプ２９の表面に現れて
表面が凹状とされる。そして、この凹状の段差は第２の
絶縁膜２４の段差よりも大きくなる傾向がある。In the metal bump formed by the above manufacturing method, since the step of the second insulating film 24 is located below the metal bump 29, this step appears as it is on the surface of the metal bump 29, making the surface concave. Ru. This concave step tends to be larger than the step of the second insulating film 24.
このため、この凹状段差によって、金属バンプ２９をリ
ードに接続する際に、金属バンプ２９の周囲に先に圧力
が加えられることになり、半導体基板にクランクが生じ
たり、絶縁膜２４にクラックが生じ、膜剥がれや耐湿性
の劣化等の信頼性が低下される原因になっている。Therefore, due to this concave step, when connecting the metal bump 29 to a lead, pressure is applied first to the periphery of the metal bump 29, which may cause a crank in the semiconductor substrate or a crack in the insulating film 24. This is a cause of reduced reliability such as film peeling and deterioration of moisture resistance.
本発明の半導体装置は、以上の問題°を解消してクラッ
ク等を発生することなくその信頼性を向上させるために
、半導体基板の一主面に設けた第１の絶縁膜上に形成し
た第１の金属膜と、この第１の金属膜上に形成し、第１
の金属膜の一部を露呈するように開孔した第２の絶縁膜
と、この第２の絶縁膜の開孔よりも大きい寸法で前記第
１の金属膜上に形成した第２及び第３の金属膜と、前記
第２の絶縁膜の開孔の内側において前記第３の金属膜上
に形成した金属バンプとを備える構成としている。In order to solve the above problems and improve the reliability of the semiconductor device without generating cracks or the like, the semiconductor device of the present invention has a first insulating film formed on a first insulating film provided on one main surface of a semiconductor substrate. 1 metal film, a first metal film formed on the first metal film, and a first metal film formed on the first metal film.
a second insulating film with a hole formed to expose a part of the metal film; and second and third insulating films formed on the first metal film with dimensions larger than the aperture in the second insulating film. and a metal bump formed on the third metal film inside the opening of the second insulating film.
また、本発明の半導体装置の製造方法は、前記半導体装
置を製造工程を複雑化することなく製造可能とするもの
で、半導体基板の一主面に設けた第１の絶縁膜上に第１
の金属膜を形成する工程と、この第１の金属膜上に第２
の絶縁膜を形成し、かつその一部に前記第１の金属膜を
露呈させる第１の開孔を開設する工程と、前記第１の金
属膜の露呈部分に前記第１の開孔よりも大きな寸法の第
２及び第３の金属膜を形成する工程と、この第２゜第３
の金属膜上に感光性膜を形成しかつ前記第１の開孔の内
側にこれよりも小さな第２の開孔を開設する工程と、こ
の第２の開孔を通して前記第２゜第３の金属膜上に電極
バンプをメッキ法により形−成する工程と、この電極バ
ンプの下側にのみ前記感光性膜を残し、この電極バンプ
と感光性膜とをマスクにして前記第２の金属膜をエツチ
ングする工程とを含むものである。Further, the method for manufacturing a semiconductor device of the present invention enables the semiconductor device to be manufactured without complicating the manufacturing process.
a step of forming a second metal film on the first metal film;
forming an insulating film, and opening a first opening in a part of the insulating film to expose the first metal film; a step of forming second and third metal films with large dimensions;
a step of forming a photosensitive film on the metal film and opening a second hole smaller than the first hole inside the first hole; A step of forming electrode bumps on the metal film by plating, and leaving the photosensitive film only on the underside of the electrode bumps, and using the electrode bumps and the photosensitive film as a mask, forming the second metal film. The method includes a step of etching the.
次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の半導体装置の断面図であり、半導体基
板１上に第１の絶縁膜２を形成し、この上に形成した第
１の金属膜３を第２の絶縁膜４の開孔４ａ内に露呈させ
ている。この開孔４ａ内では第２及び第３の金属膜５．
７を形成し、この開孔の内側において金属バンブ９を形
成している。FIG. 1 is a cross-sectional view of a semiconductor device of the present invention, in which a first insulating film 2 is formed on a semiconductor substrate 1, and a first metal film 3 formed thereon is inserted into an opening of a second insulating film 4. It is exposed in the hole 4a. Inside this opening 4a, the second and third metal films 5.
7 is formed, and a metal bump 9 is formed inside this opening.
また、金属バンプ９以外の領域は保護１１！ＪＩＯで被
覆している。Also, the area other than the metal bump 9 is protected by 11! Covered with JIO.
第２図（ａ）〜（ｆ）は第１図の金属バンプを製造工程
順に示す図である。FIGS. 2(a) to 2(f) are diagrams showing the metal bump of FIG. 1 in the order of manufacturing steps.
先ず、同図（ａ）のように、半導体基板１上に第１の絶
縁膜２を全面に形成し、この上に図外の回路素子に接続
するアルミニウム配線を形成し、その一部を外部配線に
接続するパッドとして構成する第１の金属膜３を形成す
る。そして、この金属膜３を被覆する第２の絶縁膜４を
ＣＶＤ法等により形成し、かつこれを図示を省略する第
１のフォトレジストを用いて選択エツチングして前記バ
ンド上に第１の開孔４ａを開設する。First, as shown in FIG. 2(a), a first insulating film 2 is formed over the entire surface of a semiconductor substrate 1, and aluminum wiring connected to circuit elements (not shown) is formed on this, and a part of it is exposed externally. A first metal film 3 configured as a pad connected to wiring is formed. Then, a second insulating film 4 covering this metal film 3 is formed by a CVD method or the like, and this is selectively etched using a first photoresist (not shown) to form a first opening on the band. Open hole 4a.
次いで、同図（ｂ）のようにスパッタ法等によりアルミ
ニウム等の第２の金属膜５を３０００〜１００００人の
厚さに形成する。そして、第２のフォトレジスト膜６を
スピンナ法等で塗布して形成しこのフォトレジスト膜６
にはバッド近傍のみに開窓６ａを形成する。このとき、
開窓６ａは前記第１の開孔４ａよりも大きくすることが
肝要である。Next, as shown in FIG. 3B, a second metal film 5 made of aluminum or the like is formed to a thickness of 3,000 to 10,000 wafers by sputtering or the like. Then, a second photoresist film 6 is formed by coating with a spinner method or the like.
A fenestration 6a is formed only near the pad. At this time,
It is important that the fenestration 6a be larger than the first aperture 4a.
次に、同図（Ｃ）のように、第３の金属膜７を形成する
。この金属膜７は例えばチタン−白金の二重構造からな
り、膜厚はチタン５００〜２０００人。Next, as shown in FIG. 3C, a third metal film 7 is formed. The metal film 7 has a double structure of titanium and platinum, for example, and has a thickness of 500 to 2000 titanium.
白金５００〜３０００人程度である。この膜の形成には
、同一真空容器内で真空を止めることなくチタン。There are about 500 to 3,000 people in Shirokane. This film was formed using titanium in the same vacuum container without stopping the vacuum.
白金の連続スパッタを行うことにより接着性を向上でき
る。そして、この第３の金属膜７は第２のフォトレジス
ト膜６の段差により分断形成されているため、この第２
のフォトレジスト膜６を溶解法等によって除去し、これ
とともに所謂リフトオフ法によってバッド上以外の領域
の第３の金属膜７を除去する。Adhesion can be improved by continuously sputtering platinum. Since this third metal film 7 is formed in sections by the steps of the second photoresist film 6, this second metal film 7
The photoresist film 6 is removed by a dissolving method or the like, and at the same time, the third metal film 7 in the region other than the pad is removed by a so-called lift-off method.
その後、同図（ｄ）のように第３のフォトレジスト膜８
を塗布し、パッド上には前記第１の開孔４ａよりも小さ
い第２の開孔８ａを開設する。After that, the third photoresist film 8 is formed as shown in FIG.
A second aperture 8a smaller than the first aperture 4a is formed on the pad.
次いで、同図（ｅ）のように第２の金属膜５及び第３の
金属膜５をメッキ用電極とし、第３のフォトレジスト膜
８をマスクとして金メッキを１０〜２０μｍの厚さに行
い金属バンプ９を形成する。メッキ浴としてはシアン化
浴、酸性クエン酸浴等が利用でき、このメッキ浴中で電
界を与え、電流を必要な電流密度骨だけ流すことにより
実行できる。Next, as shown in FIG. 5E, gold plating is performed to a thickness of 10 to 20 μm using the second metal film 5 and the third metal film 5 as plating electrodes and the third photoresist film 8 as a mask. Bumps 9 are formed. As a plating bath, a cyanide bath, an acidic citric acid bath, etc. can be used, and the plating can be carried out by applying an electric field in this plating bath and flowing a current only through the bone with the required current density.
通常、下地の金属によってはメッキの前処理が必要とさ
れるがチタン−白金の場合には前処理はなくても可能で
ある。Usually, pre-treatment for plating is required depending on the underlying metal, but titanium-platinum can be plated without any pre-treatment.
そして、同図（ｆ）のように金属バンプ９をマスクにし
て第３のフォトレジスト膜８を例えばＣＣ１，を用いて
異方性エツチングし、更に金属バンプ９と第３のフォト
レジスト膜８をマスクにして例えばリン酸系の溶液で第
２の金属膜５をエツチングする。Then, as shown in FIG. 5F, the third photoresist film 8 is anisotropically etched using, for example, CC1, using the metal bumps 9 as a mask, and the metal bumps 9 and the third photoresist film 8 are further etched. The second metal film 5 is etched using, for example, a phosphoric acid solution as a mask.
次いで、金属バンプ９の下側に残存される第３のフォト
レジスト膜８を除去し、素子の保護膜として有機物の保
護膜１０、例えばポリイミドをスピンナ法により塗布し
て０．５〜４μｍ付着させる。Next, the third photoresist film 8 remaining below the metal bumps 9 is removed, and an organic protective film 10, such as polyimide, is applied as a protective film for the element by a spinner method to a thickness of 0.5 to 4 μm. .
保護膜１０は金属バンプ９の下側にも入り込んで形成さ
れ、その上で金属バンプ９上のみ除去することにより第
１図の構造を完成する。The protective film 10 is also formed under the metal bumps 9, and is then removed only on the metal bumps 9 to complete the structure shown in FIG.
この構成の金属バンプ９によれば、金属バンプ９は第２
の絶縁膜４に開設した第１の開孔４ａよりも小さく形成
した第３のフォトレジスト膜８の第２の開孔８ａの内側
に形成しているので、金属バンプ９の寸法を第１の開孔
４ａよりも小さくでき、金属バンプ９の下側に第１の開
孔４ａの段差が存在されることはない。このため、金属
バンプ９をメッキ形成しても金属バンプ表面に凹状の窪
みが発生することがなく、略平坦な形状に形成できる。According to the metal bump 9 having this configuration, the metal bump 9 has a second
Since the metal bumps 9 are formed inside the second apertures 8a of the third photoresist film 8, which are smaller than the first apertures 4a formed in the insulating film 4 of It can be made smaller than the opening 4a, and there is no difference in level of the first opening 4a below the metal bump 9. Therefore, even when the metal bumps 9 are formed by plating, no concave depressions are generated on the surface of the metal bumps, and the metal bumps can be formed into a substantially flat shape.
このため、リードへの接続時に金属バンプ°９に均一な
力が加えられ、偏った力が原因とされる絶縁膜や半導体
基板におけるクランクの発生を防止できる。Therefore, a uniform force is applied to the metal bump 9 when connected to the lead, and it is possible to prevent cranking in the insulating film or semiconductor substrate caused by uneven force.
また、この製造方法では第２の金属膜５を除去するため
のエツチング時に、マスクとしての第３の金属膜７との
間に隙間が生じていても、この部分は第３のフォトレジ
スト膜８で覆われることになるのでエツチング液が侵入
されることはなく、第１の金属膜３がエツチングされて
回路素子に主配線の断線が生じることはない。Furthermore, in this manufacturing method, even if a gap is created between the second metal film 5 and the third metal film 7 as a mask during etching to remove the second metal film 5, this portion is removed by the third photoresist film 8. Since the first metal film 3 is covered with the etching solution, the etching solution will not penetrate, and the first metal film 3 will not be etched and the main wiring will not be disconnected in the circuit element.
ここで、前記第２図（ｅ）、 （ｆ）の工程は次のよ
うに変更することもできる。即ち、第３のフォトレジス
ト膜８にポジ型レジストを用い、メッキにより金属バン
プ９を形成した後にこの金属バンブをマスクにして第３
のフォトレジスト膜８に再度露光、現像を行なう。これ
により、露光されない金属バンプ９の下側の第３のフォ
トレジスト膜８のみが残り、他は現像によって除去され
る。Here, the steps shown in FIGS. 2(e) and 2(f) can be modified as follows. That is, a positive resist is used as the third photoresist film 8, and after forming metal bumps 9 by plating, the third photoresist film 8 is formed using the metal bumps as a mask.
The photoresist film 8 is exposed and developed again. As a result, only the third photoresist film 8 under the metal bumps 9 that is not exposed to light remains, and the rest is removed by development.
次いで、リン酸系の溶液を用いて第２の金属膜５をエツ
チングすればよい。Next, the second metal film 5 may be etched using a phosphoric acid solution.
以上説明したように本発明の半導体装置は、金属バンプ
を第２の絶縁膜の開孔よりも小さく形成した第３のフォ
トレジスト膜の開孔内に形成して金属バンプの寸法を第
２の絶縁膜の開孔よりも小さくしているので、金属バン
プの下側に第２の絶縁膜の開孔の段差が存在されること
はなく、金属バンプ表面に凹状の窪みを発生させること
なく略平坦な形状に形成できる。このため、リードへの
接続時に金属バンプに均一な力が加えられ、偏った力が
原因とされる絶縁膜や半導体基板におけるクランクの発
生を防止できる。As explained above, in the semiconductor device of the present invention, the metal bumps are formed in the openings of the third photoresist film, which are formed smaller than the openings of the second insulating film, and the dimensions of the metal bumps are made smaller than the openings of the second insulating film. Since the openings are smaller than the openings in the insulating film, there is no difference in level between the openings in the second insulating film below the metal bumps, and the openings in the second insulating film are made smaller than the openings in the metal bumps. Can be formed into a flat shape. Therefore, a uniform force is applied to the metal bump during connection to the lead, and it is possible to prevent cranking in the insulating film or semiconductor substrate caused by uneven force.
また、本発明の製造方法では電極バンブの下側に第３の
フォトレジスト膜を残存させた状態で第２の金属膜を除
去するためのエツチングを行っているので、このエツチ
ング時に、マスクとしての第３の金属膜との間に隙間が
生じていても、第３のフォトレジスト膜で覆われている
のでエツチング液が侵入されることはなく、第１の金属
膜がエツチングされることにより断線の発生を防止でき
る。Furthermore, in the manufacturing method of the present invention, etching is performed to remove the second metal film while leaving the third photoresist film on the underside of the electrode bump. Even if there is a gap between the third metal film and the third metal film, the etching solution will not penetrate because it is covered with the third photoresist film, and the first metal film will be etched and the wire will be disconnected. can be prevented from occurring.
更に、本発明の製造方法は、従来工程に単に第３フオト
レジスト膜の異方性エツチングを追加し、或いはポジ型
レジストを用いた上で全面露光及び現像を追加するのみ
でよいので、製造工程を大幅に増大させることもない。Furthermore, the manufacturing method of the present invention requires only adding anisotropic etching of the third photoresist film to the conventional process, or adding full-surface exposure and development after using a positive resist, so that the manufacturing process can be simplified. It does not significantly increase.
第１図は本発明の一実施例の断面図、第２図（ａ）〜（
ｆ）は本発明の製造方法を工程順に示す断面図、第３図
（ａ）〜（ｆ）は従来方法を工程順に示す断面図である
。
１．２１・・・半導体基板、２．２２・・・第１の絶縁
膜、３．２３・・・第１の金属膜、４，２４・・・第２
の絶縁膜、４ａ・・・第１の開孔、５，２５・・・第２
の金属膜、６．２６・・・第２のフォトレジスト、６ａ
・・・開窓、７．２７・・・第３の金属膜、８，２８・
・・第３のフォトレジスト、８ａ・・・第２の開孔、９
，２９・・・金属バンプ、１０．３０・・・保護膜。
ス、八
代理人 弁理士 鈴 木 章 夫、′漫＋ 、 、ｊ
’Ｈ’、′
第３図FIG. 1 is a sectional view of an embodiment of the present invention, and FIGS. 2(a) to (
f) is a sectional view showing the manufacturing method of the present invention in order of steps, and FIGS. 3(a) to 3(f) are sectional views showing the conventional method in order of steps. 1.21... Semiconductor substrate, 2.22... First insulating film, 3.23... First metal film, 4, 24... Second
insulating film, 4a...first opening, 5, 25...second
metal film, 6.26... second photoresist, 6a
...fenestration, 7.27...third metal film, 8,28.
...Third photoresist, 8a...Second opening, 9
, 29... Metal bump, 10.30... Protective film. Suzuki, Patent Attorney Akio Suzuki, 'man＋ , , j
'H',' Figure 3
Claims (2)
成した第１の金属膜と、この第１の金属膜上に形成し、
第１の金属膜の一部を露呈するように開孔した第２の絶
縁膜と、この第２の絶縁膜の開孔よりも大きい寸法で前
記第１の金属膜上に形成した第２及び第３の金属膜と、
前記第２の絶縁膜の開孔の内側において前記第３の金属
膜上に形成した金属バンプとを備えることを特徴とする
半導体装置。(1) a first metal film formed on a first insulating film provided on one main surface of a semiconductor substrate; and a first metal film formed on the first metal film,
a second insulating film with a hole formed to expose a part of the first metal film; a second insulating film formed on the first metal film with a size larger than the aperture in the second insulating film; a third metal film;
A semiconductor device comprising: a metal bump formed on the third metal film inside the opening of the second insulating film.
１の金属膜を形成する工程と、この第１の金属膜上に第
２の絶縁膜を形成し、かつその一部に前記第１の金属膜
を露呈させる第１の開孔を開設する工程と、前記第１の
金属膜の露呈部分に前記第１の開孔よりも大きな寸法の
第２及び第３の金属膜を形成する工程と、この第２、第
３の金属膜上に感光性膜を形成しかつ前記第１の開孔の
内側にこれよりも小さな第２の開孔を開設する工程と、
この第２の開孔を通して前記第２、第３の金属膜上に電
極バンプをメッキ法により形成する工程と、この電極バ
ンプの下側にのみ前記感光性膜を残し、この電極バンプ
と感光性膜とをマスクにして前記第２の金属膜をエッチ
ングする工程とを含むことを特徴とする半導体装置の製
造方法。(2) forming a first metal film on a first insulating film provided on one principal surface of a semiconductor substrate; forming a second insulating film on the first metal film; forming a first aperture exposing the first metal film in the exposed portion of the first metal film; and forming second and third metals larger in size than the first aperture in the exposed portion of the first metal film. a step of forming a film, a step of forming a photosensitive film on the second and third metal films, and opening a second aperture smaller than the first aperture inside the first aperture;
A step of forming an electrode bump on the second and third metal films through the second opening by a plating method, and leaving the photosensitive film only on the lower side of the electrode bump, and etching the second metal film using the second metal film as a mask.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61178838A JPS6336548A (en) | 1986-07-31 | 1986-07-31 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61178838A JPS6336548A (en) | 1986-07-31 | 1986-07-31 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6336548A true JPS6336548A (en) | 1988-02-17 |
Family
ID=16055549
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61178838A Pending JPS6336548A (en) | 1986-07-31 | 1986-07-31 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6336548A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02159034A (en) * | 1988-12-13 | 1990-06-19 | Nec Corp | External electrode structure on semiconductor integrated circuit |
| JPH0453138A (en) * | 1990-06-18 | 1992-02-20 | Nec Corp | Semiconductor device and manufacture of the same |
| US6404051B1 (en) | 1992-08-27 | 2002-06-11 | Kabushiki Kaisha Toshiba | Semiconductor device having a protruding bump electrode |
| JP2008060588A (en) * | 2007-09-21 | 2008-03-13 | Fujitsu Ltd | Method for manufacturing semiconductor device |
| JP2012028708A (en) * | 2010-07-27 | 2012-02-09 | Renesas Electronics Corp | Semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6070747A (en) * | 1983-09-27 | 1985-04-22 | Oki Electric Ind Co Ltd | Manufacture of semiconductor devicse |
-
1986
- 1986-07-31 JP JP61178838A patent/JPS6336548A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6070747A (en) * | 1983-09-27 | 1985-04-22 | Oki Electric Ind Co Ltd | Manufacture of semiconductor devicse |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02159034A (en) * | 1988-12-13 | 1990-06-19 | Nec Corp | External electrode structure on semiconductor integrated circuit |
| JPH0453138A (en) * | 1990-06-18 | 1992-02-20 | Nec Corp | Semiconductor device and manufacture of the same |
| US6404051B1 (en) | 1992-08-27 | 2002-06-11 | Kabushiki Kaisha Toshiba | Semiconductor device having a protruding bump electrode |
| US6605522B1 (en) | 1992-08-27 | 2003-08-12 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device having a protruding bump electrode |
| JP2008060588A (en) * | 2007-09-21 | 2008-03-13 | Fujitsu Ltd | Method for manufacturing semiconductor device |
| JP4617339B2 (en) * | 2007-09-21 | 2011-01-26 | 富士通セミコンダクター株式会社 | Manufacturing method of semiconductor device |
| JP2012028708A (en) * | 2010-07-27 | 2012-02-09 | Renesas Electronics Corp | Semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2785338B2 (en) | Method for manufacturing semiconductor device | |
| JP2809088B2 (en) | Protruding electrode structure of semiconductor device and method for forming the protruding electrode | |
| JPS6336548A (en) | Semiconductor device and manufacture thereof | |
| JP2000150518A (en) | Manufacture of semiconductor device | |
| JPH02253628A (en) | Manufacture of semiconductor device | |
| JP3446021B2 (en) | Bump electrode structure of semiconductor device and method for forming the same | |
| JPH03198342A (en) | Manufacture of semiconductor device | |
| JPH02224336A (en) | Manufacture of semiconductor device | |
| JPH11224890A (en) | Semiconductor device and its manufacturing | |
| JPH03101234A (en) | Manufacture of semiconductor device | |
| JP2751242B2 (en) | Method for manufacturing semiconductor device | |
| JPS63122248A (en) | Manufacture of semiconductor device | |
| JP2748530B2 (en) | Method for manufacturing semiconductor device | |
| JPS6329940A (en) | Manufacture of semiconductor device | |
| JP2000299338A (en) | Method of forming projected electrodes and bare chip ic having the same | |
| JPH0312933A (en) | Manufacture of semiconductor device | |
| JP2874184B2 (en) | Method for manufacturing semiconductor device | |
| JPH02277242A (en) | Manufacture of semiconductor device | |
| JPH0350734A (en) | Manufacture of integrated circuit | |
| JP3132194B2 (en) | Method for manufacturing semiconductor device | |
| JPH06342796A (en) | Forming method of bump electrode | |
| JPS5950095B2 (en) | Manufacturing method of semiconductor device | |
| JPS621249A (en) | Semiconductor device | |
| JP3049872B2 (en) | Method for manufacturing semiconductor device | |
| JPH04307737A (en) | Manufacture of semiconductor device |