JPH0373535A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH0373535A JPH0373535A JP1210307A JP21030789A JPH0373535A JP H0373535 A JPH0373535 A JP H0373535A JP 1210307 A JP1210307 A JP 1210307A JP 21030789 A JP21030789 A JP 21030789A JP H0373535 A JPH0373535 A JP H0373535A
- Authority
- JP
- Japan
- Prior art keywords
- photosensitive resin
- film
- layer
- pad electrode
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 229910052751 metal Inorganic materials 0.000 claims abstract description 19
- 239000002184 metal Substances 0.000 claims abstract description 19
- 239000003054 catalyst Substances 0.000 claims abstract description 12
- 229920006015 heat resistant resin Polymers 0.000 claims abstract description 11
- 238000007772 electroless plating Methods 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 4
- 229910021645 metal ion Inorganic materials 0.000 claims description 2
- 229920005989 resin Polymers 0.000 abstract description 26
- 239000011347 resin Substances 0.000 abstract description 26
- 229910052782 aluminium Inorganic materials 0.000 abstract description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 7
- 238000009413 insulation Methods 0.000 abstract 3
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 229910052763 palladium Inorganic materials 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 abstract 1
- 229910052718 tin Inorganic materials 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 32
- 238000004544 sputter deposition Methods 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 244000271437 Bambusa arundinacea Species 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910052745 lead Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置およ・びその製造方法に関し、特に
バンブを有する半導体装置及びその製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having bumps and a method for manufacturing the same.
従来のバンブの形成方法を第３図を用いて説明する。 A conventional method for forming bumps will be explained with reference to FIG.
まず第３図（ａ）に示す様に、半導体素子を形成した半
導体基板１１上にアルミニウム層を蒸着法又はスパッタ
法により１μｍ程度の厚さに形成し、このアルミニウム
層全面に感光性樹脂を形成し、半導体基板１１に形成し
た半導体素子に接続するためのパッド電極領域のみを残
してアルミニウム層を選択的にエツチングしたのち、感
光性樹脂を除去してパッド電極１２を形成する。その後
、パッド電極１２を含む半導体基板１１の全面に絶縁膜
１３としてＣＶＤ酸化膜又はプラズマＣＶＤ窒化膜を形
成する０次に感光性樹脂を用いて選択的に絶縁膜１３を
エツチングしパッド電極１２上方に第１の開口を形成す
る。First, as shown in FIG. 3(a), an aluminum layer with a thickness of about 1 μm is formed on the semiconductor substrate 11 on which a semiconductor element is formed by vapor deposition or sputtering, and a photosensitive resin is formed on the entire surface of this aluminum layer. After selectively etching the aluminum layer leaving only the pad electrode region for connection to the semiconductor element formed on the semiconductor substrate 11, the photosensitive resin is removed to form the pad electrode 12. Thereafter, a CVD oxide film or a plasma CVD nitride film is formed as the insulating film 13 on the entire surface of the semiconductor substrate 11 including the pad electrode 12.The insulating film 13 is selectively etched using a zero-order photosensitive resin, and the insulating film 13 is selectively etched above the pad electrode 12. A first opening is formed in the opening.
次に第３図（ｂ）に示すように、パッド電極１２を含む
半導体基板１１の全面に第１及び第２の金属膜２１．２
２として、例えば、Ｔｉ。Next, as shown in FIG. 3(b), first and second metal films 21.2 are formed on the entire surface of the semiconductor substrate 11 including the pad electrode 12.
2, for example, Ti.
Ｃｒ−Ｃｕ等を〜１００ＯＡ程度スパッタ法により形成
し、接着層、バリアメタル層及びメッキ電極とする０次
で第２の金属膜２２上に感光性樹脂１５を形成し、この
感光性樹脂１５のパッド電極１２の上方に第１の開口よ
り大きい第２の開口を形成し、第２の金属膜２２を露出
させる。A photosensitive resin 15 is formed by sputtering approximately 100 OA of Cr-Cu, etc., on the zero-order second metal film 22 that will serve as an adhesive layer, a barrier metal layer, and a plating electrode. A second opening larger than the first opening is formed above the pad electrode 12 to expose the second metal film 22.
次に第３図（ｃ）に示すように、露出した第２の金属膜
２２上に電解メッキにより、ＡｕやＣｕからなるバンプ
２３を形成する。膜厚は１５μｍ程度あれば十分である
。さらに場合によりバンプ表面に酸化防止又はボンディ
ングの密着性向上の目的で第３の金属膜としてＡｕ膜２
４やｐｂ−３ｎ膜等を５μｍ程の厚さにメッキにより形
成する。Next, as shown in FIG. 3(c), bumps 23 made of Au or Cu are formed on the exposed second metal film 22 by electrolytic plating. A film thickness of about 15 μm is sufficient. Furthermore, in some cases, an Au film 2 is applied as a third metal film to the bump surface for the purpose of preventing oxidation or improving bonding adhesion.
4 or pb-3n film or the like is formed by plating to a thickness of about 5 μm.
次に第３図（ｄ）に示すように、感光性樹脂１５を除去
後、第２．第１の金属膜２２．２１をバンプ２３をマス
クとして順次エツチング除去する。Next, as shown in FIG. 3(d), after removing the photosensitive resin 15, the second. The first metal films 22 and 21 are sequentially etched away using the bumps 23 as a mask.
上述した従来の半導体装置では、バンプにワイヤ等をボ
ンディングする場合、ボンディング時の熱及び圧力によ
り半導体基板に応力が加わり、半導体基板にクラックを
生じバンプの密着強度及びバンプとパッド電極の電気的
なオープンが発生する。さらに、パッド電極付近の絶縁
膜にもクラックが生じ、耐湿性が劣化し、半導体装置の
信頼性の低下をまねくという欠点があった。In the conventional semiconductor device described above, when bonding a wire or the like to a bump, stress is applied to the semiconductor substrate due to heat and pressure during bonding, causing cracks in the semiconductor substrate and reducing the adhesion strength of the bumps and the electrical resistance between the bumps and pad electrodes. An open occurs. Furthermore, cracks occur in the insulating film near the pad electrodes, resulting in deterioration in moisture resistance and a reduction in reliability of the semiconductor device.
本発明の半導体装置は、半導体基板上に形成されたパッ
ド電極と、前記パッド電極上に形成された耐熱性樹脂か
らなる凸状層と、前記凸状層表面に形成され前記パッド
電極に接続する金属層とを含んで構成される。The semiconductor device of the present invention includes a pad electrode formed on a semiconductor substrate, a convex layer made of a heat-resistant resin formed on the pad electrode, and a convex layer formed on the surface of the convex layer and connected to the pad electrode. and a metal layer.
また本発明の半導体装置の製造方法は、半導体基板上に
パッド電極を形成する工程と、前記パッド電極を含む全
面に絶縁層を形成したのちパターニングし前記パッド電
極上に開口部を形成する工程と、前記開口部を含む全面
に耐熱性樹脂層を形成したのちパターニングし前記開口
部内に開口部より幅の狭い凸状層を形成する工程と、前
記凸状層及び前記開口部に露出したパッド電極の表面に
金属イオンを注入し無電解メッキ用の触媒層を形成する
工程と、無電解メッキにより前記触媒層の表面に金属膜
を形成する工程とを含んで構成される。The method for manufacturing a semiconductor device of the present invention also includes a step of forming a pad electrode on a semiconductor substrate, and a step of forming an insulating layer on the entire surface including the pad electrode and then patterning it to form an opening on the pad electrode. , a step of forming a heat-resistant resin layer on the entire surface including the opening, and then patterning it to form a convex layer having a width narrower than the opening in the opening, and a pad electrode exposed in the convex layer and the opening. The method includes a step of injecting metal ions into the surface of the catalyst layer to form a catalyst layer for electroless plating, and a step of forming a metal film on the surface of the catalyst layer by electroless plating.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の第１の実施例を説明するための半導体
チップの断面図である。FIG. 1 is a sectional view of a semiconductor chip for explaining a first embodiment of the present invention.
まず第１図（ａ＞に示すように、半導体素子を形成した
半導体基板１１上にアルミニウム層を蒸着法又はスパッ
タ法により１μｍ程度の厚さに形成する０次でこのアル
ミニウム層全面に感光性樹脂を形成し、半導体基板１１
上に形成した半導体素子に接続するためのパッド電極領
域のみを残してアルミニウム層を選択的にエツチングし
た後、感光性樹脂を除去する。その後形成されたパッド
電極１２を含む全面に絶縁膜１３として、ＣＶＤ酸化膜
又はプラズマＣＶＤ窒化膜を形成する。次に感光性樹脂
を用いて選択的に絶縁膜１３をエツチングし、パッド電
極１２の上方に開−口部３０を形成する。First, as shown in FIG. 1 (a), an aluminum layer is formed to a thickness of about 1 μm by vapor deposition or sputtering on a semiconductor substrate 11 on which a semiconductor element is formed. is formed, and the semiconductor substrate 11
After selectively etching the aluminum layer leaving only the pad electrode region for connection to the semiconductor element formed above, the photosensitive resin is removed. A CVD oxide film or a plasma CVD nitride film is then formed as an insulating film 13 over the entire surface including the formed pad electrode 12. Next, the insulating film 13 is selectively etched using a photosensitive resin to form an opening 30 above the pad electrode 12.
次に第１図（ｂ）に示すように、パッド電極１２を含む
半導体基板１１の全面にポリイミド等からなる耐熱性樹
脂膜１４を形成する。膜厚は１０μｍ程度で十分である
。さらに耐熱性樹脂膜１４上に感光性樹脂を付着形成し
、バンプ形成領域のみを残して感光性樹脂を除去する。Next, as shown in FIG. 1(b), a heat-resistant resin film 14 made of polyimide or the like is formed over the entire surface of the semiconductor substrate 11 including the pad electrode 12. A film thickness of about 10 μm is sufficient. Further, a photosensitive resin is deposited on the heat-resistant resin film 14, and the photosensitive resin is removed leaving only the bump forming area.
次に第１図（ｃ）に示すように、感光性樹脂１５をマス
クとして耐熱性樹脂膜１４を選択的にエツチングし、凸
状層１６を形成する。その後半導体基板１１の全面に再
び感光性樹脂１５Ａを付着形成し、開口部３０と同一の
大きさの開口部を形成する０次いで感光性樹脂１５Ａを
マスクとしてパッドを極１２及び凸状層１６の表面にＰ
ｄやＳｎ等をイオン注入し無電解メッキ用の触媒層１８
を形成する。Next, as shown in FIG. 1(c), the heat-resistant resin film 14 is selectively etched using the photosensitive resin 15 as a mask to form a convex layer 16. Thereafter, the photosensitive resin 15A is again deposited on the entire surface of the semiconductor substrate 11 to form an opening having the same size as the opening 30. Then, using the photosensitive resin 15A as a mask, pads are attached to the poles 12 and the convex layer 16. P on the surface
Catalyst layer 18 for electroless plating by ion-implanting d, Sn, etc.
form.
次に第１図（ｄ）に示すように、感光性樹脂１５Ａを除
去し１、次いで触媒層１８により選択的に金属膜として
、例えばＡｕ膜１９を無電解メッキにより形成し、凸状
層１６とＡｕ膜１９からなるバンブを完成させる。この
ように第１の実施例によれば、耐熱性樹脂とＡｕ膜より
バンブを形成するため、ボディング時の熱及び圧力によ
る応力を緩和）−１半導体基板及び絶縁膜に発生するク
ラックを低減させることができる。Next, as shown in FIG. 1(d), the photosensitive resin 15A is removed 1, and then an Au film 19, for example, is selectively formed as a metal film using the catalyst layer 18 by electroless plating, and the convex layer 16 A bump consisting of the Au film 19 is completed. In this way, according to the first embodiment, since the bumps are formed from heat-resistant resin and the Au film, stress caused by heat and pressure during bonding is alleviated.)-1 Reduces cracks that occur in the semiconductor substrate and insulating film. be able to.
第２図は本発明の第２の実施例の断面図である。FIG. 2 is a sectional view of a second embodiment of the invention.
本第２の実施例では第１の実施例と同様にパッド電極ｊ
２と絶縁膜】３とが形成された半導体基板１１上に耐熱
性樹脂からなる凸状層１６を形成し、更にその表面に無
電解メッキ用の触媒層を形成する。次にこの触媒層の表
面に無電解メッキにより、ハンダ付性の良好な第１の金
属膜として、例えばＣｕ膜３１を形成した後、第２の金
属膜としてＰ ｂ −Ｓ ｎ Ｍ ３２を形成してバン
ブを完成させる。In the second embodiment, as in the first embodiment, the pad electrode j
A convex layer 16 made of a heat-resistant resin is formed on the semiconductor substrate 11 on which the insulating film 2 and the insulating film 3 are formed, and a catalyst layer for electroless plating is further formed on the surface of the convex layer 16. Next, a Cu film 31, for example, is formed as a first metal film with good solderability by electroless plating on the surface of this catalyst layer, and then Pb-SnM 32 is formed as a second metal film. to complete the bambu.
この第２の実施例では凸状層１６上の金属をＣｕとＰｂ
−３ｎとで形成できるため、コストを低減できるという
利点がある。In this second embodiment, the metals on the convex layer 16 are Cu and Pb.
-3n, which has the advantage of reducing costs.
以上説明したように本発明は、バンブを耐熱性樹脂から
なる凸状層とその表面の金属層とにより構成することに
より、ボンディング時の熱および圧力による応力を緩和
できるため、半導体基板及び絶縁膜に発生するクラック
を低減した信頼性の高い半導体装置が得られるという効
果がある。As explained above, in the present invention, by forming the bump with a convex layer made of a heat-resistant resin and a metal layer on the surface thereof, stress caused by heat and pressure during bonding can be alleviated. This has the effect of providing a highly reliable semiconductor device with fewer cracks occurring during the process.
第１図及び第２図は本発明の第１及び第２の実施例を説
明するための半導体チップの断面図、第３図は従来例を
説明するための半導体チップの断面図である。
１１・・・半導体基板、１２・・・パッド電極、１３・
・・絶縁膜、１４・・・画然性樹脂膜、１５，１５Ａ・
・・感光性樹脂、１６・・・凸状層、１８・・・触媒層
、１９・・・Ａｕｌ１．２１・・・第】の金属層、２２
・・・第２の金属膜、２３ 、、、バンブ、２４Ａｕｌ
Ｊｉ、３ｌ−Ｃｕ膜、３２ ・−Ｐ ｂ −Ｓ ｎ膜。1 and 2 are cross-sectional views of a semiconductor chip for explaining first and second embodiments of the present invention, and FIG. 3 is a cross-sectional view of a semiconductor chip for explaining a conventional example. 11... Semiconductor substrate, 12... Pad electrode, 13.
... Insulating film, 14... Striking resin film, 15, 15A.
... Photosensitive resin, 16 ... Convex layer, 18 ... Catalyst layer, 19 ... Au1.21 ... Metal layer, 22
...Second metal film, 23, , bump, 24Aul
Ji, 3l-Cu film, 32·-P b -S n film.
Claims (2)
ッド電極上に形成された耐熱性樹脂からなる凸状層と、
前記凸状層表面に形成され前記パッド電極に接続する金
属層とを含むことを特徴とする半導体装置。(1) a pad electrode formed on a semiconductor substrate; a convex layer made of a heat-resistant resin formed on the pad electrode;
A semiconductor device comprising: a metal layer formed on the surface of the convex layer and connected to the pad electrode.
記パッド電極を含む全面に絶縁層を形成したのちパター
ニングし前記パッド電極上に開口部を形成する工程と、
前記開口部を含む全面に耐熱性樹脂層を形成したのちパ
ターニングし前記開口部内に開口部より幅の狭い凸状層
を形成する工程と、前記凸状層及び前記開口部に露出し
たパッド電極の表面に金属イオンを注入し無電解メッキ
用の触媒層を形成する工程と、無電解メッキにより前記
触媒層の表面に金属膜を形成する工程とを含むことを特
徴とする半導体装置の製造方法。(2) a step of forming a pad electrode on a semiconductor substrate; a step of forming an insulating layer on the entire surface including the pad electrode and then patterning it to form an opening on the pad electrode;
forming a heat-resistant resin layer on the entire surface including the opening, and then patterning it to form a convex layer narrower than the opening in the opening; A method for manufacturing a semiconductor device, comprising the steps of: forming a catalyst layer for electroless plating by implanting metal ions into the surface; and forming a metal film on the surface of the catalyst layer by electroless plating.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1210307A JPH0373535A (en) | 1989-08-14 | 1989-08-14 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1210307A JPH0373535A (en) | 1989-08-14 | 1989-08-14 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0373535A true JPH0373535A (en) | 1991-03-28 |
Family
ID=16587243
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1210307A Pending JPH0373535A (en) | 1989-08-14 | 1989-08-14 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0373535A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06140532A (en) * | 1992-10-28 | 1994-05-20 | Ngk Insulators Ltd | Substrate having bump |
| US6365500B1 (en) * | 1994-05-06 | 2002-04-02 | Industrial Technology Research Institute | Composite bump bonding |
| KR100361084B1 (en) * | 2000-01-21 | 2002-11-18 | 주식회사 하이닉스반도체 | Semiconductor package and fabricating method thereof |
| KR100417126B1 (en) * | 2001-06-01 | 2004-02-05 | 한국전자통신연구원 | Fabrication method of interconnection bump with high density and high aspect ratio |
| KR100514230B1 (en) * | 2000-05-01 | 2005-09-13 | 세이코 엡슨 가부시키가이샤 | Method for forming bump and method for making semiconductor device |
-
1989
- 1989-08-14 JP JP1210307A patent/JPH0373535A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06140532A (en) * | 1992-10-28 | 1994-05-20 | Ngk Insulators Ltd | Substrate having bump |
| US6365500B1 (en) * | 1994-05-06 | 2002-04-02 | Industrial Technology Research Institute | Composite bump bonding |
| KR100361084B1 (en) * | 2000-01-21 | 2002-11-18 | 주식회사 하이닉스반도체 | Semiconductor package and fabricating method thereof |
| KR100514230B1 (en) * | 2000-05-01 | 2005-09-13 | 세이코 엡슨 가부시키가이샤 | Method for forming bump and method for making semiconductor device |
| KR100417126B1 (en) * | 2001-06-01 | 2004-02-05 | 한국전자통신연구원 | Fabrication method of interconnection bump with high density and high aspect ratio |
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