JPH0715909B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having bumps.

[Conventional technology]

The semiconductor device having bumps can be bonded by one operation, is suitable for automation and high-speed bonding, and has a feature that the mounting volume is small.

2A to 2D are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a conventional method for manufacturing a semiconductor device.

As shown in FIG. 2A, an aluminum layer having a thickness of about 1 μm is deposited on the insulating film 2 provided on the semiconductor substrate 1 and selectively etched to provide the electrode pad 3. Next, the interlayer insulating film 4 having a thickness of 0.5 to 1.0 μm is provided on the surface including the electrode pad 3 and is selectively etched to provide the opening 5 on the electrode pad 3.

Next, as shown in FIG. 2 (b), a chromium layer 6 and a copper layer 7 for enhancing the adhesiveness with the barrier metal and the bump are formed on the surface including the opening 5 to a thickness of 0.1 to 0.2 μm, respectively. Are sequentially deposited. In this case, a titanium-palladium combination may be used instead of the chromium-copper combination.

Next, as shown in FIG. 2C, a photoresist film 8 is provided on the copper layer 7 and patterned to form an opening 9 including the opening 5 and slightly larger than the opening 5. next,
Copper is deposited on the copper layer 7 in the opening 9 by electroplating to form bumps 10. Next, the surface of the bump 10 is prevented from being oxidized and inner lead bonding is performed.
A solder plating layer 12 made of a material suitable for the above is formed.

Next, as shown in FIG. 2D, the photoresist film 8 is removed, and the bumps 10 are used as a mask to form the first and second metal layers.
Etch and remove 6,7.

[Problems to be solved by the invention]

The above-described conventional method for manufacturing a semiconductor device is excellent in that the solder plating layer formed on the surface of the bump electrode is adhesive to the bump electrode, but the thermal expansion coefficient between the solder and copper is different. Therefore, there is a problem that stress is applied to the solder plating layer, cracks are formed in the solder plating layer with the lapse of time, and the oxidation resistance is deteriorated.

[Means for solving problems]

A method for manufacturing a semiconductor device according to the present invention comprises a step of depositing a metal layer on an insulating film provided on a semiconductor substrate and selectively etching the electrode pad to provide an electrode pad, and an interlayer insulating film on a surface including the electrode pad. Providing and selectively etching to form a first opening on the electrode pad; sequentially depositing first and second metal layers on a surface including the opening; and the second metal Providing a photoresist film on the layer and patterning it to provide a second opening including the first opening and slightly larger than the first opening; and a step of forming the second opening by electroplating. Depositing a metal layer on the second metal layer to form bumps on the photoresist film around the second opening and the periphery of the second opening; and plating a lead layer on the surface of the bump. And the surface of the lead layer Forming a plating layer but configured to include a step of removing by removing the photoresist film and the second and sequentially etched first metal layer the bump as a mask.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

1A to 1D are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention.

As shown in FIG. 1A, an aluminum layer having a thickness of about 1 μm is deposited on an insulating film 2 provided on a semiconductor substrate 1 and selectively etched to provide an electrode pad 3. Next, an interlayer insulating film 4 having a thickness of 0.5 to 1.0 μm is provided on the surface including the electrode pad 3 and is selectively etched to provide an opening 5 on the electrode pad 3.

Next, as shown in FIG. 1 (b), a chromium layer 6 and a copper layer 7 for strengthening the adhesiveness between the barrier metal and the bump are formed on the surface including the opening 5 to a thickness of 0.1 to 0.2 μm, respectively. Deposit on. In this case, instead of the combination of chromium-copper, titanium-
A combination of palladium may be used.

Next, as shown in FIG. 1 (c), a photoresist film 8 is provided on the copper layer 7 and patterned to form an opening 9 including the opening 5 and slightly larger than the opening 5, and the chromium layer 6 is formed.
Using the copper layer 7 as an electrode, a copper layer is deposited on the copper layer 7 in the opening 9 by an electrode plating method to form bumps 10 on the opening and the photoresist film 8 around the periphery of the opening 9. Next, a lead layer 11 of 1 μm is formed on the surface of the bump 10 with a sulfonic acid-based plating solution.
m to a thickness of 2 to 5 μm with the same plating solution
A solder plating layer 12 having a thickness of m is deposited.

Next, as shown in FIG. 1D, the photoresist film 8 is removed, and the copper layer 7 and the chromium layer 6 are sequentially etched and removed using the bumps as a mask.

〔The invention's effect〕

As described above, the present invention intervenes the lead layer between the copper bump and the solder layer on the surface, thereby alleviating the generation of internal stress due to the solder and suppressing the diffusion of tin into the copper layer. Suppresses deterioration of oxidation resistance due to the occurrence of cracks,
It has an effect of improving reliability with respect to inner lead bonding and heat treatment in a later process.

[Brief description of drawings]

1 (a) to 1 (d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention, and FIGS. 2 (a) to 2 (d) are conventional semiconductor device manufacturing methods. FIG. 6 is a cross-sectional view of the semiconductor chip in the order of steps for explaining. 1 ... Semiconductor substrate, 2 ... Insulating film, 3 ... Electrode pad,
4 ... interlayer insulating film, 5 ... opening, 6 ... chrome layer, 7
...... Copper layer, 8 ...... Photoresist film, 9 ...... Opening, 10 ...
… Bumps, 11 …… Lead layer, 12 …… Solder plating layer.

Claims (1)

[Claims] 1. A step of depositing and selectively etching a metal layer on an insulating film provided on a semiconductor substrate to provide an electrode pad, and an interlayer insulating film provided on a surface including the electrode pad and selectively etching. And then providing a first opening on the electrode pad, sequentially depositing first and second metal layers on the surface including the opening, and photoresist on the second metal layer. A film is formed and patterned to form the first
A second opening including a second opening that is slightly larger than the first opening, and a metal layer is deposited on the second metal layer in the second opening by electroplating. A bump on the photoresist film around the second opening and the periphery of the second opening; a step of plating a lead layer on the surface of the bump; and a solder plating layer on the surface of the lead layer. A method of manufacturing a semiconductor device comprising: a step of forming the photoresist film; and a step of removing the photoresist film and sequentially etching and removing the second and first metal layers using the bumps as a mask.