JPH0697663B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device having bump electrodes.

(Prior Art) Conventionally, as a method of forming a solder bump electrode of a semiconductor flip chip element, there are a selective vapor deposition method, an electroplating method, a solder ball method, and a solder dipping method.
Japanese Examined Patent Publication No. 43-28735 or philip Tech, Rev vol 3
Known by 4 ', 74 and so on.

The reason why the selective evaporation method is that the evaporation time is long, it is difficult to control the evaporated film thickness, the solder ball method cannot reduce the diameter of the bump electrode, and the solder dip method cannot increase the bump electrode. Has not been adopted so much.

An example of a conventional bump electrode forming method for a semiconductor flip chip device by electroplating is shown in FIGS. 3 (a) to 3 (h).
Shown in. First, as shown in FIG. 3A, the semiconductor substrate 1
The Al electrode pad 3 is formed at a place where the bump on the field oxide film 2 formed above is to be formed, and the passivation film 4 is further grown by the CVD method, and then the film 4 on the Al electrode pad 3 is formed. Is removed and a through hole is opened.

Next, as shown in FIG. 3 (b), Al-Ni alloy layer 5 and Ni layer 6
Are sequentially deposited.

Next, as shown in FIG. 3 (c), masking is performed with a resist or the like to remove Ni other than the portion where the bump electrode is formed.
Layer 6 is etched to expose a portion of Al-Ni alloy layer 5.

Next, as shown in FIG. 3 (d), the exposed portion of the Al—Ni alloy layer 5 is covered with a resist 7 except the portion where the bump electrode is formed by a normal photolithography process.

Next, as shown in FIG. 3 (e), a copper plating layer 8 is plated by an electroplating method using the Al—Ni alloy layer 5 as a current conducting layer. The copper plating layer 8 usually has a thickness of about 10 μm.

After that, as shown in FIG. 3F, solder plating is performed to form bump electrodes of the solder plating layer 9. The thickness of this solder is about 40 to 60 μm.

Next, as shown in FIG. 3 (g), the resist 7 for plating is removed with a solvent, and then the exposed Al—Ni alloy layer 5 is etched.

Finally, as shown in FIG. 3 (h), the solder plating layer 9 is usually melted at a temperature of 200 to 350 ° C. to make the trapezoidal bump electrodes spherical.

Here, the intermediate metal Al-Ni alloy layer 5 is an adhesion metal to the field oxide film 2 and the Al electrode pad 3, and is an intermediate metal layer.
The Ni layer 6 and the copper plating layer 8 are diffusion barrier layers that prevent mutual diffusion between the Al electrode pad 3 and the solder layer 9.

Hereinafter, the Ni layer 6 and / or the copper plating layer 8 may be referred to as a diffusion barrier layer.

(Problems to be Solved by the Invention) However, there is a drawback that the copper plating layer 8 is etched together in the step of removing the Al—Ni alloy layer 5 shown in FIG. 3 (g). When the copper plating layer 8 is etched, the adhesion strength of the bump electrode 9 to the Si substrate is reduced, and further, the bump electrode 9 is peeled off from the Si substrate, which is not preferable in terms of bonding reliability.

As described above, as shown in FIG. 3, the metal composition of Al / -Ni-Cu- ^Pb / Sn has been exemplified as the method of forming the solder bump electrode, but Ti-Cu-Ni- ^Pb / Sn, Cr-Cu-Ni
^-There are ^Pb / Sn, etc., but in any case, the presence of copper and / or nickel layer as a diffusion barrier layer is required, and copper and / or nickel as the diffusion barrier layer is used as a current path for plating. Layer (current film)
Here, the etchant that etches the Al-Ni alloy layer 5, that is, it is very easy to be etched by acid, and the bump electrode 9 of any metal structure causes a decrease in the adhesion strength of the bump electrode 9 to the Si substrate, resulting in reliable bonding. It was not preferable in terms of sex.

That is, these drawbacks are due to continuous plating of dissimilar metals, and the soluble metal first plated is directly exposed in the resist removing step shown in FIG. 3 (g).

(Means for Solving the Problem) In order to solve the above problems, the present invention does not continuously coat the copper plating layer 8 and the solder layer 9 which form a diffusion barrier, and after the process of the copper plating layer 8 is completed, the solder is not formed. By performing photolithography for selective coating of the layers on the outer periphery of the diffusion barrier layers 6 and 8, the outer peripheral portions of the side walls of the diffusion barrier layers 6 and 8 are not exposed in the resist removing step on the outer peripheral portions of the diffusion barrier layers. It is the one.

(Operation) According to the above manufacturing method, the solder plating layer is filled in the hole formed in the outer peripheral portion of the side wall of the diffusion barrier layer, and the top surface and the side wall of the diffusion barrier layer are all covered with the solder plating layer. The Al-Ni layer forming one electrode is not eroded by the etchant of the Al-Ni layer.

(Embodiment) An embodiment of the method for manufacturing a semiconductor device of the present invention will be described below with reference to the process sectional views of FIGS. Since the steps up to the step of plating the copper plating layer 8 are the same as those in the conventional manufacturing method shown in FIGS. 3 (a) to 3 (e), the description of the manufacturing method will be omitted.

Now, as shown in FIG. 1 (i), after the copper plating layer 8 is completed, all the resist 7 for this plating is removed,
The other portions of the Ni layer 6 and the copper plating layer 8 are again covered with the resist 11 so that the outer peripheral portions 10 of the side walls are exposed. This results in holes 10
a is formed on the outer peripheral portion of the side wall.

Next, solder plating is performed as shown in FIG.
By forming a bump electrode by the solder plating layer 9, the holes 10a in the sidewall outer peripheral portion 10 of the Ni layer 6 and the copper plating layer 8 are also filled with the solder plating layer 9.

Next, as shown in FIG. 1 (k), after removing the resist 11 for plating the solder layer 9 with a solvent, the Al—Ni alloy layer 5 is etched. In this etching process, the top surface and the side surfaces of the Ni layer 6 and the copper plating layer 8 are all covered with the solder plating layer 9, so that they are not immersed in the etchant of the Al—Ni alloy layer 5.

Finally, as shown in FIG. 1 (l), the solder plating layer 9 is usually melted at a temperature of 200 to 350 ° C. to make the trapezoidal bump electrode spherical.

As described above, in the method for manufacturing a semiconductor device of the present invention, the resist is removed after the plating process of the diffusion barrier layer that is soluble in an etchant for a metal used in the semiconductor industry, for example, an acid, and then the diffusion barrier layer is removed again. A photolithography process is performed on the outer periphery of the diffusion barrier layer, and solder plating is performed so that all surfaces of the diffusion barrier layer are covered with the solder plating layer 9, and a current path layer (current film) for plating is used here.
When the Ni alloy layer 5 is etched, the diffusion barrier layer is prevented from being etched.

Next, a second embodiment will be described with reference to process sectional views of FIGS. The process of removing a part of the Al—Ni alloy layer 5, that is, the process up to FIG. 3C is the same as the conventional manufacturing method, and therefore the description thereof is omitted.

2 (m) corresponds to FIG. 3 (d), the resist 7 is subjected to photolithography for the copper plating layer 8 serving as a diffusion barrier. Use resist 7a.

Next, as shown in FIG. 2 (n), the copper plating layer 8 is plated within the range of the thickness of the resist 7a. Next, as shown in FIG. 2 (o), the resist 7a on the side wall outer peripheral portion 10 of the diffusion barrier layers 6 and 8 is masked by the mask member 12 so as to be exposed, and then developed as shown in FIG. 2 (p). Hole in the outer periphery 10 of the side wall
10a is formed. Since the following steps correspond to the steps after FIG. 1 (j), the drawings are not shown.

In the second embodiment, as seen in the first embodiment,
It can be performed without removing the resist 7 and forming the resist 11 again in the step (i).

(Effects of the Invention) As described in detail above, by performing photolithography for the solder layer 9 on the outer periphery of the Ni layer 6 and the copper plating layer 8 after the step of forming the copper plating layer 8, the photolithography is performed in the resist removing step. The diffusion barrier layers 6 and 8 are not exposed. As a result, the current path layer for plating (here, Al
-When etching the Ni layer 5), this diffusion barrier layer 6,8
Will not be etched. Therefore, the adhesion strength of the bump electrode to the silicon substrate does not decrease, and the yield is high,
A highly reliable bump electrode process becomes possible. It also exhibits a highly reliable barrier effect and can improve the reliability of flip chip bonding to a substrate.

[Brief description of drawings]

FIGS. 1 (i) to 1 (l) are process cross-sectional views of a method for manufacturing a semiconductor device showing a first embodiment of the present invention, and FIGS.
(P) is a process sectional view of a method for manufacturing a semiconductor device showing a second embodiment of the present invention, and FIGS. 3 (a) to (h) are process sectional views of a conventional bump electrode forming method. 1 ... Semiconductor substrate, 2 ... Field oxide film, 3 ... Al
Electrode pad, 4 ... Passivation film, 5 ... Al-Ni alloy layer, 6 ... Ni layer, 7 ... Resist, 7a ... Positive resist, 8 ... Copper plating layer, 9 ... Solder plating layer, Ten…
… Sidewall peripheral part, 10a …… hole, 11 …… resist, 12 …… mask member.

Claims (5)

[Claims] 1. A first region in a first region on a main surface of a semiconductor substrate.
Forming a conductive layer, forming a second conductive layer on the main surface and the first conductive layer, and diffusing on the second conductive layer corresponding to the first region. Forming a barrier layer, and forming a second layer on the diffusion barrier layer and on a side surface of the second region corresponding to a second region on the main surface surrounding the first region.
Forming a third conductive layer to be a bump electrode terminating on the conductive layer, and selecting the second conductive layer that is not covered with the third conductive layer using the third conductive layer as a mask. And a step of physically removing the semiconductor element. 2. A step of forming a first insulating film on the main surface of the semiconductor substrate, and a step of forming the first conductive film on the first insulating film corresponding to a first region on the main surface. A step of forming a layer, a step of forming a second insulating film having an opening in a predetermined portion of the upper surface of the first conductive layer on the first insulating film, The second layer is formed on the second insulating film.
The method of manufacturing a semiconductor element according to claim 1, further comprising the step of forming a conductive layer. 3. A step of heating the second conductive layer to form a bump electrode after the step of selectively removing the second conductive layer, the method comprising the steps of: A method of manufacturing a semiconductor device according to the item 1. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the first conductive layer is an electrode pad, and the second conductive layer is a current path layer. 5. The step of forming the third conductive layer comprises the step of forming the second conductive layer.
Selectively forming a mask member on the second conductive layer corresponding to a third region on the main surface surrounding the region, the side surface of the diffusion barrier layer, the side surface of the mask member, and the side surface of the mask member. 2. A semiconductor element according to claim 1, further comprising a step of filling an opening formed of an upper surface of the second conductive layer corresponding to the second region with the third conductive layer. Production method.