JPS62160744A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the reliability of bonding without exposing a diffused barrier layer in a resist removing process, in manufacturing a semiconductor element having a bump electrode, by performing photolithography for a solder layer after a copper plating process at the outer surfaces of an Ni layer and the copper plated layer. CONSTITUTION:After copper plating, resist for this plating is all removed. The other part is coated with resist 11 again so that an outer surface parts 10 of the side walls of an Ni layer 6 and a copper plated layer 8 are exposed. As a result, holes 10a are formed at the outer surface parts of the side walls. As a result, holes 10a are formed at the outer surface parts of the side walls. Then solder plating is performed, and a bump electrode is formed by a solder plated layer 9. The holes 10a of the outer surface parts 10 of the side walls are filled with the solder 9. Then, the resist 11 for plating of the solder 9 is removed with solvent. Then an Al-Ni alloy layer 5 is etched. In this etching process, the top surfaces and the side surface of the Ni layer 6 and the copper plated layer 8 are not eroded with etchant since they are all coated with the solder plated layer 9. Finally, the solder plated layer 9 is dissolved ordinarily at 240-350 deg.C, and a trapezoidal bump electrode is turned into a spherical shape.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention is based on bread! The present invention relates to a method of manufacturing a semiconductor element having electrodes.

(Prior Art) Conventionally, methods for forming solder bump electrodes of semiconductor flip-chip devices include selective vapor deposition, electroplating, solder ball method, and solder dip method.
Special Publication No. 43-28735 or Philip
It is known from Tech+ Rev vol 34'+ 74 and the like.

The selective vapor deposition method requires a long vapor deposition time and is difficult to control the deposited film thickness, the solder sol method cannot reduce the diameter of the bump electrode, and the solder dip method cannot increase the height of the bump electrode. Not widely adopted.

An example of a method for forming bump electrodes of a semiconductor free-lag chip element using the conventional electroplating method is shown in FIGS. 3(a) to 3(h).
Shown below. First, as shown in FIG. 3(,), a semiconductor substrate 1
At the place where a bump is to be formed on the field oxide film 2 formed above, an At electrode/metal 3 is formed, and then a carbon oxide film 2 is formed.
After growing the passivation film 4 by the VD method, the film 4 on the At electrode/IP pad 3 is removed and a through hole is opened.

Next, as shown in FIG. 3(b), an At-Ni alloy layer 5, an N
The i-layer 6 is sequentially deposited.

Next, as shown in FIG. 3(c), masking is performed with a resist or the like to remove the N
The i-layer 6 is etched to expose a portion of the At-Ni alloy layer 5.

Next, as shown in FIG. 3(d), the At-Ni alloy layer 5
At the exposed portions, the resist 7 is removed by a normal photolithography process except for the portions where bump electrodes are to be formed.

Next, as shown in FIG. 3(,), a copper plating layer 8 is plated by electroplating using the At--Ni alloy layer 5 as a current conducting layer. This copper plating layer 8 usually has a thickness of about 10 μm.

Thereafter, as shown in FIG. 3(f), solder plating is performed to form bump electrodes of the solder plating layer 9. The thickness of this solder is approximately 40 to 60 μm.

Next, as shown in FIG. 3(g), after removing the plating resist 7 with a solvent, the exposed At--Ni alloy layer 5 is etched.

Finally, as shown in Figure 3 (h), usually 240 to 35
The solder plating layer 9 is melted at a temperature of 0° C. to make the platform-shaped bump electrode into a spherical shape.

Here, the intermediate metal At-Ni alloy layer 5 is a metal that adheres to the field oxide film 2 and the At electrode pad 3, and the intermediate metal layer 6 and copper plating layer 8 are the metal that adheres to the At electrode pad 3 and the solder layer 9. It is a diffusion barrier layer that prevents mutual diffusion of .

Hereinafter, the Ni layer 6 and/or the copper plating layer 8 may also be referred to as a diffusion barrier layer.

(Problems to be Solved by the Invention) However, there is a drawback that the copper plating layer 8 is etched together with the step of removing the At-Ni alloy layer 5 shown in FIG. When the copper plating layer 8 is etched, the adhesion strength of the bump electrode 9 to the SL substrate decreases, and furthermore, the bump electrode 9 peels off from the substrate 81, which is unfavorable from the viewpoint of reliability of female bonding.

As shown in FIG. 3, the metal composition of A4/-Ni-Cu-Pb/Sn has been exemplified as a method for forming solder bump electrodes, but other typical metal compositions include Ti-C
u-Ni-Pb/Sn, Cr-Cu-Ni-Pb/
In either case, a copper and/or nickel layer is required as a diffusion barrier layer. layer (current film)
Here, it is very easily etched by the etchant that etches the At-Ni alloy layer 5, that is, acid, and the adhesion strength of the bump electrode 9 to the substrate 81 decreases in any of the bump electrodes of any metal configuration, resulting in a reduction in bonding. Preferable in terms of reliability.

It wasn't.

That is, these drawbacks are due to the fact that when different metals are continuously plated, the soluble metal to be plated first is directly exposed in the resist removal process shown in FIG. 3(g).

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention does not continuously plate the copper plating layer 8 and the solder layer 9, which form a diffusion barrier, but after the copper plating layer 8 process is completed, the solder is removed. By performing photolithography on the outer periphery of the diffusion barrier layers 6 and 8 for selective coating of layers, the outer periphery of the side walls of the diffusion barrier layers 6 and 8 is prevented from being exposed during the resist removal process. This is what I did.

(Function) According to the above manufacturing method, the holes formed on the outer periphery of the side walls of the diffusion barrier layer are filled with the solder plating layer, and the top surface and side walls of the diffusion barrier layer are all covered with the solder plating layer, so that the plating current can be applied. When etching the At--Ni layer constituting one electrode, the At--Ni layer is not corroded by the etchant.

(Example) Hereinafter, an example of the method for manufacturing a semiconductor element of the present invention will be described based on process cross-sectional views of FIGS. 1(i) to (4).

Incidentally, since the steps up to the plating process of the copper plating layer 8 are the same as those in the conventional manufacturing method shown in FIGS.

Now, as shown in FIG. 1(i), after the copper plating layer 8 is completed, the resist 7 for this plating is completely removed.
Other parts are again covered with a resist 11 so that the side wall outer peripheral part 10 of the 81 layer 6 and the copper plating layer 8 is exposed. As a result, a hole 10a is formed in the outer periphery of the side wall.

Next, perform solder plating as shown in Figure 1 (j),
A bump electrode is formed by the solder plating layer 9 and the N4 layer 6 is formed.
The inside of the hole 10a in the side wall outer peripheral portion 10 of the copper plating layer 8 is also filled with this solder plating layer 9.

Next, as shown in FIG. 1(k), after removing the renost 11 for plating the solder layer 9 with a solvent, the At--Ni alloy layer 5 is etched. In this etching process, the top and side surfaces of the 81 layer 6 and the copper plating layer 8 are covered with a solder plating layer 9.
Since it is completely covered with the etchant of the AL-Ni alloy layer 5, it is not immersed in the etchant of the AL-Ni alloy layer 5.

Finally, as shown in Figure 1 (4), the temperature is usually 240~350℃.
The solder plating layer 9 is melted at a temperature of 100 to turn the table-shaped bump electrode into a spherical shape.

As described above, in the semiconductor device manufacturing method of the present invention, after the plating process of the diffusion barrier layer, which is soluble in metal etchants such as acids used in the semiconductor industry, the resist is removed and the diffusion barrier layer is re-plated. A photolithography process is performed on the outer periphery, and solder plating is performed so that all surfaces of the diffusion barrier layer are covered with a solder plating layer 9, and a current path layer (current film) for plating is formed.
This is to prevent the diffusion barrier layer from being etched when etching the t-Ni alloy layer 5.

Next, a second embodiment will be described using process cross-sectional views shown in FIGS. 2(c) to 2(p). Note that the steps up to the step of removing a portion of the AL-Ni alloy layer 5, ie, the step shown in FIG. 3(C), are the same as the conventional manufacturing method, and therefore the description thereof will be omitted.

Now, in FIG. 2(c), corresponding to FIG. 3(d), photolithography is performed on the resist 7 for the copper plating layer 8 which will serve as a diffusion barrier, but in this example, the resist is of a gauge type. Use resist 7a.

Next, as shown in FIG. 2(n), a copper plating layer 8 is plated within the thickness of the resist 7a. Next, Figure 2 (
, ), the side wall outer peripheral portion 10 of the diffusion barrier layers 6, 8
A hole 10a is formed in the outer peripheral portion 10 of the side wall by masking with a mask member 12 so that the register 7a is exposed and developing as shown in FIG. 2(p). The following process is shown in Figure 1 (j
) Since it corresponds to the subsequent steps, the presentation of the figure is omitted.

In the second embodiment, as seen in the first embodiment, (i
) process can be performed without removing the resist 7 and forming the resist 11f again.

(Effects of the Invention) As described in detail above, by performing photolithography for the solder layer 9 on the outer periphery of the 81 layer 6 and the copper plating layer 8 after the process of copper plating layer 8 is completed, this process can be performed in the resist removal process. The diffusion barrier layers 6 and 8 are not exposed. As a result, when etching the current/gas layer for plating (here the At--Ni layer 5), the diffusion barrier layers 6, 8 are no longer etched. Therefore, it is possible to perform a highly reliable bump electrode process with a high yield without reducing the adhesion strength of the bump electrode to the silicon substrate. It also exhibits a highly reliable barrier effect and can improve the reliability of flip chip bonding to a substrate.

[Brief explanation of drawings]

FIGS. 1(i) to (4) are process cross-sectional views of a method for manufacturing a semiconductor device showing a first embodiment of the present invention, and FIGS. 1(p) to (p) show a second embodiment of the present invention. FIGS. 3(a) to 3(h) are cross-sectional views of the process of the method for manufacturing a semiconductor device, and are cross-sectional views of the conventional banzoelectric molding method. 1... Semiconductor substrate, 2... Field oxide film, 3...
...htM, Gokuhatsuto, 4...Nogusivation film,
5...At-Ni alloy layer, 6...Ni layer, 7...
・Resist, 7a...Positive Renost, 8...Copper plating layer, 9...Solder plating layer, 10...Side wall outer periphery, 10a...Hole, 11...Resist, 12...・
Mask parts. Patent Applicant Oki Electric Industry Co., Ltd. J, 96.8fis No. 2.1*Ri'j'J 74s
i Engineering JX 1ml! l II 1 ≦ Mizj5 Ming J 2
,, Bunkata An t4i "" is written, LA'z-Tunaie
Figure 2 Sub〉G, r) l gun 7° electrical collection 1 Saishin G large. 111J row Ichimeki figure 3

Claims (1)

[Claims] (1) a. Forming a second insulating film having an opening on the conductive layer formed on the first insulating film on the main surface of the semiconductor substrate, and b. Passing the conductive layer through the opening. and the second
forming a metal layer forming a conductive path for plating extending on the insulating film; c. forming a diffusion barrier metal layer slightly larger than the metal layer on the metal layer at a portion corresponding to the conductive layer; d. Forming a mask member on the main surface on which the diffusion barrier layer is formed, exposing the top and side surfaces of the diffusion barrier layer and covering the remaining main surface; e. The mask. forming a bump electrode constituent metal by plating on the upper and side surfaces of the diffusion barrier layer that are not covered with the member; f. removing the mask member and selectively removing the exposed metal layer; g. A method for manufacturing a semiconductor device, comprising the step of heating the bump electrode forming metal to form a spherical bump electrode. 2. The semiconductor device according to claim 1, wherein the diffusion barrier metal layer is composed of a two-layer film of Ni and Cu, and the Cu has the same size as the Ni and is formed on the Ni by plating. manufacturing method.