JPS6019810B2 - Buffer memory control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a buffer memory control system, and particularly to a buffer memory control system that is located between a data channel processing device and a main memory, and is used to store data read from the main memory in blocks of a predetermined size. In a buffer memory configured to store the data transferred from the data channel processing device to the main memory in units of blocks, the data can be efficiently transferred from the data channel processing device to the main memory. The present invention relates to a buffer memory IJ control method that allows

FIG. 1 shows an example of a data processing system to which the present invention is applied, in which a central processing unit (CPU) and a data channel processing unit (hereinafter abbreviated as DCH) are connected to a main memory (M5M) via a storage control device. is connected to.

A magnetic disk, magnetic tape, etc. are connected below the DCH. Further, a buffer memory (not shown) is provided at an intermediate location between the main memory and the DCH, for example, in the storage control device. When the DCH requests data transfer from the main memory, the storage control device checks whether the address of the requested data is registered in the tag part of the built-in buffer memory, and if it is registered, transfers it from the buffer memory. If it is not registered, the block containing the requested data is loaded from the main memory as a block, sent to the DCH, and registered in the buffer memory. As long as the data requested by DCH is registered in the buffer memory, the data read from the buffer memory is transferred to the DCH, and only when unregistered data is requested, a block is loaded from the main memory. Data is transferred from the main memory to the DCH more quickly than when the DCH is not used. Also, when the DCH transfers data to the main memory, the storage control device checks whether the transfer destination address is registered in the buffer memory, and if it is registered, the data is transferred from the DCH to that area of the buffer memory. Write data, and if it is not registered, it will be an empty space in the buffer memory. A block or an optimal block is found, a new address is registered in the tag section, and the data transferred from the DCH is written. The DCH determines that the data transfer to the main memory is complete when the data is written to the buffer memory, and the process proceeds to the next step, so the data transfer from the DCH to the main memory is faster than when the buffer memory is not used. This will be done promptly. Data written from the DCH to the buffer memory must be transferred to the main memory at some point, and the transfer to the main memory is performed in blocks of the buffer memory. This is called a block store. Float store is basically performed after a certain block is filled with data to be transferred from DCH, and if there is no longer an area in the buffer memory to transfer data from DCH, or if the main memory is used to transfer data to DCH. When there is no longer an area on the buffer memory to which a block should be loaded from the DCH, a block that is not filled with data from the DCH may inevitably be flock-stored to the main memory. In this case, the main memory is partially written, and the data that had been transferred from the DCH up to that point is written to the main memory, and the other parts of the block remain the old data. Now, considering the buffer memory created between OCH and main memory, in data transfer between main memory and magnetic disk, magnetic tape, etc., block load from main memory, block store from DCH, etc. The data in the blocks of the buffer memory used in the above must not be kept in the buffer memory for a long time, but must be quickly transferred to a magnetic disk, magnetic tape, etc., or to the main memory.

SUMMARY OF THE INVENTION An object of the present invention is to make it possible to efficiently transfer data in a buffer memory written from a DCH to a main memory. The data extracted from the main memory is stored in blocks of a predetermined size, and the data transferred from the data channel processing device to the main memory is stored in blocks for one day. In the buffer memory configured in the buffer memory, a flag is provided corresponding to each block on the buffer memory to indicate that the block has been retrieved or stored by the data channel processing device, and
An address queue is provided which sequentially holds the addresses in the buffer memory of the blocks to which the flag has been given by the storage operation, and the blocks in the buffer memory are stored in accordance with the addresses held in the address queue.

The present invention is characterized in that the contents of the message are read and transferred to the main memory. First, an overview of the present invention will be explained below.

The data transferred from the DCH to the main memory is data from the magnetic disk pack device or magnetic tape device, and these data are transferred to consecutive areas of the main memory in ascending or descending order. In many cases, whether a block of the buffer memory is filled with data transferred from the DCH is determined by detecting that a write request from the DCH is made for the last data in the block. If the address of the write request from DCH indicates the first or last address in the block, and that block has already been registered, it is determined that the block is filled with the data transferred from DCH, and will be described later. The E flag of the tag section is turned on and the address in the buffer memory is written into the address queue provided in the present invention. Addresses in the buffer memory written to the address queue indicate blocks of buffer memory that require transfer to main memory, and are read out in the order written to the address queue, and the buffer memory indicated by the address is The block is transferred to main memory. Data transfer from the buffer memory to the main memory is given a lower priority than other main memory accesses, so the data transfer is performed using free time in the main memory. When the transfer to the main memory is completed, the block disappears from the buffer memory, and another block can be registered in its storage location. It is best if the address queue has the same number of stages as the number of blocks in the buffer memory, but the number of stages may be less than the number of blocks depending on the quantity. At this time, there may be blocks that cannot be placed in the address queue even if the E flag is attached, but when an interrupt occurs from the DCH indicating that the data transfer has ended, the untransferred blocks will be transferred to the main memory. Therefore, no logical problem arises. Note that when data is transferred from the main memory to the DCH, the E flag is assigned if the requested address of the DCH indicates the last address in the block and the block has already been registered.
The E flag can be used to replace blocks in buffer memory. Hereinafter, the present invention will be explained with reference to the drawings. FIG. 2 shows a buffer memory control circuit according to an embodiment of the present invention.
FIG. 3 is a diagram for explaining the address configuration in the embodiment, and FIG. 4 is a diagram showing the configuration of the buffer memory in the embodiment.

In FIG. 2, 1 is a data section of the buffer memory, 2 is a tag section of the buffer memory, 3 is an address comparison circuit, 4 is an E flag setting circuit, 5 is an address queue, 6 is an address queue control circuit, and 7 to 11 are gate, 12 is an address line from DCH, 13 is a data line from DCH, 14 is a data line from main memory (MEM), 15 is V which will be described later.
Flag, C flag write line, 16 is E flag write line, 17 is data line to DCH, 18 is data line to MEM, 19 is address queue write control line, 20 is address queue output control line, 21 is a queue write request line, 22 is an address line to M top M, 0 to 28 on each line, BO to BI
indicates a bit position which will be described later in FIG. In the preferred embodiment, the buffer memory is set-associative, and its address structure is allocated as shown in FIG.

In other words, bits 0 to 20 of the address are the tag address,
Bits 21 to 25 are set in the buffer memory.
Address, pits 26-28 are blocked (BhOCK)
Of these, 8 bytes B address, bits 29 to 31 are bytes (B
y) address. Further, as addresses within the buffer memory, bits BO to BI are addresses within the buffer memory. BLLOCK address, bits 21-2
5 is the set address and bit in the buffer memory, 26 to 28 are the 8 bytes in the block (BLOCK) (
B) It is considered an address. As shown in FIG. 4, the buffer memory is divided into sets 0 to 31, and each set consists of four blocks (BLOCK).

Furthermore, each block of the data part is 8 bytes (Byte)
x8=64 bytes. In the evening part, V, C,
It holds each flag of E. The V flag indicates that the block data is invalid when it is "0" and the data is valid when it is "1", and the C flag indicates that the block data is DCH when it is "0".
“1” indicates that no writing is being performed.
The E flag indicates that writing has been performed when it is "0", indicating that the block is still used by DCH, and "1" indicates that the block has been exhausted by DCm. The operation in FIG. 2 is as follows.

When a data transfer request to the DCH occurs, address line 1
The contents (tag address) of the tag section 2 are read out for four blocks by the set address of the 21st to 25th bits 5 of the address above.

And this exposed tagua dress and address line 12
The 0th to 20th bits above are compared by the address comparison circuit 3. Comparison is performed for four blocks at the same time, and if there is a match, the gate 10 is controlled by the output of the address comparison circuit 3, and the corresponding one of the four blocks of data read simultaneously from the data section 1 is Only block data is selected. Selected data is gate 11
, and sent to the DCH via data lines 1 and 7. At this time, the 8B address in the block on the address line 12 (
If the 26th to 28th bits) indicate the last address of the block, the E flag setting circuit 4 detects this and turns the E flag of the tag section 2 on to 0 ("1").

On the other hand, if there is no match as a result of the comparison by the address comparison circuit 3, the desired data is block loaded from the main memory and the block address and block data are registered in the tag section 2 and data section 1, respectively. Evening. Next, when a data transfer request from the DCH to the main memory occurs, the tag section is read in the same manner as above, and as a result of the comparison by the address comparison circuit 3, if a matching block exists, the corresponding block in the data section 1 is Data sent through the open data line 13 is written.

At this time, the 8B address in the block on the data line 12 (
When the 26th to 28th bits) indicate the beginning or end of the block, the E flag setting circuit 4 detects this and turns on the E flag of the tag section 2 (1"), and also sets the address A queue write request is sent to the queue control circuit 6. As a result, the address key control circuit 6 writes the buffer memory addresses (BO to B) to the address queue 5.
1, bits 21-25). On the other hand, as a result of the comparison by the address comparison circuit 3, if the address does not match the address in the block 11 section 2, an appropriate block is found and the transfer data from the DCH is written in the data section 1, and at the same time, it is written in the tag section 2. Make sure to register your address. The C flag of the tag section 2 is given when data is written from the ZDCH to the buffer memory, and indicates that the data in that block is data that should be transferred to the main memory. The address queue 5 stores the address in the buffer memory of the block to which the E flag has been assigned among the data to be transferred to the main memory, so the buffer memory is The block filled by the DCH above can be transferred to main memory. FIG. 5 shows a specific example of the E flag setting circuit 4. In the figure, there are three decoder circuits, 34 is an AND gate, and 35 and 36 are OR gates.

Decoder circuit 3, block address, bit 2
6 to 28 and outputs two signals indicating the values "0" (the beginning of the block) and "7" (the end of the block). Gates 31 to 36 receive the above-mentioned E flag write request,
This is a logic circuit for generating queue write requests, and its operation is easily understood, so a detailed explanation will be omitted.
FIG. 6 shows a specific example of the address queues 5 and 3 and the address queue control circuit 6 shown in FIG. 42 is a reading output counter, 43 and 44 are eleven circuits, 45 is a subtracter, 46 is an SR flip-flop, 47 to
50 is an AND3 circuit, 51 is an OR circuit, 52 is a write input line, 53 is an output line, 54 is a queue write address line; 55 is a write instruction line; 56 is a queue output address line;
57 is a read instruction line.

The address queue is composed of N stages, and writing to the queue 41 and logical output from the queue are performed by addresses from the write counter 41 and the read counter 42, a write instruction line 55, and a discussion instruction line 57, respectively.

The write counter 41 and the issue counter 42 increment each time a write to the queue and an issue are made, respectively.
When it increments to N-1, it returns to 0 at the next write or logical logic. In the initial state, the values of the write counter 41 and the output counter 42 are both "0", and at the same time, the SR flip-flop (FULL) 46 is also "0".
The subtracter 45 monitors the values of both counters, and when the difference between the two is not "0" or FULL=1,
The queue can be read only when the main memory is free. When a queue write request is issued, if FULL=0, writing to the queue is performed. SR flip-flop (
FULL) 46 indicates that all the queues are filled, and the difference between the values of both counters is ``minus 1''.
? '(=0), and when a write request comes while a request for discussion is inhibited while waiting in the main memory, FULL=1 is set.

When FULL=1 is set for one day, write requests are prohibited, and when read requests are allowed, FULL=0 is reset. The subtracter 45 calculates (value of write counter) - (value of issue counter), and the result is the number of pieces of address information accumulated in the queue. "-1" indicates that the number of pieces of address information is (N-1), and indicates that there is only one empty space in the queue.
As explained above, according to the present invention, the E flag is provided in the tag section of the buffer memory, and an address queue is provided to store the address in the buffer memory of the block filled with data by the DCH. , it is possible to efficiently transfer data from the DCH to the main memory.

[Brief explanation of drawings]

FIG. 1 is an example of a data processing system to which the present invention is applied, FIG. 2 is a buffer memory control circuit of an embodiment according to the present invention, FIG. 3 is a diagram illustrating the address structure in the embodiment, and FIG. 4 is an implementation example. FIG. 5 shows a specific example of an E flag setting circuit, and FIG. 6 shows a specific example of an address queue and an address queue control circuit. In FIG. 2, 1 is the data section of the buffer memory, 2
is the tag part of the buffer memory, 3 is the address comparison circuit, and 4 is the tag part of the buffer memory.
1 is an E flag setting circuit, 5 is an address queue, and 6 is an address queue control circuit. Figure 1 Figure 2 *3 Figure 4 Figure S Figure 5

Claims (1)

[Claims] 1 Located between the data channel processing device and the main memory, it stores data read from the main memory in blocks of a predetermined size, and also transfers data from the data channel processing device to the main memory. In the buffer memory configured to temporarily store the blocks as a unit, a flag is provided corresponding to each block on the buffer memory to indicate that the block has been read out by the data channel processing device or has been completely stored. , an address queue is created which sequentially holds the addresses in the buffer memory of the blocks to which the flag has been given by the storage operation, and the contents of the blocks in the buffer memory are read using the addresses held in the address queue. A buffer memory control method characterized in that the buffer memory is transferred to a main storage device.