JPS6019816B2 - microprogram control adapter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microprogram control device in a data processing device, and more particularly to a microprogram control adapter that logically connects an internal bus and an external interface of a control device.

In general, a computer system consists of a central processing unit, various peripheral devices, and a peripheral control device located between the peripheral devices and the central processing unit.The central processing unit and peripheral control device are connected to a system called the 1/0 interface. A unique general purpose interface is defined on each device as an external interface.

Conventionally, this type of external interface control has often implemented unique control logic for each type of peripheral control device, and the circuits specific to the connected peripheral device and the control circuit for the external interface often coexist. There were many. For this reason, when peripheral devices are improved due to advances in technology, the control device has to be changed accordingly. In addition, recently, technological innovations in microprocessors and various LSIs have been remarkable, and each device that makes up a computer system has its own processor, and it has come to be controlled by microprograms, but a communication method between microprograms has been established. This method was unique to each device.

An object of the present invention is to provide a firmware-controlled data processing device employing the above-mentioned microcomputer or the like, which has versatility as a means for connecting an internal bus in the device and an external interface, and which is connected by an external interface. An object of the present invention is to provide an adapter for coupling an external interface to an internal bus, which eliminates the above-mentioned drawbacks by enabling communication between microprograms between two firmware-controlled devices.

In order to achieve the above object, the microprogram control adapter according to the present invention provides a microprogram control adapter for a virtual register that holds the base address of a virtual register defined at an arbitrary address in the memory of a peripheral control device that is controlled by a microprogram. Means for determining the address in memory of a particular virtual register based on the contents of the base address register and control information given from an external interface defined between the central processing unit and the peripheral control unit; It has a buffer address register and a data length register for storing the data buffer address and data buffer length defined in A means for generating an interrupt and a microprogram that executes independently from the microprograms on the control device and central processing unit side, has visibility from the two microprograms, and synchronizes the microprograms. It has a general-purpose information register as a storage register for information defined between two microprograms, and is configured to enable general-purpose communication between two microprograms.

According to the above configuration, the object of the present invention can be completely achieved.

In addition to the adapter according to the present invention, "having visibility to the microprograms on the peripheral control device side and the central processing unit means that it is accessible from both microprograms, and this is the basic principle of the present invention. In other words, the microprogram of the central processing unit that accesses this adapter via the external interface and the microprogram of the peripheral control unit that controls this adapter via the internal bus can communicate.

Hereinafter, the present invention will be explained in more detail by giving typical examples of the present invention.

FIG. 1 is a block diagram conceptually showing the positioning of the external interface/internal bus coupling adapter IQ2 of the present invention in a data processing system, and shows one of the ideal embodiments of the present invention.

The central processing unit 101 and the peripheral control unit 111 are connected through an external interface IQ9.

The peripheral control device 111 is a peripheral control device processor 103.
and internal bus 110, random access memory RAMI04 used as virtual registers for storing microprograms and working area data buffers, and peripheral devices (
i) Peripheral device adapter for connecting 107, 108 (i) 105, 106 and external interface/internal bus coupling adapter 102 of the present invention for coupling external interface 109 and internal 110. The peripheral device adapters (i) 105 and 106 are controlled by a microprogram stored in RAMI04 with a minimum amount of hardware that has a unique control circuit depending on the type of peripheral device to be connected. In order to understand the physical configuration as shown in Figure 1, peripheral device adapter (i) 105, 1 can be configured depending on the type of peripheral device.
By replacing 06, it can easily become any peripheral control device in terms of hardware. Note that both the virtual register and the data buffer are defined on the RAMI04 in the peripheral control device 111, and output data to the peripheral device, for example, is stored in the data buffer. In this case, the virtual register stores command information that instructs how to process input/output data.

The base address register for the virtual register is RAMI04.
It is used to determine the base address of the virtual register defined above, the address in RAMI04 of the data buffer is specified by the buffer address register, and the length of input/output data is specified by the data length register.

In the transfer of input/output data, when the corresponding information is set in each register by the microprogram as described above, the internal bus control circuit, external interface control circuit, data length register countdown, and data length register countdown Depending on the function, etc., it can operate without the control of the microprogram.

After operating independently, it is clear that there is no need to be controlled by the microprogram until the interrupt signal is generated, and the interrupt signal is used as an opportunity to synchronize with the microprogram.

FIG. 2 is a detailed block diagram showing an embodiment of an adapter for coupling an external interface to an internal bus according to the present invention, in which an external interface control line 201 and an external interface information line 202 correspond to the external interface 109 in FIG.

Also, internal bus data 219, internal bus address line 220
, the internal bus control line 221 corresponds to the internal bus 110'.

First, access to this adapter from the external interface is performed using the following procedure.

Control information is set in the control information register 205 and a register to be accessed is selected. Next, the write information to the corresponding register is sent onto the external interface information line.

Conversely, when reading the contents of a register, this is possible by selecting the register to be accessed from the control information register 205 and then reading the data on the external interface information line.

Control lines 1-n and data lines 1-1 in FIGS. 3 and 4 are time charts showing the access flow.
Control lines 1-1 and 1-2 are external interface information lines 2
Signal line representing the direction of information on 02, control line 1-3,1
1-4, 1-6, and 1-6 indicate the types of information on the external interface information line 202.

Control line 1 indicates that control lines 1-3 and 1-4 are control information.
-5, 1-6 indicate other data. The control information decoding circuit 206 is a decoder that decodes the contents of the control information register 205 according to the definition of control information.

An example of the definition of control information is shown below. In this embodiment, for convenience of explanation, the external interface information line is 8 bits wide, the internal bus data line is 8 bits wide, and the internal bus address line is 20 bits wide.

Since the control information is transferred using the external interface information line 202, 8 bits are available. Bit 0・
...Register access direction specification: 0 When writing to register: 1: register bit 1...Real register/virtual register specification: 0 When register specification: 1, virtual register specification Hit Handwritten Shiota summary ~#6 Snake lock possible (inner register #0 is designated as data buffer) If the control information is defined as above, the control information decoding circuit 2
06 outputs the READ/WRITE status determination signal 223 in the state of bit 0, and the bus request signal 224 in the state of bit 1.
A register selection signal 222 is output according to the states of bits 2-7.

The real register defined by the control information refers to a register existing in the external interface internal bus coupling adapter.

It also points to some suitable location in memory defined in the virtual register RAMI04. When bit 1 of the control information is "1", the location of virtual register #n is that bits 2 to 7 of the control information are the lower 6 bits of the address as the virtual register address 217, and the upper 14 bits are the virtual register base address register 216. The contents of the address are determined by the customer and output on the internal bus address line 22 when the virtual register is accessed. In this embodiment, the virtual register base address register 216 is determined by treating the upper 6 bits as 0 at all times and setting the remaining 8 bits in advance from the microprogram.

It is easily understood that the address of the virtual register can be set to an appropriate address depending on the circumstances of the device.

In this embodiment, where the flow of accessing the virtual register from the external interface is shown in FIGS. 3 and 4, the width of the outside of the virtual register is set to 1 byte to facilitate understanding.

FIG. 3 is a time chart of reading the virtual register, and FIG. 4 is a time chart of writing to the virtual register. Control line 2-1, 2-2
, 2-3, 2-4, and 2-5 indicate internal bus control lines 221, which are controlled by the internal bus control circuit 214. Data line 2-1 represents internal bus data line 219. control line 2
Reference numeral 11 is a signal for requesting the adapter to occupy the internal bus, and control line 2-2 indicates that bus occupation is permitted, and upon permission, the control line 24 declares that the bus is occupied. Access memory during this time.

The direction of access is indicated by controls 2-5. Register #0 specified by the control information is used when accessing the data buffer area in RAMI04.

By setting the data length to be transferred in the data length register 209 and the address of the start of the area to be transferred in the buffer address register 215 in advance, the above-mentioned virtual register access can be performed using the control information from the external interface. Data buffers defined on RAM 104 are accessed by a similar sequence. After processing one byte, the data length register 209 is counted down, the address of the buffer address register 215 is updated, and the sequence of FIGS. 3 and 4 is repeated for the number of bytes to be transferred.

When the content of the data length register 209 becomes "0", the status holding register 2101 is set to "0", and the data is sent to the processor 0 in the peripheral control device via the internal bus control circuit 214.
It is possible to inform the microprogram by interrupting 3. In the explanation of virtual register access and data buffer access, it is assumed that they are activated by a dialog on the external interface, but real register access and interrupts in the adapter are executed between the microprogram on the peripheral control device side and the microprogram on the central processing unit side. Whether priority is given to one or the other by using a function is determined by how the microprogram is created. Appropriate information is set from the external interface side to the general-purpose information register 211, which is a real register, and an interrupt is generated from the internal bus control circuit 214 to the internal bus side.
A microprogram on the peripheral control device side reads the contents of the general-purpose information register 211 and performs a predetermined interpretation, and conversely sets an applicable information circle in the interrupt factor holding register 208 and external interface control circuit 203
By generating an interrupt signal to the external interface m via the microprogram on the central processing unit side, the microprogram on the central processing unit side reads the interrupt factor holding register, thereby making it possible for both microprograms to communicate.

As is clear from the above explanation, the adapter shown in FIG. can be freely defined. As explained above, the present invention enables a highly versatile control device by employing an adapter for coupling between an external interface and an internal bus, which enables communication means unrelated to the content of transferred information. This has the effect of increasing the efficiency of development and design.

[Brief explanation of the drawing]

FIG. 1 is a block diagram conceptually showing the positioning of the microprogram control adapter according to the present invention in a data processing system, FIG. 2 is a block diagram showing one embodiment of the microprogram control adapter according to the present invention, and FIG. 4 is a time chart of operations on the external interface and internal bus when the central processing unit reads information from the peripheral control device, and Figure 4 shows the operation time chart on the external interface and internal bus when sending information from the central processing unit to the peripheral control device. This is an operation time chart. Turtle 01...Central processing unit, 102...External interface internal bus coupling adapter, 103...Processor in peripheral control device, 104...FAM, 105...
Peripheral device adapter 1, 106... Peripheral device adapter n,
107...Peripheral device 1, 108...Peripheral device n" 109...
External interface, 110...internal bus "11
DESCRIPTION OF SYMBOLS 1... Peripheral control device, 20.1... External interface control line, 202... External interface information line, 203... External interface control circuit, 204... Data register, 205... Control information register, 20
6... Control information decoding circuit, 207... Data register 2
208...Interrupt factor holding register, 209...Data register, 210...Status holding register, 211...
General-purpose information register, 212...multiplexer circuits 1, 2
13...Register selection circuit, 214...Internal bus control circuit 215...Buffer address register, 216...
・Base address register for virtual registers, 217...
- Virtual register address, 218... Multiplexer circuit 2, 219... Internal bus data line, 220... Internal bus address line 221... Internal bus control line, 22
2...Register selection signal, 223...READ/WRI
TE designation signal, 224...Bus request signal. Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 1 The contents of the base address register for virtual registers that hold the base address of virtual registers defined at arbitrary addresses in the memory of the peripheral control unit controlled by the microprogram and the information defined between the central processing unit and the peripheral control unit. means for determining the address in memory of a specific virtual register based on control information given from an external interface, and data for storing the address and length of the data buffer defined at an arbitrary address in memory. It has a buffer address register and a data length register, and executes access to the virtual register and data buffer independently of the peripheral control unit and the microprogram on the central processing unit side in synchronization with the dialog on the external interface. It has visibility from two microprograms, a general-purpose information register as a means for generating interrupts to synchronize between these microprograms, and a storage register for information defined between microprograms, and A microprogram control adapter that enables general-purpose communication between devices.