JP3076199B2 - Buffer access control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buffer access control circuit, and more particularly to a high speed buffer access system in a system in which a FIFO (first in first out) buffer is shared among a plurality of processors.

[0002]

2. Description of the Related Art As a system for sharing a FIFO buffer between a plurality of processors, there is an example in which a FIFO buffer is used as a communication buffer between processors. Specifically, an example in a system in which tightly coupled processors are loosely coupled by a network can be given.

[0003] In this system, since there is no memory that can be commonly accessed when performing communication between the processor groups, a FIFO buffer is used as a buffer for storing communication messages between the processor groups.

In the above-mentioned system, a FIFO buffer is connected to a bus or the like as a shared resource in a processor group, and each processor is provided with a FIFO buffer divided for each communication source, each communication destination, or both. A message is exchanged with a communication partner by writing and reading a communication message.

The length of a communication message varies depending on the system, but is generally several bytes to several tens of bytes. Since the width of the system bus is about 2 to 8 bytes, writing and reading to and from the FIFO buffer are performed over a plurality of cycles.

Since the contents of the above-mentioned communication messages follow a predetermined format, they often have similar contents. In most cases, only a part of the communication messages differs.

[0007]

In the above-mentioned conventional system, the FIFO buffer is used as a communication buffer between the processors. When communication is performed between the processors, accesses from the processors concentrate on the FIFO buffer. In addition, there is a problem that the access to the FIFO buffer is delayed due to the movement of another processor.

When accessing the FIFO buffer via the system bus, the problem due to the concentration of accesses to the FIFO buffer becomes more remarkable.

An object of the present invention is to provide a buffer access control circuit which solves the above-mentioned problems, reduces the frequency of accessing the FIFO buffer, and can improve the system performance.

[0010]

SUMMARY OF THE INVENTION A buffer access control circuit according to the present invention is a buffer access control circuit for controlling access to a FIFO buffer consisting of a plurality of entries, and is defined in advance and written into the FIFO buffer. Holding means for holding a format of data, comparing means for comparing data to be written in the FIFO buffer with the format held in the holding means, and a preset number of times that a match is continuously detected by the comparing means Determining means for determining whether the number is equal to or more than the predetermined number, and writing only a specific word having a high frequency of change among data to be written to the FIFO buffer when the determining means determines that the number is equal to or more than the predetermined number. Control means.

[0011]

[0012]

[0013]

The processor stores the data to be written in the first four entries of the data to be written in the FIFO buffer in the management table, and in the writing of the fifth and subsequent entries, the write data and the management table are stored before the writing to the FIFO buffer. Is compared for each writing unit.

When a match is detected by the comparison for each write unit, the processor suppresses writing to the FIFO buffer for the word for which the match is detected.

Thus, if the data to be written to the FIFO buffer is similar, the data to be written is already
If the data has been written to the FO buffer, the writing is not performed, so that the usage rate of the system bus and the FIFO buffer can be reduced.

[0016]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. In the figure, processors 1 and 2 are connected to a FIFO buffer 4 via a system bus 100 and a data register 3 and communicate with each other via the FIFO buffer 4.

The processors 1 and 2 include control processors (μP) 10 and 20 and control memories 11 and 21 having management tables 12 and 22 for managing write data.

The data register 3 holds the write data output on the system bus 100 from the control processors 10 and 20 of the processors 1 and 2.

The FIFO buffer 4 is composed of 4 entries × 4 words × 2 sets, and each set of the FIFO buffer 4 is assigned to each of the processors 1 and 2.
Each entry of the buffer 4 is FIFO controlled by a FIFO control circuit 6.

The write data from the data register 3 is written into the FIFO buffer 4 under the control of the FIFO control circuit 6. The data stored in the FIFO buffer 4 is read out from the oldest entry data under the control of the FIFO control circuit 6 and output.

The decoder 5 decodes control signals from the control processors 10 and 20 output on the system bus 100 and notifies the FIFO control circuit 6 of the contents.

The FIFO control circuit 6 stores the FIFO buffer 4 in accordance with the notification from the decoder 5 and an external instruction.
Control.

Control processors 10 of processors 1 and 2
Reference numeral 20 reads and executes the control program written in the control memories 11 and 21, and writes communication data to the FIFO buffer 4 via the system bus 100 and the data register 3 for communication with other processors 2 and 1. Put in.

When the communication data is written into the entry of the FIFO buffer 4 and there is a write completion instruction from the control processors 10 and 20, the decoder 5 decodes this write instruction and notifies the FIFO control circuit 6, so that FIFO control is performed. Circuit 6 validates the entry.

When there is an instruction to read communication data from the processor 2 or 1 at the other end of communication, the decoder 5 decodes the instruction to read communication data and notifies the FIFO control circuit 6 of the instruction. FIFO
The data of the oldest entry among the data stored in the buffer 4 is read and output.

Normally, since the control processors 10 and 20 output a write completion instruction after filling all four words in one entry, it is necessary to use the write cycle of the FIFO buffer 4 and the system bus 100 for four cycles.

Further, when the processors 2 and 1 sharing the FIFO buffer 4 are connected to the system bus 100,
The usage rate of the system bus 100 and the FIFO buffer 4 increases, and the efficiency of the system decreases.

For this reason, in this embodiment, the management tables 12 and 22 for managing the data written in the FIFO buffer 4 for each entry of the FIFO buffer 4 are stored in the control storage 11,
21. Data created in the buffer 21 and written to the FIFO buffer 4 is compared with the contents of the management tables 13 and 23, and writing of a coincident word is suppressed.

FI assigned to each of processors 1 and 2
Since the capacity of the FO buffer 4 is four entries, the data to be written to the first four entries of the data to be written to the FIFO buffer 4 is stored in the management tables 12 and 22.

For writing after the fifth entry, F
Prior to writing to the FIFO buffer 4, the write data is compared with the contents of the management tables 12 and 22 (data already written in the FIFO buffer 4) for each write unit (in this embodiment, 4 byte unit). The writing of the matching word is suppressed.

Thus, if the data to be written to the FIFO buffer 4 is similar, the data to be written is already F
If the data has been written to the FIFO buffer 4, the writing is not performed, so that the system bus 100 and the FIFO buffer 4
Can be reduced.

FIG. 2 is a block diagram showing the configuration of another embodiment of the present invention. In the figure, in another embodiment of the present invention, instead of the management tables 12 and 22, the format holding units 13 and 23 and the counting units 14 and 24 are stored in the control memories 11 and 21.
The configuration is the same as that of the embodiment of the present invention except for the provision of, and the same components are denoted by the same reference numerals.

The format holding units 13 and 23 hold the communication data format of the communication data between the processors 1 and 2, and the counting units 14 and 24 keep the communication data continuous with the communication data format held in the format holding units 13 and 23. This is for counting the number of times of matching.

When writing data to the FIFO buffer 4,
The control processors 10 and 20 compare the write data with the communication data format held in the format holding units 13 and 23, and count up the counting units 14 and 24 when the comparison result indicates a match. The counters 14 and 24 are reset when indicating a mismatch.

In this case, the control processors 10 and 20 make sure that a portion where the communication data format changes frequently (for example, a transfer address of the communication data format) is not compared with the write data.

The control processors 10 and 20 include a counting unit 1
When the count values of the buffers 4 and 24 exceed the capacity of the FIFO buffer 4, it is determined that the FIFO buffer 4 has been filled with the communication data format defined in advance.

Thereafter, the control processors 10 and 20
When writing the communication data into the I / O buffer 4, only the part of the communication data format which is not specified in the predefined communication data format is rewritten. Therefore, the time for writing communication data to the FIFO buffer 4 can be significantly reduced.

FIG. 3 is a diagram showing an example of a communication data format used in another embodiment of the present invention. In the figure, communication data A is a 16-byte code, and is composed of a communication source / communication destination A1, a command A2, a transfer length A3, and a transfer address A4.

In another embodiment of the present invention, the system bus 1
Since only two processors 1 and 2 are connected to the processor 00 and each set of the FIFO buffer 4 is assigned to each of the processors 1 and 2, the contents of the communication source / communication destination A1 are the same each time. It is considered something.

Therefore, the source / destination A of the communication data A
1, the command A2 and the transfer length A3 are stored in the FIFO buffer 4
And the transfer address A4 is excluded from the comparison.

In the above description, the case where the management tables 13 and 23 are provided in the control
Although the case where the format holding units 13 and 23 and the counting units 14 and 24 are provided in the control storage units 11 and 21 have been described separately, the management tables 13 and 23, the format holding units 13 and 23 and the counting unit 14, 24, the control can be switched according to the communication data.

As described above, when similar data is written to the FIFO buffer 4, the writing of the data already written to the FIFO buffer 4 is omitted, thereby speeding up the writing to the FIFO buffer 4. In addition, the usage rate of the shared resources of the processors 1 and 2 such as the system bus 100 can be reduced.

The FIFO buffer 4 has a capacity of 16 bytes × 4 words, and communication data is written through a system bus 100 having a width of 4 bytes. That is, writing one word requires four cycles.

Here, the format of the communication data is shown in FIG.
As shown in (1), when the communication content is a simple transfer request with 16 bytes of data, the only difference between the communication data is the transfer destination address A4, and all other data have the same content. . In this case, the transfer length A3 is constant.

In the first four times of writing to the FIFO buffer 4, it is necessary to write all 16-byte communication data, but in the fifth and subsequent times, only the four bytes including the transfer destination address need to be rewritten. The time required for writing communication data can be reduced to 1/4. The effect of shortening the writing time is more remarkable as the transfer length of the communication data is longer and the contents are similar and the capacity of the FIFO buffer 4 is smaller.

In the other embodiment of the present invention, the case where only the transfer destination address changes has been described. However, it is possible to cope with the case where the communication destination changes. Can be reduced to half.

[0048]

As described above, according to the buffer access control circuit of the present invention, the data written in each entry of the FIFO buffer is held, and the data written in the FIFO buffer is compared with the held contents. By suppressing the writing of data to the FIFO buffer when the result indicates a match, the frequency of access to the FIFO buffer can be reduced and the system performance can be improved.

According to another buffer access control circuit of the present invention, the data written in each entry of the FIFO buffer is held, and the data to be written to the FIFO buffer and the held contents are stored in word units. By suppressing the writing of data to a word in the FIFO buffer where a match is detected when the comparison result indicates a match,
There is an effect that the frequency of access to the buffer can be reduced and the system performance can be improved.

Further, according to another buffer access control circuit of the present invention, the format of data defined in advance and written in the FIFO buffer is held,
Data to be written to the FIFO buffer when it is determined that the number of consecutive matches between the predetermined word of the data to be written to the FO buffer and the content of the predetermined word in the held format is equal to or greater than a predetermined number. By writing only a specific word set in advance,
There is an effect that the frequency of accessing the O-buffer can be reduced and the system performance can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of another embodiment of the present invention.

FIG. 3 is a diagram showing an example of a communication data format used in another embodiment of the present invention.

[Explanation of symbols]

 1, 2 processor 4 FIFO buffer 6 decoder 10, 20 control processor 11, 21, control storage 12, 22, management table 13, 23 format holding unit 14, 24 counting unit

Claims (3)

(57) [Claims] 1. A buffer access control circuit for controlling access to a FIFO buffer consisting of a plurality of entries, comprising: holding means for holding a format of data defined in advance and written in the FIFO buffer; Comparing means for comparing the data to be written into the format with the format held in the holding means, and determining means for determining whether or not the number of times that the matching means continuously detects a match is equal to or greater than a predetermined number. And FI when the determination means determines that the number is equal to or greater than the predetermined number.
Means for controlling to write only a specific word having a high frequency of change among data to be written to the FO buffer. 2. The buffer access control circuit according to claim 1, wherein said comparison means is configured not to compare said specific word. 3. The buffer access control circuit according to claim 3, wherein said FIFO buffer is configured to be shared among a plurality of processors connected via a system bus.