JP2000215154A - Dma controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a DMA controller which can decrease the penalties due to the waiting for transfer of channels caused in a DMA transfer mode without preparing a buffer for every channel. SOLUTION: A DMA transfer request generation part 2 generates a DMA transfer request for every channel by a DMA transfer request signal 30, and a DMA transfer request control part 3 decides a channel that uses a DMA buffer 5 to save the data and performs the DMA transfer of data. Then the buffer 5 is used by a certain channel, a request is given from another channel having higher priority and also the buffer 5 has the sufficient capacity to store the data. Under such conditions, the buffer 5 is used for the channel having higher priority and the DMA transfer of data is carried out by means of the remainder of the buffer 5. Thus, it's possible to prevent a case where the necessary processing time cannot be fully secured due to the waiting for transfer of channels and then to improve the data transfer efficiency.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to DMA (Direct Memory Access) between devices (memory, I / O).
It relates to a DMA controller that performs transfer control. The transition from a channel using a DMA buffer to a different channel is performed without providing multiple DMA buffers for each channel to temporarily save DMA transfer data, thereby reducing the penalty caused by waiting for channel transition and transferring data. A DMA controller designed to increase efficiency.

[0002]

2. Description of the Related Art A conventional technique will be described with reference to an information system shown in FIG.

This system uses a DMA controller 100
1, CPU 1002, bus controller 1003, memory 1004, I / O device 1005, system bus 100
6.

[0004] The DMA controller 1001
2, specifically, from the CPU 1002 to the DMA controller 100 via the control of the bus controller 1003.
1 based on the information on the channel, source address, destination address and transfer byte size set in the control register 1010.
Request a DMA transfer.

The DMA controller 1001 issues a transfer request by asserting a DMA transfer request signal 1020 to the bus controller 1003.
The source access request signal 1021 is asserted in the cycle in which the DMA transfer request signal 1020 is asserted, and the source access request signal is negated in accessing the destination. In addition, when requested, the address 1022,
The transfer data size 1023 is output.

The data flow of the DMA transfer operation is, for example, when the source is accessed, from the memory 1004 via the system bus 1006 to the DMA controller 1001.
Of the I / O device 100 via the system bus 1006 from the DMA buffer 1011 when accessing the destination.
5 is written. These transfer controls are performed by the bus controller 1003 based on a request from the DMA controller 1001.

When the DMA controller 1001 transitions from a channel that has been DMA-transferred using the DMA buffer 1011 to another channel, the data of a different channel is transferred. In order to avoid this, the operation is performed after the DMA buffer 1011 has no more data.

[0008]

However, the above-mentioned prior art has the following problems. Assuming that the memory 1004 is a memory having a burst transfer function capable of continuously reading or writing a plurality of words of data, such as an SDRAM, for example, access to the memory 1004 is performed at one time up to the boundary of a memory address at which burst transfer is possible. Is more efficient. For example, when this boundary exists every 16 bytes, if the alignment at the 16-byte boundary between the source address (0x0002) and the destination address (0x0000) is different as shown in FIG. Considering a long transfer that crosses the boundary, the first transfer has an address 1022 from the source of 0x0002 and a transfer data size 1023 of
This is a transfer of 0x8 (8 bytes). At the stage where the first data is saved in the DMA buffer 1011, the next 16 byte boundary from the initial address 0x0000 of the destination
Since there is no 16-byte data to be transferred to 0x0004 in the DMA buffer 1011, the address 1022 from the source is 0x0004 and the transfer data size 1023 is 0x10 (
(16 bytes). Third time, DMA buffer 1
Since there was enough data to transfer to the destination at 011, the address 1022 to the destination was 0x0000, and the transfer data size 1023 was 0x10.
Will be transferred. The fourth time is the address 10 from the source
22 is 0x0008 and the transfer data size 1023 is 0x10, the fifth time is the address 1022 to the destination
Is 0x0004 and the transfer data size 1023 is 0x10. In the last sixth transfer, the remaining data to be transferred is 8 bytes, so the address 1022 to the destination is 0x000.
8. The transfer data size 1023 is 0x08. 1
024 is a DMA transfer permission signal, 1025 is a read data acknowledge, and 1026 is a write data acknowledge.

As described with reference to FIG. 9 as an example, in a transfer in which the alignment at the 16-byte boundary is different between the source address and the destination address, if sufficient data to be transferred to the destination is stored, this data is 16 bytes. Therefore, even after the transfer to the destination, data continues to exist in the DMA buffer 1011 until a complete series of transfers is completed (for example, 8 bytes after the third transfer). Data remains).

For this reason, if a DMA transfer is performed for a large amount of data or a device having an extremely low access speed when a DMA transfer is performed between a source and a destination at a misaligned address in a certain channel, the other DMA transfer is performed. The problem is that the channel cannot complete the transfer within the required processing time due to the waiting time until the DMA buffer becomes empty and available.

In view of the above problems, the present invention gives priority to another channel having a high degree of urgency even if a DMA buffer used in a certain channel has sufficient storage capacity. Allocate a DMA buffer,
By performing DMA transfer control according to the remaining amount of the DMA buffer, the penalty of channel transition waiting time is reduced and transfer efficiency is improved while avoiding an increase in circuit size due to the provision of a DMA buffer for each channel. DM that can
A The purpose is to provide a controller.

[0012]

According to a first aspect of the present invention, there is provided a DMA controller for performing a DMA transfer by temporarily saving data to be DMA transferred between devices to a DMA buffer having a data size of a plurality of bytes. DMA buffer and DMA from multiple channels
A DMA transfer request control unit that determines a channel to use the DMA buffer from a plurality of channels based on a transfer request signal, and a DMA that controls data access to the DMA buffer.
When a transfer request is issued from a channel with a higher priority than the channel using the DMA buffer, the DMA transfer request control unit has a capacity to store data in the DMA buffer. For example, it is characterized in that a high-priority channel is allowed to perform a DMA transfer using a DMA buffer.

[0013] According to the DMA controller of the first aspect, the DMA transfer request control unit determines a channel to use the DMA buffer. Even when a certain channel uses the DMA buffer, the DMA transfer request control unit has a higher priority. When there is a transfer request for a high channel, if there is enough capacity to store data in the DMA buffer, transition to a higher priority channel is performed.
The transfer control is preferentially performed.

Thus, a certain channel is using
The remaining amount of the DMA buffer is changed to the higher priority channel DM.
A By using it for transfer, there is no need to provide a buffer for each channel and to avoid an increase in circuit size.Also, as one channel continues to use a DMA buffer for an extremely long time, another channel is Has the effect of preventing the processing time required by the transition waiting time penalty from being exceeded and improving the transfer efficiency.

According to a second aspect of the present invention, there is provided a DMA controller according to the first aspect, wherein a transfer data size requested by a high priority channel exceeds a capacity that can store data in a DMA buffer. And a DMA transfer request generation unit for performing a DMA transfer control of a transfer data size capable of storing data in the DMA buffer in a plurality of times to the DMA transfer request control unit.

According to the DMA controller of the second aspect, in addition to the same effect as the first aspect, the DMA transfer request generation unit for performing the DMA transfer request should originally request the capacity capable of storing data in the DMA buffer. When the transfer data size exceeds, the transfer data size is divided into transfer data sizes that can be stored in the DMA buffer, and DMA transfer requests are made a plurality of times.

As described above, when the remaining amount of the DMA buffer used by the channel is smaller than the transfer data size to be performed for a certain channel, the channel is divided into a plurality of transfers capable of performing the DMA transfer with the remaining amount of the DMA buffer. By doing so, there is an effect that it is possible to prevent a DMA transfer from being performed because the remaining amount of the DMA buffer is small, and to prevent a penalty of a channel transition waiting time from being generated.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to FIGS.

FIG. 2 shows an example of the configuration of an information system using a DMA controller according to an embodiment of the present invention.
The DMA controller 1001 is the same as the conventional system shown in FIG.

FIG. 1 shows the configuration of a DMA controller 1 according to the present invention. The DMA controller 1 includes a DMA transfer request generator 2, a DMA transfer request controller 3, a DMA buffer controller 4, a DMA buffer 5, a control register 6, a DMA data bus 10, and a control data bus 11.

The DMA controller 1 is used for control.
It has a DMA buffer write pointer 15, a DMA buffer read pointer 16, a DMA buffer full flag 17, a DMA buffer flag 18, and a DMA buffer lock flag 19.

The main control contents of the DMA transfer request generation unit 2 are as follows.
This is to generate a DMA transfer request corresponding to the information of the control register 6 set from the CPU 1002.

The main control contents of the DMA transfer request control unit 3 are as follows.
This is to arbitrate the request from the DMA transfer request generator 2 between channels and make a DMA transfer request to the bus controller 1003.

The main control contents of the DMA buffer control unit 4 are as follows.
This is to control the reading and writing of data from and to the DMA buffer 5 based on the timing of the acknowledge signal from the bus controller 1003.

The DMA buffer 5 is a buffer for storing DMA transfer data read from the source device until the data is transferred to the destination.

The control register 6 is a register for storing a set value for controlling the DMA controller 1. The DMA controller 1 is activated by setting the control register 6 by the CPU 1002.

The DMA buffer write pointer 15
This is a pointer indicating an address to which data is to be written next to the buffer 5.

The DMA buffer read pointer 16
This is a pointer indicating the address from which data is to be read next to the buffer 5. The DMA buffer write pointer 15 and the DMA buffer read pointer 16 are incremented by the DMA buffer control unit 4. When the pointers exceed the upper limit value and return to 0, the pointers return to 0 and continue.

The DMA buffer full flag 17 is a flag indicating that there is no capacity for writing data to the DMA buffer 5 and is set / cleared by the DMA buffer control unit 4.

The DMA buffer flag 18 is a flag indicating a channel using the DMA buffer 5, and is set / cleared by the DMA transfer request generator 2.

The DMA buffer lock flag 19 is a flag indicating a channel used exclusively by locking the DMA buffer 5 and is set by the DMA transfer request control unit 3 and cleared by the DMA transfer request generation unit 2. You.

FIG. 3 shows a control flowchart for each channel of the DMA transfer request generator 2.

In step 101, it is determined whether to activate the DMA channel. The control register 6 has a source address, a destination address,
The DMA transfer request generator 2 has a transfer data size and a DMA transfer request flag field. The DMA transfer request generator 2 activates the channel in which the control register 6 is newly set and the DMA transfer request flag field is set. For a channel in which the field of the DMA transfer request flag is not set, the process waits in step 101, and for a channel in which the DMA transfer request flag is set, the process proceeds to step 102.

In step 102, it is determined whether a transfer request from the source or a transfer request to the destination is made in the DMA transfer. The DMA transfer request generation unit 2 includes a source data counter 20 for counting the size of already transferred data, a destination data counter 2
Each has a value of 0, each immediately after the DMA channel is activated. In step 102, if the difference between the values of the source data counter 20 and the destination data counter 21 exceeds the smaller of the data size that can be transferred to the device that performs DMA transfer at a time or the remaining amount of the DMA buffer 5, Alternatively, if the source data counter 20 indicates that all data has been transferred, it is determined that sufficient data to be transferred to the destination is stored in the DMA buffer 5, and a transfer request to the destination is issued. Otherwise, a transfer request is made from the source. The remaining amount of DMA buffer 5
If (value of DMA buffer read pointer 16)> (value of DMA buffer write pointer 15), (value of DMA buffer read pointer 16)-(DMA buffer write pointer 1)
(Value of DMA buffer read pointer 16)
<(Value of DMA buffer write pointer 15)
(Total capacity of DMA buffer 5) + (Value of DMA buffer read pointer 16)-(Value of DMA buffer write pointer 15)
Given by

In step 103, the DMA transfer request control unit 3
Make a DMA transfer request to the To the DMA transfer request controller 3
The DMA transfer request is performed by asserting the DMA transfer request signal 30, the source access request signal 31 is asserted for a source access request, and the source access request signal 31 is negated for a destination access request. The transfer data size is the data size that can be transferred to the device that performs DMA transfer at one time, and the data size that has not been transferred.
If the DMA buffer flag 18 is set in any of the other channels, the smallest one of the three including the remaining amount of the DMA buffer 5 is output as the transfer data size signal 33. Address is Step 1
In the case of the source, the value of the source data counter 20 is added to the value (initial address) of the source address field of the control register 6 based on one of the results of the access to the source / destination determined in 02. In the case of the destination, the value of the field of the destination address of the control register 6
(Initial address) plus the value of the destination data counter 21 is output as the address 32.

In step 104, the DMA transfer request
It is determined whether the transfer request is permitted by the transfer request control unit 3. When the DMA transfer permission signal 35 from the DMA transfer request control unit 3 is asserted for the channel making the request, it is determined that the DMA transfer permission has been given to the channel, and the DMA buffer flag 18 The field is set, and the DMA transfer request generation unit 2 transitions to step 105, and if negated, transitions to step 102.

In step 105, it is determined whether or not a series of DMA transfer from the start of the DMA channel has been completed. The value of the destination data counter 21 is stored in the control register 6
If the transfer data size value of the
A It is determined that the transfer has been completed, and the DMA buffer flag 18 and
The field of the corresponding channel of the DMA buffer lock flag 19 is cleared, and the routine goes to Step 107. If not, the routine goes to Step 106.

In step 106, if an access request to the source has been made, the source data counter 20
In the case of the destination, the value of the destination data counter 21 is
Is incremented by the value that was output as.

In step 107, the DM of the control register 6
A Clear the transfer request flag field.

FIG. 4 shows a flowchart of the control of the DMA transfer request controller 3.

In step 201, it is checked whether or not there is a DMA transfer request from the DMA transfer request generator 2. If the DMA transfer request signal 30 has been asserted for any of the channels, the process proceeds to step 202.

In step 202, the DMA buffer 5
A Determine whether the channel is locked by the channel that made the transfer request. The DMA transfer request generation unit 2 does not accept a DMA transfer request from a channel other than the channel indicated by the lock flag 19 indicating that the DMA buffer is occupied by a certain channel. If the DMA buffer lock flag 19 is set and there is no request from the channel locking the DMA buffer 5, the process waits in step 202, and if not, the process proceeds to step 203.

In step 203, arbitration is performed to determine which channel is to be granted an access right based on the priority order among the channels that have made DMA transfer requests. Requests from the channel indicated by the DMA buffer lock flag 19 always win arbitration.

In step 204, it is determined whether or not a channel other than the channel to which the arbitration has been won and the access right is given uses the DMA buffer 5. DM
If the DMA buffer flag 18 is set, the transfer request generation unit 2 determines that the channel indicated by the DMA buffer flag 18 uses the DMA buffer 5. Channels other than the channel to which arbitration has been granted access rights are DM
Step A 205 when the buffer 5 is used
Otherwise, the process proceeds to step 206.

In step 205, it is determined whether or not the DMA buffer 5 has a capacity capable of storing data. If the DMA buffer full flag 17 is set, the DMA transfer request generator 2 determines that there is no capacity to write to the DMA buffer, and proceeds to step 202. If not, the process proceeds to step 206.

In step 206, an access request is made to the bus controller 1003 which is actually controlling the bus access. DMA transfer request generation unit 2
Assert the transfer request signal 1020 to make a request,
The source access request signal 31, the address 32, and the transfer data size signal 3 of the channel that locks the DMA buffer 5 indicated by the DMA buffer lock flag 19 or the channel determined by the arbitration in step 203
3 are output as a source access request signal 1021, an address 1022, and a transfer data size signal 1023, respectively.

In step 207, the bus controller 1
When 003 asserts the DMA transfer request signal 1024 to permit the DMA transfer request, the DMA transfer request generation unit 2 is notified by asserting the DMA transfer permission signal 35 that the DMA transfer has been accepted. If the channel is set in one of the DMA buffer flags 18, the field of the channel for which DMA transfer is permitted in the DMA buffer lock flag 19 is set.

FIG. 5 shows a flowchart of the control of the DMA buffer controller 4.

In step 301, the bus controller 1
If the read data acknowledge signal 1025 from 003 is asserted, the process proceeds to step 302 for controlling data writing to the DMA buffer. If not, the process proceeds to step 304.

In step 302, the data of the DMA data bus 10 is transferred to the area of the DMA buffer 5 pointed to by the DMA buffer write pointer 15, and the read data acknowledge signal 1
025.

In step 303, the DMA buffer write pointer 15 is incremented by the size of the written data. At this time, the DMA buffer write pointer 15
Has reached the upper limit, wrap-around returns to 0, and then increments again. When the value is incremented to reach a value immediately before the DMA buffer read pointer 16, the DMA buffer full flag 17 is set.

In step 304, the bus controller 1
When the write data acknowledge signal 1026 from 003 is asserted, the process proceeds to step 305 to control the reading of data from the DMA buffer, and when it is not asserted, the process proceeds to step 301.

In step 305, the data in the area of the DMA buffer 5 indicated by the DMA buffer read pointer 16 is
Reading is performed at a timing based on the write data acknowledge signal 1026.

In step 306, the DMA buffer read pointer 16 is incremented by the read data size. At this time, the DMA buffer full flag 17 is cleared. When the DMA buffer read pointer 16 reaches the upper limit value, it wraps around and returns to 0, and then increments again.

FIG. 6 shows the structure of the DMA buffer 5. The size of the DMA buffer 5 is desirably twice the data size that can be transferred to a device on the bus at one time from the viewpoint of improving the transfer efficiency.
For the purposes of the present invention, it is necessary that the data can be read from multiple addresses in the buffer, rather than being like a FIFO. In the example of FIG. 6, the DMA buffer 5 is a write data selector 5
1, a read data selector 52 and a data buffer 53. The write data selector 51 is for the DMA buffer write pointer 15 and the read data selector 52 is for the DMA buffer.
The address indicated by the buffer read pointer 16 is selected.

The operation of the DMA controller 1 configured as described above will be described with reference to the timing chart of FIG.

FIG. 7 shows the source address 0x000 in channel 1.
2, DMA transfer of destination address 0x0010, transfer data size 24 bytes, source address in channel 2
This is an example of performing a DMA transfer of 0x1000, destination address 0x1010, and transfer data size of 16 bytes.
In this example, the priority of the channel 2 is higher than that of the channel 1, the capacity of the DMA buffer 5 is 32 bytes, and the data size that can be transferred by one access is 16 bytes of 4 bytes × 4.

First, the DMA of channel 1 is activated first,
A The transfer request generation unit 2 outputs a DMA transfer request signal 3 for channel 1.
0, the source access signal 31 is asserted and the address is
0x0002, 0x08 is output as the transfer data size signal. This request is granted by the DMA transfer request control unit 3 at the sampling timing S1, and 4 bytes × 2 times the DMA from the source.
The transfer is performed.

In order to transfer the remaining data from the source, the DMA transfer request generator 2 asserts the DMA transfer request signal 30 and the source access request signal 31 of the channel 1, and sets the address to 0x0004 and the transfer data size signal to 0x10. Output. This request is permitted at the sampling timing S2, and 4 bytes × 4 DMA transfers from the source are performed.

Next, the DMA of the channel 2 is activated, and the DMA transfer request generator 2 issues a transfer request to the destination of the channel 1 and a transfer request from the source of the channel 2. Here, the channel 2 is to transfer 16 bytes, but since the remaining capacity of the DMA buffer 5 is 8 bytes, an 8-byte transfer request is made. Specifically, the channel 1 DM
A The transfer request signal 30 and the source access signal 31 are negated, and the address is 0x0010 and the transfer data size signal is 0x10.
And the channel 2 asserts the DMA transfer request signal 30 and the source access signal 31, and sets the address to 0x1000,
Outputs 0x08 to the transfer data size signal. At the sampling timing S3, the DMA transfer request control unit 3 permits the transfer of the channel 2 having the higher priority, and thereafter performs the transfer of the channel 2 until the access to the destination of the channel 2 is permitted at the sampling timing S6.

Upon completion of the transfer of the channel 2, after the sampling timing S7, the data of the channel 1 stored in the DMA buffer 5 is transferred to the destination.
A series of transfers is completed for channel 1 as well.

[0062]

According to the DMA controller according to the first aspect of the present invention, the remaining amount of the DMA buffer used by a certain channel is used for the DMA transfer of the channel with a higher priority, so that the buffer is provided for each channel. Without the provision of a circuit and avoiding an increase in circuit size, as one channel continues to use the DMA buffer for an extremely long time as in the past, the processing time required by another channel due to the penalty of the channel transition waiting time is reduced. This has the effect of preventing loss of performance and improving transfer efficiency.

According to the DMA controller of the second aspect, in addition to the same effects as those of the first aspect, when the remaining amount of the DMA buffer used by the channel is smaller than the transfer data size to be transmitted to a certain channel, the DMA Dividing into multiple transfers that can be DMA-transferred based on the buffer remaining capacity prevents the DMA transfer from being performed due to the low DMA buffer remaining capacity and preventing the occurrence of a channel transition wait time penalty. effective.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a DMA controller 1 of the present invention.

FIG. 2 is a configuration diagram of an information system using a DMA controller 1 of the present invention.

FIG. 3 is a control flowchart of a DMA transfer request generation unit 2.

FIG. 4 is a control flowchart of a DMA transfer request control unit 3;

FIG. 5 is a control flowchart of a DMA buffer control unit 4;

FIG. 6 is a configuration diagram of a DMA buffer 5;

FIG. 7 is a timing chart showing a DMA transfer operation of the DMA controller 1.

FIG. 8 is a configuration diagram of a conventional DMA controller information system.

FIG. 9 is an address diagram showing an example of a DMA transfer using a DMA buffer continuously.

[Explanation of symbols]

 1 DMA controller 2 DMA transfer request generator 3 DMA transfer request controller 4 DMA buffer controller 5 DMA buffer 6 Control register 10 DMA data bus 11 Control bus 15 DMA buffer write pointer 16 DMA buffer read pointer 17 DMA buffer full flag 18 DMA Buffer flag 30 DMA transfer request signal 31 Source access request signal 32 Address 33 Transfer data size signal 35 DMA transfer enable signal 1020 DMA transfer request signal 1021 Source access request signal 1022 Address 1023 Transfer data size signal 1024 DMA transfer enable signal 1025 Read data acknowledge 1026 Write data acknowledge

Claims (2)

[Claims] 1. A method for transferring data to be DMA-transferred between devices,
A DMA controller for performing a DMA transfer by temporarily saving data to a DMA buffer having a data size of a plurality of bytes, wherein the DMA controller uses the DMA buffer based on the DMA buffer and DMA transfer request signals from a plurality of channels. DMA for determining a channel from the plurality of channels
A transfer request control unit; and a DMA buffer control unit that controls data access to the DMA buffer.
If there is a transfer request from a higher priority channel than the channel using the buffer, the DMA
If the transfer request control unit has a capacity capable of storing data in the DMA buffer, the transfer request control unit
A DMA controller which permits a DMA transfer using a DMA buffer. 2. When the transfer data size requested by a high-priority channel exceeds the capacity that can be stored in the DMA buffer, a request corresponding to the request of the high-priority channel is sent to the DMA buffer. DMA of transfer data size that can be stored
2. The DMA controller according to claim 1, further comprising a DMA transfer request generation unit for performing a transfer request control unit.