JP2716563B2 - Data write control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary of the Invention] A write control circuit of an information processing device connected to a memory via a bus, a memory write can be performed without being aware of an address boundary by software, and The purpose of this is to prevent write access without delay from becoming slow: 1. A data write control circuit in a data processing device connected by a memory and a bus, with a capacity of at least twice the data bus width (k) (J),
A data buffer (13) for holding write data from the data processing unit (CPU), an address buffer (14) for holding a write address from the data processing unit, and a size buffer for holding a write size width from the data processing unit (16), a circular shifter (12) for circularly shifting the write data from the data processing device by the surplus of the capacity (j) of the write address and setting it in the data buffer, and a write access by the write address and the write size. A boundary check circuit (17) for detecting that the address crosses an address boundary. The boundary check circuit (17) includes an adder (17a) for adding the write address and the write size, and the adder (17a). If (the K data bus values) lower log ₂ K bits of the addition result of the carry is generated from the eye Or write access if the lower log ₂ following bits K-bit write address K width of the write are not all zero and a flag (17b) to be set as a straddle thing to address boundary, further said boundary check circuit When the flag (17b) of (17) is set, a clock control circuit (15) for suppressing the clock of the data processing device for one cycle after the first write access is provided. Controls the processing unit to stop the operation and performs write access again. The write size to be sent on the write size bus (WSB) is the value of the size buffer if the flag (17b) is not set. If the flag (17b) is set, the first time is calculated as k remainder of k-write address,
The second time is the value of the size buffer minus the first write size, and the write address transmitted on the address bus (AB) is
If the flag (17b) is not set, the value of the address buffer is used. If the flag (17b) is set, the value is updated to the address buffer for the first time and updated to the next address boundary for the second time. The write data sent to the data bus (DB) is the upper k of the data buffer if the flag is not set.
When the flag is set, the first time is the upper k minutes of the data buffer, and the second time is the lower k minutes.

[Industrial applications]

The present invention relates to a write control circuit of an information processing device connected to a memory via a bus.

In a processor, memory access is very frequent and it is important to increase the speed.

In many cases, continuous memory areas are accessed successively, and software is conscious of address boundaries in order to facilitate program creation and facilitate program compatibility between devices with different memory bus widths. Need not be done. In addition, even if access is performed across address boundaries, it is required that performance degradation be minimized.

[Conventional technology]

There is a system in which a data bus has a width of a plurality of bytes and a plurality of bytes are read / written by one memory access, but data can be read / written in byte units. In FIGS. 4 (a) and 4 (b), the plurality of bytes are 4 bytes, and 4 bytes are read / written by one address in the memory MEM. However, data can be handled in byte units. This is possible by excluding the lower 2 bits of the memory access address and specifying each byte of 4 bytes to be read / written by the lower 2 bits. It is. In this system, a bus address corresponds to a memory address. That is, each data on the 32 (4 bytes) bus signal lines is composed of 32 bits on one address of the memory and 1 data.
One to one.

In such a system, it is easy to handle 4 bytes corresponding to a memory address. For a read, the memory MEM is read at that address, and the 4 bytes that have come out are taken out to the data bus DB. The upper four bytes may be written to the storage location selected by the address of the memory MEM. This is described with reference to FIG.
.. (This is represented by the address of the lower 2 bits) corresponds to reading / writing in units of 4-byte data.

Data is handled in byte units, so 0-3,
4 to 7,... In some cases, 2 bytes of 3 and 4 are read / written instead of 4 bytes. To do this,
If it is read, read 0-3 and select 3 of them,
Further, the processing is to read out 4 to 7 and select 4 of them. In the case of write, the memory has a function of 1-byte write, 2-byte write,..., 4-byte write.
Is written to the corresponding position, and 4 is written to the corresponding position in the second memory access. If only 4-byte access, read 0-3, replace 3 of them with new data, write the result to the read address, read 4-7, replace 4 of them with new data,
The result is written to the read address, and so on.

In this way, when accessing across an address boundary such as between 3 and 4 or between 7 and 8, it is different from the case where accessing does not cross an address boundary (partitioned by an address boundary). Processing and complexity.

[Problems to be solved by the invention]

Conventionally, when data is written by a processor, its address is checked by software or firmware, and when it crosses a bus boundary, an access is made in two steps, and the address of each access is Updating, determination of the light size, etc. were performed by a program.

Therefore, the address is loaded into the register, it is checked whether or not the lower bit crosses the boundary of the bus width, and if so, the first write size is calculated, write access is performed, and then the address is updated. After that, the second write size is calculated, and the second write is performed.

The problem with issuing a memory write request by checking the address using this software is that despite the simple memory write, the number of steps is considerably large, and the time until the write is completed is extremely long. It will be. In addition, when an address check is performed by firmware, an address boundary is always checked at the beginning of a memory write instruction, so that a write instruction that does not cross an address boundary may be delayed.

It is an object of the present invention to improve such a point that a memory write can be performed without being aware of an address boundary by software, and a write address that does not cross an address boundary is not delayed. It is.

[Means for solving the problem]

As shown in FIG. 1, in the present invention, the data write control
Circular shifter 12, Data buffer 13, Address buffer 14, Size buffer 16, Boundary check circuit 17
Is used.

The data buffer 13 has a capacity j that is at least twice the bus width k of the data bus DB. In the above example, the bus width k is 4 bytes and the capacity j is 8 bytes. Data processing unit (CPU) 1
The data width of 1 is equal to the bus width, and is 4 bytes in this example.

The circular shifter 12 receives the 4-byte data from the CPU 11, shifts by the remainder of the capacity j of the write address, and
For example, if the write address is 3, the data is shifted by 8 (j) -3 = 5 and set in the data buffer 13.

The boundary check circuit 17 checks, based on the write address and the write size, whether the write access crosses an address boundary. For example, lower 2 of the write address
If the bit is 00 and the write size is 4 bytes, the write access does not cross the address boundary, and if the write address is 3 and the write size is 2, the write access crosses the address boundary, and the boundary check is performed. The circuit 17 detects such a straddling / not straddling. When straddling,
The output WC of the boundary check circuit 17 is, for example, 1; When crossing, CPU clock C
LK is suppressed for one cycle and write access is performed again.

In the data write, the write data is put on the data bus DB, the write address is put on the address bus AB, and the write size is put on the write size bus WSB. The write size to be added to the WSB is the value of the size buffer 16 when not straddling, the surplus of k of the k-write address when straddling the first time, and the value of the size buffer minus the first write size when straddling. The write address to be assigned to the AB is the value of the address buffer when it does not straddle, the value of the address buffer when straddling the first time, and the value updated to the next address boundary the second time. Also, when writing data to the DB does not straddle,
When straddling the upper k bytes of the data buffer, the first is the upper k bytes of the data buffer and the second is the lower k bytes.

[Action]

According to this configuration, the CPU 11 only outputs the write data D, the write address ADD, and the write size SZ. If the CPU 11 does not cross an address boundary, the CPU 11 performs one write access. Can be divided into two times, and the write address can be updated for the two times to write data.

The boundary check circuit 17 determines whether or not an address boundary is straddled, and the selectors 18, 19, and 10 select data, address, and size according to the result.

In this method, since a cycle such as address boundary determination by software does not enter, quick write access is possible.

〔Example〕

More specifically, FIG. 1 shows that the CPU 11 performs write access,
The write address ADD, the write data D, and the number of write bytes (write size) SZ are generated. The circular barrel shifter 12 circularly shifts the write data D to a write position on the memory bus according to the value of the address ADD. The data buffer 13 holding the write data D is set with the write command by the write command. The address buffer 14 holding the address data is addressed by a write instruction.
ADD is set. The clock control circuit 15 disables the clock CLK input to the CPU by the output of the boundary check circuit 17. The write size Z is set in the write size buffer 16 for holding the write data width by a write instruction. The boundary check circuit 17 is a circuit for checking whether or not the write address crosses the bus address boundary based on the write address ADD and the write data width SZ. The resultant signal WC controls the clock CLK of the processor and outputs the signal to the bus. Data / address / write size to be selected. The data select 18 is a circuit for selecting data to be output to the bus.
Then, according to the result of the boundary check of the circuit 17, the write data to be transmitted to the bus is selected. The address select 19 is a circuit for selecting an address to be output to the bus, and selects an address to be transmitted based on the result of the boundary check. The size select 10 is a circuit for selecting a write size to be output to the bus, and selects a write size to be output to the bus based on the address ADD and the result of the boundary check.

If the CPU 11 is a 32-bit type, the bus width is 32 bits (4 bytes), and if the write data is 2 bytes, 1 byte, 3 bytes, etc., these are packed from one end as shown in FIG. , Generally output right justified. In response to this, the circular shifter 12 shifts according to the lower 2 bits of the write address, in this example, the lower 2 bits. For example, to write a 2-byte data D ₁ and D ₂ in address 3 and 4 as in the above example, a state of FIG. 3 of 12a shifted 3 times. The data buffer has a capacity twice as large as the bus width (although it may be more than twice), and when the data buffer is divided into two, the data D ₁ is placed on the right end (address 3) of 13a,
Comes data D ₂ to 3b the left edge of the (address 0). Therefore, a desired write can be performed by using the first write 13a and the second write 13b.
The circular shifter 12 and the data buffer 13 have such functions, and the data select 18 selects between 13a and 13b.

Explaining the whole, the data buffer 13, the address buffer 14, and the size buffer 16 are set by the CPU write instruction. At this time, the write data from the CPU is shifted by the circular shifter 12. In the above example, the number of shifts is three, but this is
8-8, the write address 3, and the write size 2 can be calculated as 8-3-2. In addition, when the number of shifts until the right-justification in FIG. 3 is added, the number of shifts is 8-3.
= Become 5 (details 8-3 for D _1, 8-4 for the D _2). The write address and the write data width from the processor are set in the address buffer 14 and the size buffer 16 as they are.

The boundary check circuit 17 adds the write size to the write address, checks the carry from the lower log ₂ k bit of the addition result, and when the carry is 1 and there is a write access, the control signal WC is cycled for one cycle. After one
Send only cycles. Here, k is the bus width, which is 4 in this example. In this example the lower log ₂ k bit thus lower 2
The write address is 3 (11 in binary, upper bits are omitted) and the write size is 11 if it is 2 (10 in binary).
When + 10 = 101, carry 1 is output from the lower 2nd bit.
This indicates that it straddles the address boundary of the bus.

In the case of write access that does not cross the bus address boundary, the carry is 0 (there is no carry), and the address, write size, and write data from the CPU are set in each buffer and then left unchanged (the required data There is a shift) address AB, write size bus WSB, data bus DB
Sent up.

In the case of a write access that crosses an address boundary of a bus, write data and a write address up to the address boundary are sent out onto the bus without being set in the buffer. As the write size, (k-write address)
Sent to the bus. Then, in the next cycle, the control signal WC is turned on, the clock of the CPU is suppressed, the value of the write address updated from the address ADD up to the address boundary is sent out onto the bus, and the write data exceeds the address boundary. Write data to the selected area is selected and sent out onto the bus. Control signal for light size
When the WC is on, a value obtained by subtracting the first light size from the light size SZ is transmitted to the bus.

To explain this in Figure 3, the write data D ₁ of the up address boundary, a write address 3, write size 1 =
4-3 is sent out to the bus and the first write is performed.
After that, since the writing has not yet been completed, the address ADD is updated to the next value in units of 4 bytes (the lower two digits are 0) while the CPU is stopped according to the clock, and this is sent to the bus, and the data buffer 13b a selection of and sends the data D ₂ to the bus, a write size is sent to the bus as the remaining 2-1 = 1, this performs the second write.

In the example of FIG. 3, when 2-byte data is written to address 1, only one access is required because it does not cross an address boundary. In this case, the following is performed. That is, the circular shifter 12 shifts 8-1-2 = 5 times and shifts the data.
D _1, D transferred ₂ from the left 13a to the second and third, the write address 1, write size as 2 instructs the light. Since the remaining light size is now 0, the process is completed. A boundary check is also performed, but this is performed in parallel with the write operation, so that the write operation is not delayed due to this check.

FIG. 2 shows a specific example of the boundary check circuit 17 and the like. The data buffer 13 is an 8-byte register composed of 13a and 13b in FIG. 3, and the selector 18 selects between 13a and 13b. The selection signal is the output of the selector 21. The boundary check circuit 17 includes an adder 17a and a flag 17b. The adder 17a adds the output of the address buffer 14 and the output of the size buffer 16, and when the carry from the second least significant bit is 1, or 4 bytes. When the lower 2 bits of the write address are other than 00 in the write operation, the signal C is output and the flag 17b is set. Therefore, when the write access crosses the 4-byte boundary, the signal C is turned on, the flag 17b is set, and the write size to be sent out onto the bus by operating the selector 10 is not the value of the size buffer 16 but the value of the selector 22. Output. The flag 17b instructs the second write cycle, and stops the clock of the CPU 11 while the flag 17b is on, thereby controlling the selectors 22, 19, and 21. This flag 17b
It may be turned on for only one cycle per write.

The adder / subtracter 23 is the lower 2 of the write size + write address.
Output bit-4. In the above example, 2 + 3-4 = 1 is output. The subtractor 24 outputs the lower 2 bits of the 4-write address. In the above example, 4-3 = 1 is output. When the output C of the adder 17a is off (O), the selector 10 selects the size buffer 16; when it is on, the selector 22 is selected; when the flag 17b is off (first access), the selector 22 When 24 is ON (second access), the adder / subtractor 23 is selected.

The adder 25 outputs +4 obtained by setting the lower 2 bits of the write address to 0. That is, an address for each address boundary is output. The selector 19 selects the address buffer 14 when WC = 0 (first access), and selects the adder 25 when WC = 1 (second access).

The flag output WC also operates the selector 21 and when WC = 0,
When the third bit from the lower end of the write address is 0, the upper 4 bytes (13a) of the data buffer 13 are selected, and when the third bit is 1, the lower 4 bytes (13b) of the data buffer 13 are selected. When WC = 1, the opposite write data is output on the bus.

The flag output WC further controls the clock control 15, which is an inhibit gate, and inhibits the clock output from the oscillator from being input to the CPU 11 while WC = 1.

As an example where the write access does not cross the 4-byte bus boundary, the case where the CPU writes 4-byte data from the 0th byte will be described. An address whose lower 2 bits are 0 is set in the address buffer 14 and the size buffer 16 stores 4 bits. Is set. Since the lower 2 bits of the write address are 0, the write data is shifted four times by the shifter 12 and set in the 8-byte data buffer 13 left-justified. The output C of the adder 17a is 0 + 4, since there is no carry from the lower 2 bits and the lower 2 bits of the write address are 0 in 4-byte write, C = 0, and the data of the buffers 13, 14, 16 Is output to the buses DB, AB, and WSB, and is completed by one write access.

Next, as an example where write access crosses a 4-byte boundary,
The operation when the CPU writes the third to fourth bytes will be described. In this case, 3 is set in the address buffer 14 and the size buffer 4 is set. Since the write address is 3, the write data is shifted by 8-3-4 = 1 time to 8
It is set in the byte data buffer 13.

The output C of the adder 17a is turned on because the lower 2 bits of the address are not 0 in a 4-byte write, the flag 17b is set in the next cycle, and the write size is initially the value 1 of the subtractor 24, the next Becomes the value 3 of the adder / subtractor 23.

The write address is the value of the address buffer 14 since WC = 0 at first, and the value of the adder 25 since WC = 1 next. Write data is initially an 8-byte data buffer 13
Is the upper 4 bytes, and the next is the lower 4 bytes.

Further, according to the present invention, the access can be speeded up only by adding an external interface circuit without changing the CPU main body or the program.

〔The invention's effect〕

As described above, according to the present invention, memory write access can be performed by software without being aware of address boundaries. In addition, write access that does not straddle an address boundary is not delayed, and write access that straddles a boundary is only one cycle slower than when there is no straddle. It is much faster than

[Brief description of the drawings]

1 is a principle diagram of the present invention, FIG. 2 is a block diagram showing an embodiment of the present invention, FIG. 3 is an explanatory diagram of an operation, and FIG. 4 is an explanatory diagram of an address boundary. In FIG. 1, 11 is a data processing device, WSB is a write size buffer, AB is an address bus, and DB is a data bus.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Toru Watanabe 1015 Uedanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Takumi Maruyama 1015 Kamikodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited ( 72) Inventor Takumi Takeno 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Shinya Kato 1015, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (56) References JP-A Sho48 JP-A-68209 (JP, A) JP-A-54-129934 (JP, A) JP-A-62-174842 (JP, A)

Claims (1)

(57) [Claims] 1. A data write control circuit in a data processing device connected to a memory and a bus, the data write control circuit having a capacity (j) of twice or more a data bus width (k),
A data buffer (13) for holding write data from the data processing unit (CPU), an address buffer (14) for holding a write address from the data processing unit, and a size buffer for holding a write size width from the data processing unit (16), a circular shifter (12) for circularly shifting the write data from the data processing device by the surplus of the capacity (j) of the write address and setting it in the data buffer, and a write access by the write address and the write size. A boundary check circuit (17) for detecting that the address crosses an address boundary. The boundary check circuit (17) includes an adder (17a) for adding the write address and the write size, and the adder (17a). If (the K data bus values) lower log ₂ K bits of the addition result of the carry is generated from the eye Or write access if the lower log ₂ following bits K-bit write address K width of the write are not all zero and a flag (17b) to be set as a straddle thing to address boundary, further said boundary check circuit When the flag (17b) of (17) is set, a clock control circuit (15) for suppressing the clock of the data processing device for one cycle after the first write access is provided. Controls the processing unit to stop the operation and performs write access again. If the flag (17b) is not set, the write size sent to the write size bus (WSB) is the value of the size buffer. If the flag (17b) is set, the first time is calculated as k remainder of k-write address,
The second time is the value of the size buffer minus the first write size, and the write address transmitted on the address bus (AB) is
If the flag (17b) is not set, the value of the address buffer is used. If the flag (17b) is set, the value is updated to the address buffer for the first time and updated to the next address boundary for the second time. The write data sent to the data bus (DB) is the upper k of the data buffer if the flag is not set.
A data write control circuit characterized in that when the flag is set, the first time is the upper k minutes of the data buffer, and the second time is the lower k minutes.