JPH0412491B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an operand supply device to a central processing unit in an information processing system, and particularly to an operand supply device for instructions requiring two or more relatively long operands.

<Prior Art> Conventionally, this type of information processing system, as shown in FIG. and a central processing unit 2 for execution. The main storage device 1 is
It has 8-way interleaving function by having 8 banks B0 to B7. That is, the memory addresses are assigned in the order of B0→B1→...→B7→B0→B1→..., thereby shortening the cycle time of the main memory device 1 and enabling high-speed data processing.

FIG. 2 is a time chart of memory access showing the effect of the interleaving function described above. The cycle time of each bank of B0 to B7 in the main memory device 1 is assumed to be 5T (T: unit of machine cycle), and the memory access is This is a case where they occur in the order of consecutive addresses. The rectangles in the diagram indicate the operating time of each bank,
The numbers inside the rectangle represent the access order in octal notation. From Figure 2, main memory 1 has a cycle time
Can operate at 1T.

Now, consider a case where an instruction executed by the central processing unit 2 requires two relatively long operands A and B in the main memory 1. FIG. 3 is a time chart showing the operation of an access request from the central processing unit 2 to the main storage device 1 for reading operands A and B in this case. Byte or 8-byte units) are divided in the order of storage addresses and an octal number is assigned to each, and the operands A and B are alternately read one word at a time from each bank of the main memory 1 to the central processing unit 2. It shows.

No. 1 in FIG. 3 is a case where there is no collision in each bank of the main memory device 1 during reading of all operands, and the period of reading each word of both operands is 2T as shown in the figure. No. 2 is a case where Ai (the i-th word of operand A) and Bi access the same bank in main memory 1, and since reading operand B is always in a waiting state for 4T, each word The read cycle is 6T. Similarly, in No. 3 to No. 5, there is a case where a collision occurs during operand reading in each bank of the main memory device 1.

From the above, the reading period of each word is 2T for No. 1, 6T for No. 2 and No. 4, and 3T on average for No. 3 and No. 5. That is, depending on the storage location of the operand in the main memory, the interleaving function of the main memory cannot be fully utilized, resulting in a reduction in information processing performance.

In particular, the above drawbacks directly affect information processing systems that can perform large-scale scientific and technical calculations at high speed by being able to execute vector instructions. For example, the inner product instruction, which is a typical vector instruction, calculates R←R+ 〓 ⁱ (Ai × Bi), that is, calculates the sum of the products of each element Ai and Bi of vector A and vector B on the main memory. The instruction is to store the processing in the arithmetic register in the central processing unit indicated by R, but if both vector A and vector B are stored in the main memory with consecutive addresses, the conventional example described above will occur, and the above disadvantages will be avoided. I'll accept it.

<Summary of the Invention> The purpose of the present invention is to provide a function for supplying operands to a central processing unit so that the interleaving function of the main memory can always be utilized to the maximum regardless of the storage location of the operands in the main memory. An object of the present invention is to provide an operand supply device with the following features.

An operand supply device according to the present invention includes: a first address register indicating a storage address of a first operand in a main memory; a first operand buffer for temporarily storing the first operand;
a second address register that indicates the storage address in main memory of the second operand; a second operand buffer that temporarily stores the second operand; A signal that takes the first memory address as an input and instructs which operand determined in advance is to be read out first according to the difference between the two first memory addresses, and a signal that indicates how many times the readout of the operand to be read later should be started. a read-only memory for storing a signal instructing whether to wait for an amount of time; and the first address register, first operand buffer,
and a sequence control circuit that determines update timing for each of the second address register and the second operand buffer.

The operand supply device determines in advance the order of access requests for reading each word of each operand to the main memory so that there is no conflict between access requests in each bank in the main memory, and Access requests are generated in the determined order.

<Example> Next, the present invention will be described in detail with reference to the drawings.

FIG. 4 shows an information processing system in which an operand supply device 3 of the present invention is added to FIG.
has an 8-way interleaving function by having 8 banks B0 to B7, and the cycle time of each bank is 5T. In this case, if the main memory access operations No. 1 to No. 5 in Fig. 3 can be operated as shown in No. 1 to No. 5 in Fig.
2T, and the interleaving function of the main memory device 1 can always be utilized to the maximum extent.

FIG. 6 shows an embodiment of an operand supply device that enables the operation shown in FIG. 5. The central processing unit 2 fetches and decodes the instruction to generate an initial setting signal 211 which is an initial setting instruction in the operand supply device 3, and a first signal 211 which indicates the start address on the main memory of each of the first operand and the second operand.
Address information 212 and second address information 213
It includes an instruction fetch section 21 that generates an instruction, and an instruction execution section 22 that executes an operation of an instruction.

The operand supply device 3 of the present invention uses the first address information 21 when the initial setting signal 211 is logic "1".
When 2 is “0”, the main memory address is incremented, that is, “+
a selection circuit 31 that selects the output of the "+8" circuit 34 that performs "8", and the output of the selection circuit 31 inputs the initial setting signal 211 or the first address signal 501 to the S input via the OR circuit 32; a first address register 33 set by
OR circuit 36, second address register 37, “+8” circuit 38, and first address update signal 50
1 is logic “1”, the first address register 33
When the output is “0”, the second address register 3
a selection circuit 39 that selects the output of 7 and sends address information 391 to the main memory 1;
The 8-byte long read data 101 from the 8-byte read data 101 from the 8-byte length is used as input data, the WA input is used as a write address input, the RA input is used as a read address input, and the S input is used as an input data write instruction input. This register file is a 4-word x 8-byte register file that can simultaneously read data (until the next rising edge) and write data on the rising edge of the clock signal (the write data and write address input must be supplied by then). 1 operand
Buffer 40 and initial setting signal 211 to R input
and the input data is set by the first buffer write signal 504 to the S input.
The write address register 41 and the output of the register 41 are set to “+1” and the write address for the first operand buffer 40 is incremented.
1” circuit 42 and the above circuits 40, 41 and 42
The second operand buffer 4 has the same function as
3. Second write address register 44 and “+
1” circuit 45 and the initial setting signal 211 to the R input.
The read address register 46 is cleared by the buffer read signal input to the S input, and the input data is set by the buffer read signal to the S input. The “+1” circuit 47 increments the read address, and the first address information 212 and the second
2 after receiving each lower 3 bits of address information 213.
An access request signal 503 that determines the main memory access order of two operands and requests main memory access of the main memory device 1; and a buffer read signal 50 that indicates the operand supply timing to the instruction execution unit.
6 and a sequence control circuit 50 that outputs the signal groups 501 to 505 described above.

A detailed circuit example of this sequence control circuit 50 is shown in FIG. The lower 3 bits of each of the first address information 212 and the second address information 213, a total of 6 bits, are used as address inputs, and the optimum method for each combination of the 6 address input bits is determined in a 3-bit pattern as the operand read order. 64 words stored in advance as ×
A 3-bit read-only memory 51 and an upper 1 bit of the output of the read-only memory 51 that indicates which of the first operand A or the second operand B is accessed first in the main memory as "1" or "0", respectively. As input data, initial setting signal 2
a first-out register 52 with 11 as a set input;
When the initial setting signal 211 is "1", the higher 1 bit of the output of the read-only memory 51 is set to "A", and when it is "0", it is set to A.
A selection circuit 53 that selects the output of the A/B register 54 that instructs main memory access to B or B, and an initial setting signal 2.
11 is "1", the lower 2 output of the read-only memory 51 instructs how many times to wait first before accessing the operand to be accessed later.
The bits (no wait at “01”, one wait at “10”, two waits at “11”) are set to the initial setting signal 2.
When 11 is “0”, the number of waiting times is “-1”.
1" circuit 57, a wait register 56 that sets and inputs either the initial setting signal 211 or the output of the AND circuit 59 via the OR circuit 60, and a wait register 56 that selects the output of the "1" circuit 57. The ALL “0” detection circuit 58 detects that the number of seconds has passed, and while the wait count is “0” by the ALL “0” detection circuit 58, the operand to be accessed after the one indicated by the first-out register 52 is Nantes circuits 61, 62 and AND circuit 6, which are gate groups for inhibiting main memory access
3, 64, and the first address update signal 501 and second address update signal 50 output from the AND circuit 63.
2 and outputs the access request signal 503; and the first address update signal 5.
01 and the second address update signal 502 are respectively input, and the first buffer write signal 504 and delay circuits 66 and 67 that output the second buffer write signal 505, respectively; a circuit 68 that is a gate group that selects the buffer write signal 504 or 505 for the operand that will be accessed later as indicated by the first-out register 52;
69, an OR circuit 70, and a buffer read register 71 which inputs the output of the OR circuit 70 and outputs a buffer read signal 506 which is a 1T delayed signal of the buffer write signal for the operand to be accessed later. .

FIG. 8 is a time chart showing the operation of the above circuit for the case No. 2 in FIG. In this case, the 3-bit output of the read-only memory 51 is “111”
The upper 1 bit causes main memory access to operand A to occur first, and the lower 2 bits causes main memory access to the latter operand B to wait twice in machine cycles 2 and 4 in Figure 8. It is shown that. The initial setting signal 211 brings all registers into their initial states. In "machine cycles 1 to 5", the first address update signal 501 corresponding to operand A is
The main memory is accessed by appearing A2 three times, the first
The address register 33 is incremented by "+8" and the wait register 56 is updated ("-1"), and the second address update signal 502 corresponding to operand B is
had to wait twice. In "machine cycle 6~", processing for operand A and operand B is performed alternately every machine cycle. The first buffer write signal 504 and the second buffer write signal 505 are transmitted from the first address update signal 501 and the second address update signal 502 to the main memory 1, respectively.
occurs with a delay of 7T, which corresponds to the access time of
The buffer read signal 506 is delayed by 1T from the second buffer write signal 505 for the latter operand B.
occurs. From the above, this example shows the
Operation No. 2 becomes possible. The 3-bit data pattern in the read-only memory 51 is as shown in the rightmost column of FIG.

In the above embodiment, the main memory is interleaved.
Although the case where the number of ways is 8 and the cycle time is 5T is shown, in other cases as well, it is sufficient to find the optimum solution and store the resulting pattern in the read-only memory 51 in the same manner as in FIG. It is clear that the order of operand supply by the read-only memory 51 can be controlled by so-called hard logic of a subtracter for both operand addresses and an encoder that receives the difference as input.

As explained above, the present invention has the advantage that it is possible to make the most of the performance of the main storage device and to obtain high-speed information processing performance.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a conventional example of an information processing system, Fig. 2 is a time chart explaining the interleaving function of the main storage device 1 shown in Fig. 1 (and Fig. 4), and Fig. 3 is a block diagram showing a conventional example of an information processing system. Time chart showing operation of operand access in Figure 1, No. 4
FIG. 5 is a block diagram showing an information processing system including the operand supply device 3 of the present invention, FIG. 5 is a time chart showing operand access operation according to an embodiment of the invention, and FIG. 6 is an embodiment of the invention. 7 is a circuit diagram of the sequence control circuit 50 shown in FIG. 6, and FIG. 8 is a time chart showing the operation of each circuit shown in FIGS. 6 and 7. 1: Main memory device, 2: Central processing unit, 3: Operand supply device, 21: Instruction fetch section, 22:
Instruction execution unit, 31, 35, 39, 53, 55: Selection circuit, 33: First address register, 37:
2nd address register, 40: 1st operand buffer, 41: 1st write address register, 43: 2nd operand buffer, 44:
2nd write address register, 46: read address register, 50: sequence control circuit,
51: Read-only memory, 52: First-out register,
54: A/B register, 56: Wait register, 6
6, 67: Delay circuit, 71: Buffer read register.

Claims (1)

[Claims] 1. A main memory device that stores instructions and operands, and a central processing unit that fetches instructions from the main memory device and executes the fetched instructions, and the main memory device stores information having a multi-way interleaving function. In the processing system, in order to supply an operand in the main memory to the central processing unit, a first address register indicating a storage address in the main memory of a first operand, and a first address register that temporarily stores the first operand. a first operand buffer for storing a second operand; a second address register indicating a storage address in main memory of a second operand; a second operand buffer for temporarily storing a second operand; A signal that takes two starting storage addresses of an operand and a second operand as input, and instructs which operand to read out first, which is predetermined according to the difference between the two starting storage addresses, and the operand to be read out later. a read-only memory that stores a signal instructing how many memory accesses to wait before starting readout; , 2nd address・
An operand supply device comprising: a sequence control circuit that generates update timing for each of a register and a second operand buffer.