JP2924004B2 - Instruction code transfer method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an instruction code transfer method between a CPU and a memory, and particularly to an address bus independent of a data bus.
The present invention relates to an instruction code transfer method when a connection is made between a CPU and a memory.

[Conventional technology]

Instruction codes and operands stored in the memory are provided between a control device and an arithmetic device (hereinafter, collectively referred to as a CPU) of the information processing device and a storage device (hereinafter, referred to as a memory).
In order to read data into the CPU or write data from the CPU to memory, not only the data bus for transferring operand data, but also the address bus for specifying memory addresses Tied. Fig. 3 shows a CPU using the conventional parallel data transfer method.
And a configuration between the memory and the memory. Between the CPU 301 and the memory 302,
Bidirectional data bus D, address bus A for notifying address from CPU, data transfer direction (CPU to memory: write, or memory to CPU: read), data transfer period, timing indicating transfer start timing From the CPU 301 consisting of multiple signal lines to indicate etc.
A signal line group C output to 302 is connected. CPU301
To read the data in the memory 302,
It is necessary to drive the address bus A and the signal line group C at a predetermined timing during a bus cycle. To write data, it is necessary to drive the address bus A, the data bus D, and the signal line group C at a predetermined timing during a bus cycle. That is, when the program reaches an instruction to read and reference the data of the memory operand, the address bus A and the signal line group C drive the read bus cycle MR for the address XR at which the memory operand is stored. Occur. When the program reaches an instruction to write-reference the data of the memory operand, the address bus A, the data bus D and the signal line group C drive the address XW where the memory operand is stored. Generates a bus cycle MW.

When there is no read or write for the memory operand, the CPU 301 executes the instruction to be executed in the program, so that the addresses M, M + 1, M where the instruction codes are stored are executed.
+2,... Address bus A,
And read bus cycle by driving signal line group C
F0, F1, F2,... Are sequentially generated (a read bus cycle for reading an instruction code is called a fetch bus cycle). The memory address is not continuous with respect to the immediately preceding fetch bus cycle only when CPU 301 executes a branch instruction. However, the frequency of occurrence of these branch instructions depends on the architecture of the CPU 301 and the nature of the software to be executed, but it can be said that the probability that an instruction code is accessed for consecutive addresses is considerably high. In general, it is well known that the occurrence probability of a bus cycle is in the order of fetch>read> write.

[Problems to be solved by the invention]

In recent years, the cycle time of a bus cycle generated by a CPU including a microprocessor tends to be faster than the access time of an inexpensive memory device due to an increase in the operating frequency. In order to fully exploit the performance of a high-speed CPU itself as an information processing device, it is necessary to increase the amount of information (the number of bits) of a memory operand that can be transmitted in one bus cycle.
In order to realize this, data between CPU and memory
In order to increase the bit width of the bus by a power of 2, it is necessary to increase the number of signal lines and terminals by the data bus connection,
There is a drawback that leads to an increase in apparatus scale and cost.

An object of the present invention is to provide an instruction code transfer method capable of increasing the number of instruction codes that can be transferred in one bus cycle without increasing the number of signal lines and terminals.

[Means for solving the problem]

The present invention relates to a method for transferring an instruction code from a memory connected by an address bus and a data bus to a CPU, wherein the means for detecting execution of a branch instruction in the CPU is provided by the detecting means. Means for notifying the memory that the instruction code immediately after the branch instruction is to be transferred and transferring the instruction code other than immediately after the branch instruction based on the detection state, and connecting the data on the address bus to the internal data bus A first memory bank in the memory, selectively connected to the data bus, the data bus or the address bus.
Addresses for the two memory banks according to a second memory bank selectively connected to a bus, a state notified by the notifying unit, and address information notified from the CPU via the address bus. It is characterized by comprising information generating means.

〔Example〕

Hereinafter, the configuration and operation of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram for explaining an embodiment of the present invention. As shown in FIG.
1. Stores instruction code and operand data and stores even address bank 103 and odd address bank 104
Memory 102 with the CPU101 and 16 bits that connects the memory 102 bidirectional data bus D ₁₅ -D _0, 24-bit bi-directional address bus A ₂₃ -A _0, the data transfer direction shows R / W (-) signal, valid signal indicating the transfer period of data DS (-), the address bus a _23-state signal indicating the state of use of -A ₀ ADREN (-), CPU101 instruction fetch immediately after the branch operation Is connected. In still within memory 102, even address bank 103 is connected to data bus D ₁₅ -D ₀ through 16 bits of the data buffer 105. The odd-numbered address bank 104 has a 16-bit data buffer 1
Through 06 are connected to the data bus D ₁₅ -D ₀ or via the 16-bit data buffer 107 address bus A ₂₃ lower 16 bits of _{-A 0, (A 15 -A 0} ). The address generator 108 generates an address _Am (22 bits) to be input to the memory element constituting each bank for the even address bank 103 and the odd address 104 (+1 or holding). The control circuit 109 is a circuit for controlling the data buffers 105, 106, 107 and the address generator. The CPU 101 has a 24-bit address buffer 111 and 16-bit data latches 112 and 113, and a data bus D ₁₅ -D ₀ via the data latch 112.
And the lower 16 bits of the 32-bit internal data bus, the address bus A ₁₅ -A ₀ via the data latch 113 and the upper 16 bits of the 32-bit internal data bus. As for the memory address output to the address bus A ₂₃ -A ₀ , data on the internal address bus is output via the address buffer 111. Instruction code queue 121
Is connected to the 32-bit internal data bus
Bus D ₁₅ -D _0, and lower address bus bit A ₁₅
-A A register group including a plurality of 32-bit width registers for storing a 16-bit or 32-bit width instruction code read from ₀ . The instruction code queue 121 writes the upper / lower 16 bits of the internal data bus to the upper or lower 16 bits, and
32 bits on the bus can be written together.
Although not shown in FIG. 1, the branch instruction detector 122 is positioned as a part of an instruction decoder that interprets instruction codes in 32-bit units fetched from the instruction code queue 121. This circuit detects an attempt to execute a branch instruction such as return. The control circuit 123 controls the data latches 112 and 113 and the address buffer 111, and controls the CPU 101
Is a circuit for generating ADREN (-) and FLASH (-) signals to the outside.

Next, an access operation from the CPU 101 to the memory 102 will be described. First, read operand data /
The write access operation will be described. The read or write access from the CPU 101 to the memory 102, that is, the occurrence of a bus cycle,
The generation of the DS (-) signal indicates the timing.
At the same time in synchronism with the bus cycle, the operand address is output to the address bus A ₂₃ -A _0. When the DS (-) signal is generated and the R / W (-) signal is "0", the CPU 101
Write to memory 102 from memory 102, if "1", from memory 102
This indicates a read access to the CPU 101. In the read access, DS (-) period signal is active ( "0"), the memory 1, which is specified by the address bus A ₂₃ -A ₀
02 is output on data bus D ₁₅ -D ₀
When the (-) signal returns from active ("0") to inactive ("1"), necessary data is taken into the CPU 101. On the other hand, in the write access, in synchronism with the bus cycle, operand data is output to the data bus D ₁₅ -D ₀ from CPU 101. DS (-) signal is active ( "0") from the inactive ( "1") specified by the address bus A ₂₃ -A ₀ of the memory 102 at the time of return to the address data to the bus D ₁₅ -D ₀ above Is written.

Even address bank 103 and data buffer 105
The pair when A ₁ of the address bus A ₂₃ -A ₀ is "0", the odd bank address 104 and the data buffer 1
06 of the pair, A ₁ of the address bus A ₂₃ -A ₀ is selected when the "1". The state of these operations is shown in FIG.
FIG. 5 is a diagram showing the flow of read data and addresses in the memory 102. 5 (a) shows a flow when A ₁ is "0" at the time of access, by selected signal LWEN the data buffer 105 is activated,
Data in the even address bank 103 is read to the data bus D ₁₅ -D ₀ via the data buffer 105. Further, FIG. 5 (b) shows the flow of when A ₁ is "1" at the time of access, by selected signal HWEN the data buffer 106 is activated, data of the odd-numbered bank address 104 is data Data bus D ₁₅ − via buffer 106
It is lead to D _0. A similar data flow occurs during a write access.

Next, the fetch / access operation of the instruction code will be described. For fetch access always from memory 102 to CPU
Since the data transfer to 101 is performed, the basic operation is the same as the read access (the R / W (-) signal is always inactive ("1")). However, the ADREN (-) signal and the FLASH (-) signal may be generated in synchronization with the bus cycle (the read access and the write
On access, these signals remain inactive). A bus cycle that occurs when the CPU 101 fetches the instruction code at the branch destination address when executing a branch instruction such as a jump, call, or return will be described. When the FLASH (-) signal generated only once for one branch operation becomes active ("0"), the data and address flows in the bus cycle for fetch access are as shown in FIG. And a bus cycle for read access as shown in FIG. That is,
At this time ADREN (-) signal is inactive ( "1"), the address A _m of 24-bit width from the CPU101 to the memory 102 to the address bus A ₂₃ -A ₀ is output. Address A _m that is output at this time in the upper 22 bits of the address bus _{A 23 -A 0 (A 23 -A} 2) is held in the internal address generator 108. Address bank A ₂₃ − for actual access to even address bank 103 and odd address bank 104
Address A _m on A ₂ is used. At the end of the bus cycle for a fetch access,
In preparation for access, the address A _m stored in the address generator 108 is incremented by one. When the next fetch access occurs, the address _{Am + 1} updated by the address generator 108 is used for accessing the even address bank 103 and the odd address bank 104.

Next, a description will be given of a bus cycle corresponding to an access to a continuous address after a fetch cycle at the time of execution of a branch instruction. At this time, ADREN (-) signal is active ( "0"), and the lower one of the address bus A ₂₃ -A ₀
6 bits (A ₁₅ -A ₀ ) are 1 from memory 102 to CPU 101
6-bit data is output. At this time,
When the selection signal LWEN of the data buffer 105 is activated as shown in FIG. 5C, the data in the even address bank 103 is transferred to the data bus D ₁₅ -D ₀ via the data buffer 105. When data is read and the selection signal AWEN of the data buffer 107 is activated at the same time, the data in the odd address
Via address bus A ₁₅ -A ₀ . In this case, the addresses for the even-numbered address bank 103 and the odd-numbered address bank 104 are assigned to the address bus A ₂₃ −
It not through the A _0, is generated inside the memory 102 by the address generator 108 to be described later.

The sequential fetch access, address the lower word data (16 bits wide) from the even address bank 103 to the data bus D ₁₅ -D _0, the upper word data (16 bits wide) from the odd address bank 104・ Bus A ₁₅
It is output to the -A _0. In other words, the fetch access immediately after the branch instruction is always performed in units of 2 words (32 bits) or 4 bytes in another expression, and is performed in units of a boundary between two words (the lower 2 bits of the address are 00b). Need access.

Therefore, the fetch access immediately after the branch instruction is an even word (bit 1 of address bus A ₂₃ -A ₀ , that is, A 1
_{If 1} is "0"), the next necessary instruction code is not on the boundary of two words (odd word), so the 22-bit address temporarily held in the address generator 108 for the next fetch access it is necessary to control not incremented by one a _m.

In such a continuous fetch access, if data is transferred via the address bus, data transfer at least twice the bit width of the conventional data bus together with the data bus can be performed in one bus cycle. Can be performed, that is, a double transfer rate can be obtained.

Next, a specific configuration example of each part will be described. FIG. 4 is a diagram showing a specific configuration of the address generator 108. Address multiplexer (AMPX) 131 is a 22-bit multiplexer selectively outputs the lower 22 bits A ₂₃ -A ₂ output or address bus, the address register 132 by the selection signal ASEL (ASEL is "1 "If the a ₂₃ -A _{0," 0} "if the output of the address register 132 is selected). Address register 132 is a 22-bit register, the address bus low-order 22 bits A ₂₃ -A ₂ by the strobe signal ASTB, incrementer 22-bit width increments the value of the address register 132 by the strobe signal AINC (INC) Latch the output of 133. That is, by the generation of the strobe signal ASTB,
Initialized to a value of A ₂₃ -A _2, it can be incremented by one content by the generation of the strobe signal AINC.

FIG. 6 is a diagram showing a specific configuration of a part related to a control signal of the address generator 108 in the control circuit 109.
As the selection signal ASEL, the ADREN signal is used as it is. 2
Input AND gate 144 detects that a bus cycle has occurred for fetch access immediately after the branch operation, and generates strobe signal ASTB. The strobe signal AINC is 2
Although the output of the input OR gate 147 is used, the output of the two-input AND gate 145 indicates that a bus cycle for continuous fetch access has occurred, and the bus cycle for the fetch cycle immediately after branching. Is detected by the output of the two-input AND gate 146. The falling detector 141 detects the fetch
The end of the bus cycle for access is detected, and the pulse generator 142 connected to the series generates a pulse of one clock width. Delay element 14
3 is an odd-numbered bus cycle when a one-clock-width pulse is generated by the falling detector 141 and the pulse generator 142 when the bus cycle for fetch access immediately after the branch operation is completed. It is used to hold that information (A ₁ ) indicating that the access was to a word is valid.

Although omitted here, the data buffers 105, 106, 107
The control signals LWEN, HWEN, and AWEN are realized by a combinational circuit that satisfies the following logical expression with respect to a bus cycle for fetch access.

LWEN = DS.and ((not (ADREN ) .and.not (A 1)) or.ADREN.);. HWEN = DS.and (not (ADREN) .and.A 1); AWEN = DS.and. (ADREN) Further, generation control of a bus cycle for fetch access of the control circuit 123 of the CPU 101 will be described. FIG. 7 is a flow chart showing a bus cycle control operation for fetch access of the control circuit 123;
Control of results generated by the signal ADREN, shows FLASH, the state of A _1, and a method for storing the instruction code to the instruction code queue 121 in the drawings below. In the figure, a flag is a flag for storing that preparation for continuous fetch access is not completed (the bus cycle for the immediately preceding fetch access was for an even word). Bus for continuous fetch access
At the end of the cycle, it is used to control the writing of the odd word instruction code output to the upper 16 bits of the internal data bus to only the upper 16 bits of the instruction code queue 121. Further, in the method of storing the instruction codes are shown in the drawings the bottom in FIG. 7, the instruction code word unit of is shown by dots are transferred via the data bus D ₁₅ -D _0, in the shaded It illustrates the relationship between the mean instruction code word unit that is transferred via the address bus a ₁₅ -A _D. The operation branches depending on whether the control is set, whether the fetch access is immediately after the branch instruction, or if the fetch access is immediately after the branch instruction, whether the operation is for an even word.

In the conventional instruction execution sequence in which a bus cycle for fetch access of eight times (8 words, 16 bytes) is required until a continuous branch instruction is executed, the present invention uses five buses. • Can be implemented in cycles, reducing the number of bus cycles to about 63%. Furthermore, 9 for fetch access for 16 words
Reduced to about 56% in one bus cycle, and reduced to about 53% in 17 bus cycles for fetch access for 32 words. -The number of cycles can be reduced to a minimum of 1/2 (50%).

Next, another embodiment of the present invention will be described. FIG. 2 shows the configuration of this embodiment. In this embodiment, the CPU 201 has a data bus ID dedicated to instruction codes, an address bus IA, a control signal group IC, and a data bus DD dedicated to operand data, an address bus DA, and a control signal group DC. It is characterized in that it is connected to the instruction code dedicated memory 203 and the operand data dedicated memory 202.

In the case of this configuration, since the address bus IA connected to the instruction code dedicated memory 203 does not output any address for accessing the operand data, the address bus IA is used to transfer the instruction code. The possibility of using this for the purpose is dramatically improved.

〔The invention's effect〕

As described above, when accessing the instruction code using the present invention, by using the address bus connected between the CPU and the memory as an auxiliary data bus, the number of terminals and the wiring amount can be reduced. Thus, it is possible to transfer a maximum of twice the number of instruction codes per unit time from the memory to the CPU as compared with the related art.

[Brief description of the drawings]

FIG. 1 is a block diagram for explaining a first embodiment of the present invention, FIG. 2 is a block diagram for explaining another embodiment of the present invention, and FIG. 3 is a diagram showing a conventional instruction code transfer system. FIG. 4 is a diagram specifically showing the configuration of the address generator in the first embodiment, FIG. 5 is a diagram showing the flow of data and addresses in the first embodiment, and FIG. FIG. 7 is a diagram specifically showing the configuration of the control circuit on the memory side in the first embodiment, and FIG. 7 is a diagram showing the flow of operation of the control circuit on the CPU side in the first embodiment. 101, 201, 301 ... CPU, 102, 302 ... memory, 202 ... operand data dedicated memory, 203 ... instruction code dedicated memory, 103 ... even address bank, 104 ... odd address bank, 105, 106, 107 ... data buffer, 108
... Address generator, 109 control circuit, 111 address buffer, 112, 113 data latch, 121 instruction code queue, 122 branch instruction detector, 123 control circuit, 131 ... Address multiplexer, 132 ... Address latch, 133 ... Incrementer, 141 ... Fall detector, 142 ... Pulse generator, 143 ... Delay element, 144,145,146 ... 2-input AND gate, 147 ... 2 inputs O
R gate.

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 9/38 G06F 13/16 G06F 12/02

Claims (1)

(57) [Claims] In a system for transferring an instruction code from a memory connected to a CPU via an address bus and a data bus to the CPU, the CPU includes means for detecting a branch instruction, and a branch instruction detected by the detection means. Means for supplying address information immediately after the branch instruction to the address bus when detecting the address bus, and information on the state of the address bus and the CPU without supplying address information to the address bus other than immediately after the branch instruction. Means for notifying the memory of the data, a means for connecting data on the address bus to an internal data bus other than immediately after the branch instruction, and a memory means connected to the data bus in the memory. ,
Address generation means for supplying address information notified from the CPU via the address bus by the information notified by the notification means from the CPU or new address information generated according to the address information to the memory means. Immediately after the branch instruction, the address information on the address bus is supplied to the memory means as it is, and the corresponding data from the memory means is transferred to the CPU via the data bus only. In the case other than immediately after the branch instruction, the address information generated by the address generating means is supplied to the memory means, and the corresponding data from the memory means is transmitted via both the data bus and the address bus. The CPU
An instruction code transfer method, wherein the instruction code is transferred to a computer.