JPS58111591A - Sampling pulse generating circuit - Google Patents

Abstract

PURPOSE:To obtain a smapling pulse locked accurately with an input signal, by selecting a plural signals having different phase by every prescribed time to obtain a reference signal locked with a reference phase signal of the input signal. CONSTITUTION:After an output of an oscillation circuit 31 is frequency-divided at a frequency division circuit 32, the output is applied to a delay circuit 33. Any one among plural delayed signals from the delay circuit 33 is selected at a switching circuit 34 and applied to an exclusive OR circuit 36 with a clock run- in signal of a character multiplex signal D outputted from a wave shaping circuit 12. The circuit 36 supplies an error signal representing the phase difference between the both signals to a sampling circuit 37. In the circuit 37, the error signal is sampled among a plurality of signals delaying the output signal of the switching circuit 34 by every prescribed time at a delay circuit 38 as a sampling pulse, and the output is applied to an ROM39. The ROM39 switches the switching circuit 34 so that the phase of the reference signal coincides with the phase of the clock run-in signal.

Description

[Detailed Description of the Invention] Technical Field of the Invention This invention obtains sampling pulses for sampling character data, etc. contained in the text multiplex signal, for example, in a receiver capable of receiving a text multiplex signal. The present invention relates to a sampling pulse generation circuit suitable for.

Technical Background of the Invention In general, character multiplex signals, as shown in FIG.
However, IH is superimposed on one of the horizontal scanning periods (1 horizontal scanning period) or several horizontal scanning periods.

The signal form is superimposed with a 1.0 digital signal. Figure (b) shows the format of a character multiplex signal, where A1 is a part of the header on which clock run-in signal CR, framing code FC-, etc. are superimposed, and A is character data, etc. It consists of an information section that is superimposed.

Note that SH is a horizontal synchronization signal of a television signal, and 8B is a color burst signal as well. The clock run-in signal CR is superimposed as an 8-cycle clock signal at the beginning of the header part Al, as shown in the same figure (C1).

When transmitting the character multiplex signal 8A, various data following the clock run-in signal CR are transmitted in a state in which they are synchronized with the clock run-in signal CR. In other words, the clock run-in signal CR is a reference phase signal indicating the reference phase of the character multiplex signal. The frequency of this clock run-in signal CR is '15fsc (however, fSC(2,8686M
Hz) is set to the color subcarrier frequency).

When sampling the character multiplex signal 8A on the receiving side, it is sampled using a sampling pulse SP with a frequency of 815 f''C (5,7272 MHz).In this case, the sampling pulse SP is used as a clock run-in signal C.
R (2) To synchronize (from 2, to ensure that frame code FC, character data, etc. are sampled accurately)
: has been done. FIG. 4(d) shows a pulse indicating a horizontal scanning period in which a character multiplex signal is superimposed, and is a so-called capture gate. A processing circuit for character multiplexed signals provided on the receiving side samples data of two characters during the generation period of G (G) and writes the sampled data to a buffer memory (2).

FIG. 2 is a block diagram showing an example of a character multiplex signal processing circuit. In FIG. 1, a video signal detected by a video detection circuit 11 is supplied to a waveform shaping circuit 12 and a sync separation circuit 13 (==supplied).

In the waveform shaping circuit 12, the character multiplex signal is level sliced and converted into a TTL (transistor transistor logic) level signal. In the synchronization portion I11 circuit 13, the horizontal synchronization signal 8B and the vertical synchronization signal Bv are separated. The count values of the vertical position counter 14 and the horizontal position counter 15 are reset by the vertical synchronization signal 3v and horizontal synchronization signal 19H separated by the synchronization separation circuit 13. The capture gate generation circuit 16 generates a capture gate (G) as explained in section 11m(d) at the position where the character multiplex signal is superimposed based on the power runt values of the vertical position counter 14 and the horizontal position counter 15. let

When the sampling pulse generation circuit 17 outputs the input signal G from the acquisition gate generation circuit 16, the sampling pulse generation circuit 17 performs sampling in synchronization with the clock run-in signal C1 of the character multiplexed signal converted into a TTL level signal by the waveform shaping circuit 12. Pulse SP is derived.The sampling circuit 18 samples the framing code FC, character data, etc. output from the waveform shaping circuit 12 using the sampling pulse 8P generated from the sampling pulse generation circuit 11, and The data is serial-parallel converted. The sampled data after this serial-parallel conversion is supplied to the framing code detection circuit 19. Then, character data etc. are written into the buffer memory 20 only when the framing codes PC match. .

Character data etc. written to the buffer memory 20 are sent to the RO.
M (read-only memory) CPUJ according to the 2J program, ? The data is subjected to the following processing and written into the pattern memory 23 and color memory 24. The pattern data and color data written in the pattern memory 23 and the color memory 24 are generated based on the outputs of the vertical position counter 14 and the horizontal position counter 15, and the television signal (according to the synchronized addressing signal) output from the address generation circuit 25. read out, pattern/color decoder circuit 2
6 (two supplied; this pattern/color decoder circuit 26
Then, the input data is converted into R-axis, G-axis, and B-axis color signals and luminance signals. The output signal of the pattern/color decoder circuit 26 is converted into an analog signal by the output interface circuit 21, and then supplied to a picture tube (not shown) C2 for image display.

Note that 2B is a keyboard, and 29 is, for example, 11: Il! This is a RAM (random access memory) in which display position designation data for designating the □ position at which teletext is displayed on screen Ii is stored.

Above, we have briefly described an example of a character multiplex signal processing circuit. For this reason, 42 is such that the sampling pulse SP output from the sampling pulse generation circuit 17 is the clock run-in signal CB.
By the way, in order to sample the input signal, C2, which obtains the sampling pulse 8P synchronized with this input signal, is generally divided into two types (analog method and digital method). If an analog method is adopted for sampling a character multiplex signal, the clock run-in signal CR is extracted and this Clock □ It is sufficient to synchronize the operation of an oscillator that derives the sampling pulse SP with the run-in signal CR1.Also, when adopting a digital system, the clock run-in signal CRtl- is generated at a frequency several times that of the clock run-in signal CR. By sampling, detecting the phase shift between the clock run-in signal cR and the sampling pulse for sampling this clock run-in signal CR, and synchronizing the oscillator that derives the sampling pulse SP for sampling the character multiplex signal. good.

Problems with the background technology However, when using the analog method described above,
Since the character multiplex signal (generally) only comes once per 21 fields, the gain and time constant of the synchronous circuit become a problem, which not only makes the design of the synchronous circuit difficult, but also makes the clock run-in signal C
There is a problem in that it is difficult to obtain a sampling pulse SP that is accurately synchronized with R.

In addition, when using a digital system, in order to suppress the phase shift of the sampling pulse SP to within 20 nB, the pulse for sampling the clock run-in signal CI must be set at an extremely high frequency (8 times that of the clock run-in signals C and H). (approximately 45 MHz) pulses must be used. Therefore, a counter circuit for counting these pulses becomes very expensive.

Further, the character multiplex signal is not necessarily superimposed for one horizontal scanning period of the entire retrace period, but may be superimposed for several horizontal scanning periods. In this case, since the phase of the character multiplex signal differs depending on the horizontal scanning period to be superimposed, it is necessary to correct the phase of the sampling pulse SP with the leading clock run-in signal CR for each horizontal scanning period. Therefore, as a sampling pulse generation circuit, even if the phase of the clock run-in signal CR changes (
Second, it is necessary to obtain a sampling pulse SP accurately synchronized with the clock run-in signal CR in response to this change.

Purpose of the Invention The present invention has been made to address the above-mentioned circumstances, and is capable of obtaining sampling pulses accurately synchronized with an input signal, and having a fast response to phase changes of the input signal.
Moreover, it is an object of the present invention to provide a chimpling pulse generation circuit that is easy to design, does not require an expensive counter circuit, and is suitable for generating a sampling -1-\-1 pulse for sampling a character multiplex signal.

SUMMARY OF THE INVENTION Therefore, the present invention generates a plurality of signals having the same frequency as a reference phase signal of an input signal and whose phases differ by a predetermined time, and uses any one of the plurality of signals as a reference signal to determine the reference phase. Detects the phase difference with the input signal, sequentially samples this phase difference with multiple delayed signals obtained by delaying the reference signal by a predetermined time, and determines whether the reference signal leads or lags the input signal in phase.5 , ``I, □□, see above, eh, number.'' Select a signal whose phase is delayed by a predetermined time from the reference signal currently being output from among No. 9 as the reference signal, and calculate the phase. If there is a delay, select a signal whose phase is advanced by a predetermined time as the reference signal.By repeating this process, a reference signal synchronized with the reference phase signal of the input signal is obtained, and the sampling pulse is derived from this reference signal. It is configured to obtain the following.

EMBODIMENT OF THE INVENTION Hereinafter, one embodiment of the present invention fi+/li will be explained in detail with reference to the drawings. In the following description, the case where the present invention is applied to the generation of pulses for sampling a character multiplex signal will be described as a representative example. FIG. 8 is a circuit diagram of one embodiment. First, number 3 has a frequency of 875. f” (5,7272
This is an oscillation circuit that outputs a free-run signal of MHz. The oscillation output signal of this oscillation circuit 3 is frequency-divided by a 1/2 frequency divider circuit 32 (=1/2). Each delayed signal of the delay circuit 33 is supplied to a switching circuit 34. The switching circuit 34 can arbitrarily select any one of the plurality of delayed signals of the delay circuit 33.

\,,.

A control signal for this selection is supplied from the latch circuit 35.

The output signal of the switching circuit 34 is supplied to an exclusive OR circuit 36 together with a clock run-in signal CI, which is a character multiplex signal output from the waveform shaping circuit 12. In this case, the exclusive OR circuit 36 is connected to the switching circuit 34.
Using the output signal as a reference signal, an error signal indicating the phase difference between this reference signal and the clock run-in signal CR is derived.

This error signal is supplied to a sampling circuit 37. In this sampling circuit 37, the error signal is sampled using a plurality of signals obtained by delaying the output signal of the switching circuit 34 by a predetermined time by a delay circuit 38 as sampling pulses.

Is this sampling data ROM 34? (- is supplied.The ROM 39 determines whether the phase of the reference signal is ahead or behind the phase of the clock run-in signal CR based on the sampling data, and if it is ahead, the switching circuit 3
4 outputs data that causes the delay signal whose phase is delayed by a predetermined time from the currently selected delay signal to be selected. Inverse (: If there is a delay, data is output that causes the delayed signal whose phase is advanced by a predetermined time to be selected. This data in the ROM 39 is added or subtracted from the data held in the latch circuit 35 by an adder circuit 40. , this calculation result is supplied to the latch circuit 35,
The data in the latch circuit 35 is rearranged. The new data of the latch circuit 35 is supplied as a control signal to the switching circuit 34, and the switching circuit 34 selects a delayed signal whose phase is ahead of the currently selected delayed signal by a predetermined amount of time, or a delayed signal that is delayed. . This signal is again supplied to the exclusive OR circuit 36 as a reference signal, and the above-described operation is performed again. In other words, an error signal is obtained during the l clock period of the reference signal, this error signal is sampled, the data in the latch circuit 35 is rewritten, and the signal selected by the two switching circuits 34 is switched until the next clock rises. By repeating the operation during the arrival period of the click-in signal CR, the reference signal selected by the switching circuit 34 is synchronized with the clock run-in signal CR+2.Then, the sampling pulse BP is synchronized with the clock run-in signal CR. By passing the synchronized reference signal and a predetermined delay signal among the plurality of delay signals of the delay circuit 38 obtained from the reference signal through the exclusive NOR circuit 41, a signal with a frequency of 8/, fsa is obtained.

Here, an example of the specific configuration of FIG. 8 is shown in FIG.
Its configuration and operation will be explained with reference to the timing chart shown in figure s5.

First, FIG. 5 shows the clock run-in signal CR present at the beginning of the character multiplex signal. The figure (b) shows an output signal (hereinafter referred to as a reference signal) 8s of the switching circuit 34. These clock run-in signal CB and reference signal 81
By supplying this to the F/F-OR circuit 36, an error signal S corresponding to the phase difference between the two as shown in FIG. As the phase difference between the signal J#CM and the reference signal 81 becomes smaller, it becomes smaller and becomes 0 when both signals are synchronized.

Error signal 8. is supplied to the D input terminal of ~8A to the D clip flow circuit I constituting the chimbling circuit 37 (see FIG. 8). Further, the reference signal S1 is supplied to the TTL delay lines IB to 9B forming the delay circuit 38 (see FIG. 3).

The delay amount of each TTL delay line 7B to 9B is set to about 2 Unsec. The output signals of the T and T L delay lines 2B-9B are supplied to the clock input terminals of the D flip-flop circuits IA-8A, respectively. TTL delay line 2B~9B
Output signals 83 to S L (1 respectively in FIG. 5(d) to
(k) (- is shown. In such a configuration, the D flip-flop circuits IA to 8A sample the error signal S3 at the rising edge of the output signal 83 to S1 of the TTL delay lines 2B to 9B. Accordingly, it is possible to determine how far the phase of the reference signal Sl output from the switching circuit 34 leads or lags behind the phase of the clock run-in signal CR.

For example, in the case of FIG. 5, the output signal S of the TTL delay line 2B
3, the error signal S3 is at the υ level. Even at the timing of the rise of the output signal of the next TTL delay line 3B, the error signal S is at 0 level (there are two levels).

Looking at the rising timing of the output signals of the ζ2 TTL delay lines 2B to 9B one after another, it becomes 00001111.

By looking at this sampling output, it is possible to know how much the clock run-in signal CR is behind or ahead of the reference signal 81.

Each sampling data is supplied to ROM 39. R
OMJ4J switches the switching circuit 3 based on the sampling data.
Data indicating whether to advance or shift the phase of the reference signal 81 outputted from 4 is output. This data is adder times lol! 40 (Latch circuit No. 36 = added or subtracted from the held data, and this operation result becomes the new data of the latch circuit 35. The data in the latch circuit 35 changes. 6) The switching circuit 34 is The phase of the base 11! signal 81 is switched.

That is, the switching circuit 34 has an output path 33 (
(see FIG. 8) is supplied. The delay circuit 33 has, for example, 15 TTL delay lines IC to 15c. The delay amount of each TTL delay line IC~15C is approximately: i! Q
nse. The output signal of the TTL delay line 9C, the output signal of the tube circuit, and the output signal of the TTL delay line 10C to 1
The output signal of 5C is a signal that is advanced in phase with respect to the clock run-in signal CR, and the output signals of TTL delay lines IC to 8C are signals that are delayed in phase. When the clock run-in signal CR arrives, that is, in the initial state, it is turned off! I! The circuit 34 selects the output signal of the TTL delay line 9C as the reference signal S1. The control signal for this switching circuit 34 consists of a 4-bit digital signal, and is set to 0000 in the initial state.

In the case of FIG. 5, the reference signal S1 is the clock run-in signal C.
Since it is behind M, from 10M39 onwards, the data in the latch circuit 35 is increased by 1 bit, that is, 0001.
is output and added to the data held in the adder circuit 40 (: and the latch circuit 35i2). From this 62, the output data of the latch circuit 35 increases by 1 bit, and the output data of the latch circuit 35 increases by 1 bit, and
4, the output signal of the TTL long line 10C is selected, and the phase of the reference signal 8 is advanced by 21 nsec. When changing the data held in the latch circuit 35, the ROM 39 outputs data that changes the output data of the latch circuit 8j bit by bit in order to avoid the influence of noise. The latch pulse of the latch circuit 35 is T, which is a delayed reference signal 81.
A signal obtained by inverting the output signal S8 of the TL compliance line 7B by the NOR circuit 42 is used.

This means that when the sampling of the error signal 8s is completed and the calculation operation of the adder circuit 4# is completed, the latch circuit
This is to ensure that data is rewritten.

The switching circuit 34 closes the reference signal □ S1 [The output signal of the newly selected TTLjl resistance 10C is supplied to exclusive or path No. 16 = again as the error signal S! is detected. This error signal S! is D flip-flop circuit I
A~8Δ is sampled, and the sampling data is supplied to the ROM 39. In this case, the sampling data is (JUOUOIII). Since this is ≦2, data is output from the ROM 39 that increases the data held in the latch circuit 35 (2) by 1 bit, and the adder circuit 4
It is added as 0. Latch circuit 35 (-) Due to the additional bit of data being held, switching circuit 34
Then, the output signal of the TTL delay line 11C is selected. This time, the above-mentioned processing is performed using the output signal of the TTL delay line 11C as the reference signal Sx. In this case, the sampling data becomes 00000 (Jll), and the ROM 39 outputs data that advances the data held by the latch circuit 35 (= data held by 1 bit). signal is selected as the reference signal.This makes the sampling data oo
The value becomes uuuuul, and the data in the latch circuit 1J advances by 1 bit. From this ζ2, the switching circuit 34'! The output signal of lLj extension JjC is selected as the reference signal S.

At this time, the sampling data becomes ooouuooo.

The reference signal 81 output from the switching circuit 14 from this
The output data of ROMJ# becomes 0000 since it is synchronized in phase with the a-run-in signal OR, and there is no need to manipulate the bits of the data held in the latch circuit 35.

The sampling pulse 8P is a TTLjl that complies with the reference signal B1 output from the switching circuit 34 and this reference signal 81.
It is obtained by passing the output signal 8@ of the line 5B and the exclusive NOR circuit 41&2 ('ii&6 (Fig.
1)). This means that the reference signal S1 with the frequency '/s fs c has a phase difference of 174 cycles from this reference signal 81.
By supplying the output signal 8 of the TL delay line 5B to the exclusive noor circuit 41, the frequency 1k 815
If you're getting an f80 signal, it's nothing but C-.

Note that 43 is a counter circuit. This counter circuit 4
3 clock terminal (= is TT by the waveform shaping circuit 12
A character multiplex signal converted from the LL/Bell signal C is supplied. In this case, the counter circuit 43 receives eight clock run-in signals CR present at the beginning of the character multiplex signal.
When counted, the counting operation stops. The count output is supplied to the NOR circuit 42, which prevents the latch pulse from being supplied to the latch circuit 35. From this 42, the phase of the sampling pulse 8P is fixed at the time when the clock run-in signal CM disappears.

Furthermore, since the counter circuit 43, D flip-flop circuits IA to 8A, and latch circuit 35 are connected to the capture gate output from the capture gate generation circuit 16 (see FIG. 2), there is no character multiplex signal. The period is set to be cleared. This is to increase the stability of the system when there is no character multiplex signal.

Further, the output signal of the counter circuit 4S is
4 is supplied to the gP terminal Hibiki 2 (l/).

In the above explanation, the reference signal Sl is the clock run-in signal C.
Although the explanation has been made assuming that the phase is behind that of R, the operation when the C2 base rate signal 81- is ahead of the clock run-in signal CR in phase as shown in Figures 6 (1 to 2) is as follows. In this case, since the phase of the reference signal S1 output from the switching circuit 34 is delayed, the adder circuit 40 performs binary subtraction. Find the complement, this +1
Adding the stored data to the data held in the latch circuit 35 (C2) is performed.

First, the exclusive OR circuit 364 converts the clock run-in signal CR shown in FIG. An error signal of 8 as shown in FIG.
Data 0001 is output from 9. Adder circuit 4
0 takes the complement of the 8-digit data 1110 of ROW J 9 and adds 1 to it to obtain data 1111.

Then, this data 1111 is added to the data 0000 held by the latch circuit 35, and this added data 1111 is held in the latch circuit 35. As a result, the reference signal output from the switching circuit 34 is TTL The output signal of the delay line 9C is switched to the output signal of the TTL delay line 8C.From this, the error signal S3's](rus intensity changes, and the sampling data becomes l1l(30000
becomes. At this time as well, data 0001 is output from the ROM 39, and the adder circuit 40 adds this complement 111LH2+1, which is the data 11.11, to the data 1111 held in the latch circuit 35, and this added data 111υ is latched. It is held in the circuit 35. Due to this C2, the output signal of TTL delay @yC is selected in the switching circuit 34. The sampling data at this time is 11
It becomes 000000.

At this time as well, data 0001 is output from the ROM 39, data 111O and 1111 are added in the adder circuit 4Q, and data 1101 is written in the latch circuit 35&2.

From this (2), the output signal of the TTL delay line 6C is selected in the switching circuit 34, and the sampling data is 100,000.
It becomes 00. Then, in the adder circuit 40, data 110
1 and 1111 are added, and this added data 1100
is held in the latch circuit 35. As a result, the switching circuit 34 selects the output signal of the TTL delay line 5C.

As a result, the sampling data becomes uoooooooo, the output data of the ROM 39 also becomes oooo, and the adder circuit 40 does not perform the addition operation. This results in
When the reference signal 81 output from the switching circuit 34 is synchronized with the σ run-in signal CR (: becomes). If the above-mentioned operation is repeated after this and the synchronization state is incorrect due to the influence of noise etc. The data held in the latch circuit 35 is corrected.Then, when the count value of the counter circuit 43 reaches 8('-), the data in the latch circuit 35 is fixed.

As described above, in this embodiment, the phase difference between the reference signal S1 and the clock run-in signal CR is detected during a half-clock period of the reference signal Sl, for example, during a high level period, and this detected error signal is used as the reference signal Sl. For example, a plurality of signals delayed by 2Qnsec are sampled one after another. Then, the sampling data is input to the ROM circuit 39 during the next half clock period of the reference signal Sl, for example, during the low level period. The ROM circuit 39 determines whether the reference signal Sl is ahead or behind the clock run-in signal C1 (based on the sampling data) and outputs data indicating whether to decrease or increase the data of the one-latte circuit 35 by one pit. The adder circuit 40 adds or subtracts the output data of the ROM 39 and the data of the latch circuit 35, and supplies this operation result to the latch circuit 35 as new data.The next clock of the reference signal S1 starts from C2. This is to correct the phase of the reference signal 81 beforehand.Therefore, it is possible to obtain the sampling pulse 8P accurately synchronized with the clock run-in signal CR.

Furthermore, even if the phase of the clock run-in signal CR changes, the phase of the 42 sampling pulse 8P can be quickly corrected each time, so even if the horizontal scanning period in which the character multiplex signal is superimposed changes. It is possible to generate chimpling pulses that can reliably sample C double-letter multiple symbols.

In addition, the oscillation wave number may be the same as the frequency of the chimpling pulse SP, and expensive high-speed elements are not required as circuit elements. Circuit design becomes easier.

FIG. 7 is a circuit diagram specifically showing another embodiment of the present invention as shown in FIG. 4 above. In FIG. 7, the fourth factor and the +-L part (2 are given the same symbols. In this embodiment, the exclusive NOR circuit 36 (instead of inputting the Nikrotsu run-in signal CR ≦2 , the clock run-in signal CR and the signal CR', which is obtained by delaying the clock run-in signal CR by 80 n5ec by the TTLJ extension 45, are supplied to the exclusive repeater circuit 46 (a double serial signal is supplied. The oscillation frequency of the oscillation circuit 31 is 1615, (
Bc (two set, each 'I'TL delay line 7B~8B,
The delay amounts for IC to J and 5C are 1 Q n 5 eel. Then, the exclusive OR circuit 36 outputs the pressure signal of the exclusive OR circuit 46 and the switching circuit 3.
An error signal S2 indicating a phase difference with the reference signal S1 with a frequency of 815 fsa outputted from the reference signal 81 is obtained.
TTL delay lines IB to 9B each have 1OUlII! c.
Signal 83"'- of frequency 815fSC obtained by delaying
Sampling is performed at 801 and ν remains. The operation of determining the data of the latch circuit 35 based on the sampling data is the same as in the previous example, so the explanation will be omitted here. Figure 188 (
1) to (e), the reference signal S1 is the output signal 8. of the exclusive NOR circuit 46. This is a timing chart showing the synchronization process in a state where the phase is ahead of the tJ9 figure [
a) to - are timing charts showing the synchronization process in a state where the two anti-ζ phases are delayed. In addition, Figures 8 and 9
In the figure, b indicates the clock run-in signal CR output from the waveform shaping circuit 12, and b indicates the T'L'L delay line 4.
5 shows the delayed clock run-in signal CR'. Further, C indicates the output signal of the exclusive NOR circuit 46, and d indicates the reference signal 81 output from the switching circuit 34. Further, C indicates the error signal S8 output from the exclusive first circuit 36', and (f) to - indicate signals output from the delay circuits 2B to 9B for sampling this error signal.

In the case of this embodiment, the input signal of the present invention means the output signal S. of the exclusive knob 1 circuit 46.

In this way, even in the configuration shown in FIG. 7, 42, the reference signal output from the switching circuit 34 is synchronized with the clock run-in signal CR+2, as in the previous configuration shown in FIG. 7, 42. be able to.

Furthermore, in the case of this embodiment, the reference signal 81 applied from the switching circuit 34 is directly used as the sampling pulse S.
It can be used as P. Moreover, T '1"L
The delay value of weekly delayed line IB tag 9B, Ic-15C is 2 in the previous example.
%J Because it has changed from n8ec to IUIII Geki,
A more accurate sampling pulse can be obtained.

Note that the present invention is not limited to the above embodiments. For example, the means for delaying the frequency-divided output signal of the 1/2 frequency divider 32 and the reference signal Sl may be a TTL delay line (not limited to two, but a structure that utilizes the delay of a TTL logic gate. The specific structure of each part of other models can be modified in various ways.

It goes without saying that the present invention is also applicable to circuits other than circuits that generate pulses for sampling teletext signals.

Effects of the Invention As described above, according to this invention 62, it is possible to obtain sampling pulses that are accurately synchronized with the input signal, and the response to phase changes (2) of the input signal is fast, and the circuit design is easy and expensive. It is possible to provide a sampling pulse generation circuit suitable for generating a sampling pulse for sampling a character multiplex signal without requiring a counter circuit.

[Brief explanation of the drawing]

Figures 1 (a) to (d) are signal waveform diagrams for explaining the signal format of teletext broadcasting, Figure 2 is a block diagram showing an example of a text multiplex signal processing circuit, and Figure 8 is a diagram of the present invention ( 2 is a circuit diagram showing one embodiment of the sampling pulse generation circuit, FIG. 4 is a circuit diagram showing an example of the integrated configuration of FIG. 8, FIGS. 5(a) to (1), and FIG. 6(a). 〜(凰) is a timing chart for explaining the operation of the fourth prisoner, s7 is a circuit diagram showing another embodiment of this invention, s8 is f3)〜
(e), FIGS. 9(a> to (e)) are timing charts for explaining the operation of FIG. 7. 31... Oscillation circuit, 32... l/2 frequency dividing circuit, 33
...Delay circuit, 34-...Switching circuit, 35...Latte circuit, 36...Exclusive OR circuit, 37...
・Sampling circuit, 38...Delay circuit, 39...
ROM, 40... Adder circuit, 4... Exclusive NOR circuit, 42... NOR circuit, 43... Counter circuit, 44... Inverter circuit, 45... TT
L delay line, 46° parallel circuit, IA~
8A...D flip-flop circuit, IB~9B, IC
-15C...TTL delay line.

Claims (1)

[Claims] A sampling pulse generation circuit C2 generates a sampling pulse for sampling an input signal by synchronizing it with a reference phase signal indicating the reference phase of the input signal, which is provided in the preceding order of the input signal. signal generating means for generating a plurality of signals having the same frequency as the signal and having a phase different from each other by a predetermined time period; control signal output means capable of deriving a control signal for determining which signal to select by the switching means C2 and holding this control signal; error signal detection means for detecting an error signal indicating a phase difference between a reference signal and the reference phase signal; and a delay means for delaying the signal selected by the switching means by a predetermined period of time to obtain a plurality of signals having different phases. a phase determining means for sampling the error signal using each signal of the delay means and determining whether the phase of the reference signal is ahead or behind the phase of the reference phase signal; and this phase determining means. Based on the determination result, when the phase is ahead, the switching means selects a signal whose phase is delayed by a predetermined time from the signal being selected; conversely, when the phase is delayed from the signal being selected, the switching means selects a signal whose phase is delayed by a predetermined time from the signal being selected. and rewriting means for rewriting the control signal held in the control signal output means so that a signal whose phase is advanced by 1 is selected, and the error is reduced until the phases of the reference phase signal and the reference signal are synchronized. The control signal output means (:
1. A sampling pulse generation circuit characterized in that the sampling pulse generation circuit is configured such that the operation of rewriting the held control signal is repeated every cycle of the reference signal.