JP2522193B2 - Horizontal sync signal converter - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus capable of converting a video signal, and more particularly to a horizontal sync signal conversion for converting a horizontal sync signal of a video signal whose nSCH phase changes into a horizontal sync signal whose nSCH phase does not change. Regarding the device.

[0002]

2. Description of the Related Art nSCH (SCH: sub-carrier to hor)
izontal) phase means the phase difference between the nfsc clock having a frequency n times the color subcarrier frequency fsc and the horizontal synchronizing signal.

An analog composite video signal of the PAL system is known as a video signal in which the nSCH phase fluctuates by a fixed amount for each line and the nSCH phase fluctuates in a q (predetermined integer) field period. In order to digitally process such a video signal, it is necessary to obtain a horizontal synchronizing signal whose nSCH phase does not change.

In the conventional horizontal synchronizing signal conversion device, the FIF
A horizontal sync signal in which the nSCH phase does not fluctuate has been obtained by writing and reading control to an O (First-In First-Out) memory.

FIG. 9 is a block diagram showing a conventional example. In the figure, a video signal a is input to a sync separation circuit 101 and a burst control oscillation circuit 102, respectively, and a first horizontal sync signal b and a vertical sync signal c separated from the input video signal a are output from the sync separation circuit 101. Then, the burst control oscillator circuit 102 outputs an nfsc clock d having a frequency n (integer) times the color subcarrier. Furthermore, H
The PLL circuit 103 inputs the first horizontal synchronizing signal b and outputs the first horizontal synchronizing signal b.
An mfh clock r having a frequency of m (integer) times phase locked to the horizontal synchronizing signal b is output.

Note that fsc is the frequency of the color subcarrier, fh is the horizontal frequency, and the integer m is the number of pixels in one line.

The FIFO control circuit 104 includes a first horizontal synchronizing signal b, a vertical synchronizing signal c, an nfsc clock d, and an mf.
The h clock r is input to control writing and reading of the FIFO memory 105. That is, with respect to the FIFO memory 105, the first memory at the timing of mfh clock r
The horizontal synchronizing signal b is written, and the second horizontal synchronizing signal g is read at the timing of the nfsc clock. In other words, the first horizontal synchronizing signal b is converted into the second horizontal synchronizing signal g having a different cycle by switching the write and read timings.

An example of a circuit for performing frequency conversion by writing and reading control with such a memory interposed is disclosed in Japanese Patent Laid-Open No. 63-132593.

[0009]

However, in the above-mentioned conventional apparatus, since frequency conversion is performed through the FIFO memory, a circuit group for controlling writing and reading of the FIFO memory is required. That is, two PLL circuits that generate the write and read clocks (the burst control oscillator circuit 102 and the HPL circuit in FIG. 9) are generated.
The L circuit 103) and the FIFO control circuit 104 that generates reset timing for writing and reading are essential.

Further, in the conventional device, the HPLL circuit 103 for generating the write clock r is the first horizontal synchronizing signal b.
Since it is oscillating as the phase comparison signal, the accuracy and stability of the oscillation frequency of the write clock r are not sufficient.

An object of the present invention is to have a simple circuit configuration,
An object of the present invention is to provide a horizontal sync signal converter capable of obtaining a stable horizontal sync signal without nSCH phase fluctuation.

[0012]

In the horizontal synchronizing signal converter according to the present invention, the first horizontal synchronizing signal in which the nSCH phase fluctuates over a predetermined number of fields for each line is nSC.
It is for converting into a second horizontal synchronizing signal without H phase fluctuation, and a line specifying means for sequentially specifying each line for every predetermined number of fields based on the first horizontal synchronizing signal, and an nSCH phase fluctuation of the specified line. Delay control means for sequentially generating corresponding delay amount data, and variable delay means for generating a second horizontal synchronizing signal by delaying the first horizontal synchronizing signal of the line according to the delay amount data. To do.

The horizontal synchronizing signal converter according to the present invention converts a first horizontal synchronizing signal whose nSCH phase varies line by line in a frame cycle into a second horizontal synchronizing signal having a different cycle width without nSCH phase fluctuation. And a sync separation means for generating a first horizontal sync signal and a frame sync signal based on the input video signal, and a frequency n times the color subcarrier phase-synchronized with the color burst signal included in the input video signal. A burst control oscillating means for oscillating an nfsc clock, a line identifying means for inputting a first horizontal synchronizing signal and a frame synchronizing signal to sequentially identify each line for each frame, and a first for absorbing nSCH phase fluctuation of the identified line Delay control means for sequentially generating delay amount data consisting of one delay amount and a second delay amount for achieving matching with the second horizontal synchronizing signal; and a delay amount. Variable to generate a second horizontal synchronization signal by inputting the data and delaying the first horizontal synchronization signal of the line according to the first delay amount and delaying the horizontal synchronization signal in units of nfsc clocks according to the second delay amount. And a delay means.

[0014]

The line specifying means sequentially specifies each line from the first horizontal synchronizing signal in which the nSCH phase changes for each line over a predetermined number of fields, and the delay control means, the nSCH phase fluctuation of the specified line. Are sequentially generated. According to the delay amount data, the variable delay means delays the first horizontal synchronizing signal to generate the second horizontal synchronizing signal having no nSCH phase fluctuation.

Alternatively, the line specifying means sequentially specifies each line from the first horizontal synchronizing signal in which the nSCH phase varies for a predetermined number of fields for each line, and the delay control means specifies the nSCH of the specified line. The delay amount data including the first delay amount that absorbs the phase fluctuation and the second delay amount that achieves the matching with the second horizontal synchronizing signal is sequentially generated.
According to the delay amount data, the variable delay means delays the first horizontal synchronizing signal by the total delay amount of the first delay amount and the second delay amount, and generates the second horizontal synchronizing signal having a different cycle without nSCH phase fluctuation.

[0016]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a horizontal synchronizing signal converting apparatus according to the present invention. In the figure,
The input video signal a is a television signal in which the nSCH phase fluctuates by a fixed amount for each line, and the fluctuation is repeated in a predetermined number of field cycles. In this embodiment, a PAL analog composite video signal is taken as such an input video signal a, and horizontal sync signal conversion in the case of converting this into a D2 standard digital video signal will be described.

In the analog composite video signal in the PAL system, the number of frame lines is 625, the horizontal synchronizing cycle is 64 μsec, and the number of pixels in one line is 4 fsc (17.7).
Counting at 34475 MHz gives 1135.0064 pixels. Therefore, in the PAL system, the nSC of the horizontal synchronizing signal (hereinafter, the first horizontal synchronizing signal) synchronized with the analog composite video signal is used.
The H phase varies by a constant amount (0.0064 pixels) for each line with respect to the 4fsc clock.

On the other hand, in the D2 standard PAL video signal, the number of frame lines is 625 and the horizontal synchronization period is 63.999639.
Similarly, the number of pixels in one line counted at 4 fsc is 1135 pixels, but only the 313th line and the 625th line have a period width of 2 pixels in order to maintain matching with the analog video signal in frame units. Is set to 1137 pixels.

Therefore, in order to convert the first horizontal synchronizing signal into a horizontal synchronizing signal (second horizontal synchronizing signal) synchronized with the D2 standard video signal, the first to the 312th lines and the 314th to 314th lines.
The period width of the first horizontal synchronizing signal of the 624th line is set to
It needs to be shortened by 0.0064 pixels. The configuration and operation of the horizontal synchronizing signal conversion device in such a case will be described below.

The input video signal a is input to the sync separation circuit 1 and the burst control oscillator circuit 2, respectively. The sync separation circuit 1 separates the first horizontal sync signal b and the frame sync signal c from the input video signal a, respectively, and outputs the first horizontal sync signal b and the frame sync signal c to the line address generation circuit 3.
The first horizontal synchronizing signal b is output to each delay circuit 4.
The frame sync signal c is generated from the vertical sync signal extracted from the input video signal a.

The burst control oscillating circuit 2 extracts a color burst signal from the input video signal a, and is n times as many as the color subcarrier phase-synchronized with the color burst signal (here, n =
The nfsc clock d having the frequency of 4) is generated.

The line address generating circuit 3 counts the number of lines at the timing of the first horizontal synchronizing signal b and is reset by the frame synchronizing signal c. Therefore, the count value 0 to 624 of each frame is output to the delay control circuit 5 as the line address e.

The delay control circuit 5 inputs the line address e of 0 to 624, and n of the line indicated by the address is input.
The delay amount data f indicating the delay amount required to eliminate the fluctuation of the SCH phase is generated and output to the delay circuit 4.

The delay circuit 4 delays the first horizontal synchronizing signal b according to the input delay amount data f to generate a second horizontal synchronizing signal g having no nSCH phase fluctuation and outputs it to the latch circuit 6. The latch circuit 6 performs a latch operation at the timing of the nfsc clock d, and outputs its latch output h by the D2 standard P
Output as horizontal sync signal of AL video signal.

FIG. 2 is a block diagram showing the configuration of the delay control system in this embodiment in more detail. In the figure, the line address generation circuit 3 includes a 10-bit counter 31, a mono-multivibrator 32, and a 10-bit flip-flop circuit 33.

The counter 31 inputs the first horizontal synchronizing signal b as a clock and the frame synchronizing signal c as a reset signal. Therefore, the counter 31 sequentially counts the number of lines for each frame, and the count value 0 to 624 is counted.
Is the line count number i and the flip-flop circuit 33
Output to.

The mono multivibrator 32 causes the output j to fall in synchronization with the rising of the first horizontal synchronizing signal b,
It is designed to raise the output j near the center of the line.

The flip-flop circuit 33 includes the counter 3
The line count number i, which is an output of 1, is input, and the latch timing thereof is determined by the output j of the mono multivibrator 32. Therefore, at a timing near the center of the line, the count number of the line is latched by the flip-flop circuit 33 and output to the delay control circuit 5 as a 10-bit line address e indicating any of the count numbers 0 to 624.

The delay control circuit 5 is a read-only memory (R
OM) 51. Data of an address map as illustrated in FIG. 3 is previously stored in the ROM 51. As shown in FIG. 3, the address input A9 of the ROM 51
When a 10-bit line address e is input to ~ A0,
Corresponding 8-bit output data Q7 to Q0 are output as delay amount data f. This delay amount data f is
Predetermined to absorb variations in the nSCH phase.
In addition, the number of H such as 0H and 37H in FIG. 3 is 16
Represents a base number. The same applies hereinafter.

The 8-bit output Q7 to Q0 of the ROM 51, that is, the delay amount data f is divided into upper 2 bits (Q7, Q6) and lower 6 bits (Q5 to Q0). The high-order 2 bits indicate the number of delay clocks in one clock unit of the nfsc clock d, and the low-order 6 bits indicate a delay amount that is sufficiently smaller than the cycle width of one clock of the nfsc clock d and can be set in 1-nanosecond units (for details, See below). Then, as will be described next, the sum of the delay amount indicated by the upper 2 bits and the delay amount indicated by the lower 6 bits becomes the total delay amount in the delay circuit 4.

The delay circuit 4 includes a programmable delay line 41 for inputting the first horizontal synchronizing signal b for delaying, a shift register 42 for inputting the delay output p thereof, and a selector for selecting one of four register outputs. And 43. As described above, the delay amount data f input from the delay control circuit 5 is divided into the upper 2 bits m and the lower 6 bits k, and the lower 6 bits k are programmable delay line 41.
The upper 2 bits m are input to the selector 43 as control signals.

The programmable delay line 41 can delay in the range of 0 to 63 nanoseconds in 1 nanosecond steps according to the value of the lower 6 bits k of the delay amount data f. For example, when n = 4, one clock cycle of the 4fsc clock d is about 56.38 nanoseconds, which is sufficient to set the delay amount smaller than the one clock cycle width.

Taking the case where the input address (line address e) in FIG. 3 is 623 (26 FH in hexadecimal) as an example, the lower 6 bits k of the output data (delay amount data f) of the ROM 51 is 56 (38 H). Therefore, the programmable delay line 41 delays the first horizontal synchronizing signal b by 56 nanoseconds.

The delay in the programmable delay line 41 absorbs the nSCH phase fluctuation, and the delay output p
The line pixel numbers of are all integers when counted by the nfsc clock d.

Next, in order to make the number of line pixels of the delay output p, which has become an integer, match the D2 standard video signal, the circuit including the shift register 42 and the selector 43 further delays in units of nfsc clock d.

The shift register 42 shifts the contents at the timing of the nfsc clock d. Therefore, the delay output p from the programmable delay line 41 sequentially shifts from the outputs Q0 to Q3 of the shift register 42 according to the nfsc clock d. Selector 43 has upper 2 bits m
1 output is selected from the shift register outputs Q0 to Q3 having different delay clock numbers according to the value of, and delayed as the second horizontal synchronizing signal g.

Thus, the first horizontal synchronizing signal b is delayed by the programmable delay line 41 in the range of 0 to 63 nanoseconds, further delayed by the shift register 42 and the selector 43 in units of nfsc clock d, and their total delay. Depending on the amount, the nSCH phase fluctuation is absorbed, and the second horizontal synchronizing signal g that matches the D2 standard PAL video signal is generated.

Next, the specific operation of this embodiment will be described.

FIG. 4 is a detailed timing chart for explaining the operation of this embodiment before and after the input of the 625th line of the PAL system analog video signal, and FIG. 5 is the input of the 1st line of the frame following FIG. 6 is a detailed timing chart illustrating the operation of the present embodiment before and after. 6 to 8 are schematic timing charts showing a schematic operation of this embodiment over one frame.

First, in FIG. 4, the input video signal a is P
This is an AL-type analog composite video signal, and the number of line pixels counted by 4 fsc as described above is 1135.006.
It is 4.

Prior to the input of the 625th line of the video signal a, the first horizontal synchronizing signal b output from the sync separation circuit 1 falls. At this time, the counter 31 of the line address generation circuit 3 has the line count number i = 622 indicating the 623rd line, and the output j of the mono-multivibrator 32 has not risen yet, so the line address which is the output of the flip-flop circuit 33. e
Also holds 622.

The line address e = 622 in the ROM 51.
When (26EH) is input, the ROM 51 outputs 8-bit data of (Q7Q6) = 0H and (Q5-Q0) = 00H to the delay circuit 4 as delay amount data f according to the address map shown in FIG. That is, the delay amount data f is 00H.

In the delay circuit 4, the lower 6 of the delay amount data f
The bit k = 00H is output to the programmable delay line 41, and the upper 2 bits m = 0H are output to the selector 43.

Since the lower 6 bits k are 00H, the programmable delay line 41 outputs the delay output p as it is to the register 42 without delaying the fall of the first horizontal synchronizing signal b.

The register 42 shifts the delayed output p at the timing of 4 fsc clock d, but the selector 4
3 selects the register output Q0 because the upper 2 bits m is 0H. Therefore, the trailing edge of the signal appearing at the register output Q0 at the timing of 4fsc clock d immediately after the delayed output p is input to the register 42 is output from the selector 43 as the trailing edge of the second horizontal synchronizing signal g.

Subsequently, when the first horizontal synchronizing signal b rises, the counter 31 of the line address generation circuit 3 is stepped up, the line count number i becomes 623, and the output j of the mono multivibrator 32 falls. When the vibrator output j rises at the timing near the center of the line, the line count number i of the counter 31 at that time
Is output from the flip-flop circuit 33, and as a result, the value of the line address e changes from 622 to 623.

Since the line address e has changed to 623, the ROM 51 outputs 8-bit delay amount data f = 80H according to the address map. As a result, the lower 6 bits of the programmable delay line 41 of the delay circuit 4 k =
00H is input, and the upper two bits m = 2 are input to the selector 43.
H type.

In this state, when the first horizontal synchronizing signal b immediately before the first line of the frame following the 625th line falls, the lower 6 bits k input to the programmable delay line 41 are 00H, so the first horizontal synchronizing signal is 00H. The trailing edge of the signal b is not delayed and the trailing edge of the delayed output p falls at the same timing. However, since the upper 2 bits m input to the selector 43 is 2H, the selector 43 selects the register output Q2 delayed by 2 clocks and outputs it as the second horizontal synchronizing signal g.

Subsequently, as shown in FIG. 5, the line count number i is 62 due to the rise of the first horizontal synchronizing signal b.
4, the vibrator output j rises at a timing near the center of the first line and the line address e becomes 62.
Change to 4. As a result, the ROM 51 outputs 8-bit delay amount data f = 78H according to the address map. The delay amount data f is, as illustrated in FIG.
Bit k is 38H (decimal 56), upper 2 bits m
Is 1H.

Since the programmable delay line 41 of the delay circuit 4 inputs the lower 6 bits k = 38H, the falling edge of the first horizontal synchronizing signal b is delayed by 56 nanoseconds. Further, since the selector 43 inputs the upper 2 bits m = 1H, the delay output p is delayed by one register by the register 42 and the selector 43.

The above operation is performed as shown in FIGS.
It is repeated every frame from the 1st line to the 625th line. Thus, the number of line pixels is 1135.00
The first horizontal synchronizing signal of the analog composite video signal of 64 is delayed by the programmable delay line 41, the register 42 and the selector 43 in accordance with the output data of the ROM 51 shown in FIG. 3, and the 1st to 312nd lines and the 314th to 62nd
The four lines are converted into the second horizontal synchronizing signal of the D2 standard PAL video signal in which the number of pixels is 1135, the 313th line and the 625th line are 1137.

In the present embodiment, the nSCH phase fluctuation of the horizontal sync signal in the PAL analog video signal is absorbed by the delay to generate the horizontal sync signal without the nSCH phase fluctuation. It also converts the cycle.

The present invention is not limited to the case of the video signal of the PAL system as described in the above embodiment, and in general, the horizontal synchronizing signal in which the nSCH phase fluctuation occurs in a predetermined field cycle for each line, changes the nSCH phase fluctuation. This can be applied when converting to a horizontal sync signal with no signal.

[0055]

As described in detail above, the horizontal synchronizing signal converting apparatus according to the present invention delays the horizontal synchronizing signal by using the delay amount data that absorbs the nSCH phase fluctuation of each line, and therefore is very stable. It is possible to obtain a horizontal sync signal without the nSCH phase fluctuation. Further, since the delay circuit system is used, the conventional FIFO circuit system is unnecessary, the circuit structure is simplified, and the circuit scale can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a horizontal synchronizing signal converting apparatus according to the present invention.

FIG. 2 is a block diagram showing the configuration of a delay control system in the present embodiment in more detail.

FIG. 3 is an address map diagram schematically showing stored contents of a ROM 51 in FIG.

FIG. 4 is a detailed timing chart for explaining the operation of the present embodiment before and after inputting the 625th line of the PAL system analog video signal.

FIG. 5 is a detailed timing chart explaining the operation of the present embodiment before and after the input of the first line of the frame following FIG.

FIG. 6 is a schematic timing chart showing a schematic operation of the present embodiment.

FIG. 7 is a schematic timing chart showing a schematic operation of the present embodiment.

FIG. 8 is a schematic timing chart showing a schematic operation of the present embodiment.

FIG. 9 is a block diagram showing an example of a conventional horizontal synchronization signal conversion device.

[Explanation of symbols]

 1 Synchronous Separation Circuit 2 Burst Control Oscillation Circuit 3 Line Address Generation Circuit 4 Delay Circuit 5 Delay Control Circuit 6 Latch Circuit 31 10-bit Counter 32 Mono Multivibrator 33 10-bit Flip-flop Circuit 41 Programmable Delay Line 42 Shift Register 43 Selector 51 Read Only Memory (ROM)

Claims (8)

(57) [Claims] 1. A first horizontal line in which a phase difference (hereinafter referred to as an nSCH phase) between a horizontal sync signal and an nfsc clock having a frequency n (integer) times the color subcarrier frequency fluctuates over a predetermined number of fields line by line. Sync signal is nSC
In a horizontal synchronizing signal conversion device for converting into a second horizontal synchronizing signal without H phase fluctuation, line specifying means for sequentially specifying each line for each of the predetermined number of fields based on the first horizontal synchronizing signal; Delay control means for sequentially generating delay amount data corresponding to the nSCH phase fluctuation of the line, and a variable delay for delaying the first horizontal synchronizing signal of the line according to the delay amount data to generate the second horizontal synchronizing signal. A horizontal synchronization signal conversion device comprising: 2. The line specifying means comprises a line counting circuit which sequentially counts and outputs the number of lines for each of the predetermined number of fields using the first horizontal synchronizing signal as a clock, and the delay control means comprises the predetermined number of lines. A delay control circuit that stores the delay amount data of each line in the field and sequentially outputs the delay amount data corresponding to the line according to the line count value that is sequentially output from the line counting circuit. The horizontal synchronizing signal conversion device according to claim 1. 3. The line specifying means comprises a line address generating circuit which receives the first horizontal synchronizing signal and generates an address of each line for each of the predetermined number of fields, and the delay control means comprises the predetermined number of lines. A read-only memory for storing the delay amount data of each line in several fields in advance and reading the corresponding delay amount data using the line count value sequentially output from the line counting circuit as an address. Item 2. A horizontal synchronizing signal converter according to item 1. 4. A horizontal sync signal converter for converting a first horizontal sync signal whose nSCH phase varies line by line in a frame cycle into a second horizontal sync signal having a different cycle width without nSCH phase fluctuation, wherein an input video signal is used. Sync separation means for generating the first horizontal sync signal and the frame sync signal based on the nfsc having a frequency n times as high as a color subcarrier phase-synchronized with a color burst signal included in the input video signal;
Burst control oscillation means for oscillating a clock; line identification means for inputting the first horizontal synchronization signal and the frame synchronization signal to sequentially identify each line for each frame; and the nSCH phase of the identified line. Delay control means for sequentially generating delay amount data including a first delay amount that absorbs fluctuations and a second delay amount that achieves matching with the second horizontal sync signal; Variable delay means for generating the second horizontal synchronizing signal by delaying the first horizontal synchronizing signal of the line according to one delay amount and delaying the horizontal synchronizing signal in units of the nfsc clock according to the second delay amount. A horizontal synchronization signal conversion device comprising: 5. The delay amount data is made up of a plurality of bits and is divided into two, an upper bit and a lower bit, one of which represents the first delay amount and the other of which represents the second delay amount. The horizontal synchronizing signal conversion device according to claim 4. 6. The variable delay means, according to the first delay amount, a programmable delay line capable of delaying the first horizontal synchronizing signal in a range from 0 to substantially the nfsc clock period, and according to the nfsc clock. A shift register having one input and multiple outputs capable of sequentially shifting the first horizontal synchronization signal; and a selector that selects one output from the multiple outputs of the shift register according to the second delay amount. The horizontal synchronizing signal conversion device according to claim 4 or claim 5 characterized by the above. 7. The line identifying means comprises a line counting circuit which sequentially counts and outputs the number of lines for each frame using the first horizontal synchronizing signal as a clock, and the delay control means comprises each line in the frame. 5. The delay control circuit for storing the delay amount data of, and sequentially outputting the delay amount data corresponding to the line according to a line count value sequentially output from the line counting circuit. Horizontal sync signal converter. 8. The line specifying means comprises a line address generation circuit for generating an address of each line for each frame based on the first horizontal synchronizing signal, and the delay control means comprises each line in the frame. 6. The horizontal read-only memory according to claim 4, further comprising: a read-only memory for storing the delay amount data in advance and reading the corresponding delay amount data by using a line count value sequentially output from the line counting circuit as an address. Synchronous signal converter.