JPH0379162A - Vertical oscillation circuit - Google Patents

Vertical oscillation circuit

Info

Publication number
JPH0379162A
JPH0379162A JP21803989A JP21803989A JPH0379162A JP H0379162 A JPH0379162 A JP H0379162A JP 21803989 A JP21803989 A JP 21803989A JP 21803989 A JP21803989 A JP 21803989A JP H0379162 A JPH0379162 A JP H0379162A
Authority
JP
Japan
Prior art keywords
field
rom
signal
circuit
sawtooth wave
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21803989A
Other languages
Japanese (ja)
Inventor
Satoru Kondo
悟 近藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu General Ltd
Original Assignee
Fujitsu General Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu General Ltd filed Critical Fujitsu General Ltd
Priority to JP21803989A priority Critical patent/JPH0379162A/en
Publication of JPH0379162A publication Critical patent/JPH0379162A/en
Pending legal-status Critical Current

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  • Details Of Television Scanning (AREA)

Abstract

PURPOSE:To reduce secular change due to a capacitor by generating a satisfactory sawtooth wave with linearity. CONSTITUTION:A horizontal synchronizing signal (a) and a vertical synchronizing signal (b) are inputted to a phase locked loop(PLL) circuit 1, and a clock pulse signal (c) and a reset pulse signal (d) are obtained, then, they are inputted to a counter 2. The counter 2 inputs output (g) to a ROM 3, and the field signal (e) of the PLL circuit 1 is inputted to the least significant bit of the ROM 3. Data of sawtooth wave is written on the ROM 3, and output data (h) is outputted as a step shape sawtooth wave via a D/A converter 4. At a first field and a second field, step shape waves with different size only by one LSB can be obtained by reading out the data of the odd address of the ROM 3 at a first field and the data of the even address at a second field with the field signal (e) to be inputted to the ROM 3.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 投射形プロジェクタ等テレビ映像信号を表示する機器の
垂直偏向回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a vertical deflection circuit for equipment that displays television video signals, such as a projection type projector.

〔従来技術〕[Prior art]

第3図のトランジスタ又はIC回路とコンデンサ・抵抗
(CR)の時定数回路との構成からなる自動発振回路5
のコンデンサ6の充放電特性を利用し、入力垂直同期信
号すをトリガ信号として垂直偏向用鋸歯状波F、を発生
する。しかし、コンデンサ6の充放電特性のため鋸歯状
波の直線性及び安定性に経時変化を生ずる。
Automatic oscillation circuit 5 consisting of the transistor or IC circuit shown in Fig. 3 and a time constant circuit of a capacitor and resistor (CR).
Using the charging and discharging characteristics of the capacitor 6, a sawtooth wave F for vertical deflection is generated using the input vertical synchronization signal S as a trigger signal. However, due to the charging and discharging characteristics of the capacitor 6, the linearity and stability of the sawtooth wave change over time.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

本発明は従来例に鑑みてなされたもので、コンデンサに
起因する経時変化を軽減し垂直偏向用鋸歯状波の直線性
及び安定性の改善を図ることを目的とする。
The present invention has been made in view of the conventional example, and an object thereof is to reduce changes over time caused by a capacitor and to improve the linearity and stability of a sawtooth wave for vertical deflection.

〔課題を解決するだめの手段〕[Failure to solve the problem]

本発明は、位相同期ループ(PLL)回路とデジタル発
振回路の構成からなるデジタル信号処理により、経時変
化のない直線性及び安定性に優れた垂直偏向用の鋸歯状
波を発生することに特徴がある。
The present invention is characterized in that it generates a sawtooth wave for vertical deflection with excellent linearity and stability that does not change over time using digital signal processing consisting of a phase-locked loop (PLL) circuit and a digital oscillation circuit. be.

〔作用〕[Effect]

第1図及び第2図において、水平同期信号aに同期した
クロックパルス信号Cと垂直同期信号すに同期したリセ
ットパルス信号dと、フィールド信号eとを発生する位
相同期ループ(PLL)回路1と、同クロックパルス信
号Cと同リセットパルス信号dで動作するカウンタ2.
読み出し専用メモリ(ROM)3.デジタル/アナログ
変換器4からなるデジタル発振回路とにより構成する。
1 and 2, a phase-locked loop (PLL) circuit 1 generates a clock pulse signal C synchronized with a horizontal synchronization signal a, a reset pulse signal d synchronized with a vertical synchronization signal d, and a field signal e; , a counter 2. which operates with the same clock pulse signal C and the same reset pulse signal d.
Read-only memory (ROM)3. It consists of a digital oscillation circuit consisting of a digital/analog converter 4.

カウンタ2はクロックパルス信号Cをカウントしその値
をROM3のアドレスに出力する。又、前記PLL回路
1出力のフィールド信号eを同ROM3のアドレスの最
下位ビット(LSB)に入力し、同ROM3の出力デー
タhをデジタル/アナログ変換器4を通して鋸歯状波f
を出力する。
The counter 2 counts the clock pulse signal C and outputs the value to the address of the ROM 3. The field signal e output from the PLL circuit 1 is input to the least significant bit (LSB) of the address in the ROM 3, and the output data h from the ROM 3 is converted into a sawtooth wave f through the digital/analog converter 4.
Output.

〔実施例〕〔Example〕

第1図に示す様に、複合映像信号を同期分離回路(図示
せず)に通して得る水平同期信号aと垂直同期信号すと
を位相同期ループ(PLL)回路1に入力し、同PLL
回路1にて水平同期信号aと垂直同期信号すとにそれぞ
れ同期したクロックパルス信号Cとリセットパルス信号
dとをカウンタ2に入力する。カウンタ2は9ビツトと
じ同タロツクパルス信号Cをカウントして、その出力デ
ータgを読み出し専用メモリ(ROM)3のアドレスに
入力し、同時に前記PLL回路1出力のフィールド信号
eを同ROM3のアドレスの最下位ビット(LSB)に
入力する。同ROM3にはNTSC方式に相当するライ
ン数の525で一巡する鋸歯状波のデータが書き込まれ
ており同ROM3の10ビツトの出力データhをデジタ
ル/アナログ変換器4を通して垂直偏向用の階段波状鋸
歯状波fとして出力し、後段の垂直偏向出力回路(図示
せず)に接続する。尚、ROM3のアドレスのしSBに
入力するフィールド信号eは第2図eに示すように、第
1フイールドでHレベルを出力し、又、第2フイールド
でLレベルを出力する為、第1フイールドでROM3の
奇数アドレスのデータを読み出し、又、第2フイールド
で偶数アドレスのデータを読み出すことにより、第2図
fの第1フイールドと第2フイールドとではI LSB
だけ大きさの異なる階段波となりインタレース走査をす
ることになる。
As shown in FIG. 1, a horizontal synchronization signal a and a vertical synchronization signal S obtained by passing a composite video signal through a synchronization separation circuit (not shown) are input to a phase-locked loop (PLL) circuit 1.
A circuit 1 inputs a clock pulse signal C and a reset pulse signal d synchronized with a horizontal synchronizing signal a and a vertical synchronizing signal S, respectively, to a counter 2. The counter 2 counts the same 9-bit tallock pulse signal C, inputs its output data g to the address of the read-only memory (ROM) 3, and simultaneously inputs the field signal e output from the PLL circuit 1 to the highest address of the ROM 3. Input to the lower bit (LSB). Data of a sawtooth wave that goes around in 525 lines corresponding to the NTSC system is written in the ROM 3, and the 10-bit output data h of the ROM 3 is passed through the digital/analog converter 4 to create a step wave sawtooth wave for vertical deflection. It is output as a wave f and connected to a vertical deflection output circuit (not shown) in the subsequent stage. Note that the field signal e input to the address register SB of ROM3 outputs an H level in the first field and an L level in the second field, as shown in Figure 2e. By reading data at odd addresses in ROM3 and reading data at even addresses in the second field, the first and second fields in FIG.
This results in staircase waves with different sizes, resulting in interlaced scanning.

〔発明の効果〕〔Effect of the invention〕

以上のように本発明は、位相同期ループ(PLL)回路
とカウンタ、読み出し専用メモリ(ROM)そしてデジ
タル/アナログ変換器からなるデジタル発振回路とによ
り、経時変化の無い垂直偏向用の直線性良好な鋸歯状波
を発生することで、大画面化する程偏向歪みの目立つプ
ロジェクタ等の偏向回路の垂直直線性及び安定性の改善
を図ることが出来る。
As described above, the present invention utilizes a phase-locked loop (PLL) circuit, a counter, a read-only memory (ROM), and a digital oscillator circuit consisting of a digital/analog converter to achieve good linearity for vertical deflection without changes over time. By generating a sawtooth wave, it is possible to improve the vertical linearity and stability of a deflection circuit of a projector or the like, where deflection distortion becomes more noticeable as the screen becomes larger.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の垂直発振回路の一実施例を示すブロッ
ク図、第2図は同第1図の動作波形図、第3図は従来の
垂直発振回路のブロック図である。 1は位相同期ループ回路、2はカウンタ、3は読み出し
専用メモリ、4はデジタル/アナログ変換器、Cは水平
同期信号に同期したクロックパルス信号、dは垂直同期
信号に同期したリセットパルス信号、eはフィールド信
号である。
FIG. 1 is a block diagram showing an embodiment of the vertical oscillation circuit of the present invention, FIG. 2 is an operation waveform diagram of FIG. 1, and FIG. 3 is a block diagram of a conventional vertical oscillation circuit. 1 is a phase-locked loop circuit, 2 is a counter, 3 is a read-only memory, 4 is a digital/analog converter, C is a clock pulse signal synchronized with the horizontal synchronization signal, d is a reset pulse signal synchronized with the vertical synchronization signal, e is a field signal.

Claims (1)

【特許請求の範囲】[Claims] テレビ映像信号を表示する機器において水平同期信号と
垂直同期信号とを位相同期ループ回路に接続し、同位相
同期ループ回路出力の水平同期信号に同期したクロック
パルス信号と垂直同期信号に同期したリセットパルス信
号とをカウンタに接続し、同カウンタの出力データと前
記位相同期ループ回路出力のフィールド信号とを読み出
し専用メモリに接続し、同読み出し専用メモリの出力デ
ータをデジタル/アナログ変換器に接続し、同デジタル
/アナログ変換器より経時変化の無い垂直偏向用鋸歯状
波を出力してなる垂直発振回路。
In equipment that displays television video signals, a horizontal synchronization signal and a vertical synchronization signal are connected to a phase-locked loop circuit, and a clock pulse signal synchronized with the horizontal synchronization signal and a reset pulse synchronized with the vertical synchronization signal are output from the phase-locked loop circuit. The output data of the counter and the field signal output from the phase-locked loop circuit are connected to a read-only memory, and the output data of the read-only memory is connected to a digital/analog converter. A vertical oscillation circuit that outputs a sawtooth wave for vertical deflection that does not change over time from a digital/analog converter.
JP21803989A 1989-08-22 1989-08-22 Vertical oscillation circuit Pending JPH0379162A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21803989A JPH0379162A (en) 1989-08-22 1989-08-22 Vertical oscillation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21803989A JPH0379162A (en) 1989-08-22 1989-08-22 Vertical oscillation circuit

Publications (1)

Publication Number Publication Date
JPH0379162A true JPH0379162A (en) 1991-04-04

Family

ID=16713688

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21803989A Pending JPH0379162A (en) 1989-08-22 1989-08-22 Vertical oscillation circuit

Country Status (1)

Country Link
JP (1) JPH0379162A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030059930A (en) * 2002-01-03 2003-07-12 주식회사 엘지화학 Charging And Discharging Battery
JP2005071658A (en) * 2003-08-28 2005-03-17 Sii Micro Parts Ltd Flat electrochemical cell and its manufacturing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030059930A (en) * 2002-01-03 2003-07-12 주식회사 엘지화학 Charging And Discharging Battery
JP2005071658A (en) * 2003-08-28 2005-03-17 Sii Micro Parts Ltd Flat electrochemical cell and its manufacturing method

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