JPH10336588A - Audio signal processing unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To apply scrambling/descrambling processing to an analog audio signal, without causing deterioration in sound quality in an audio signal output of a video reproducing device. SOLUTION: Scrambling is conducted, based on clock signals C1, C2, C3 generated from a timing control circuit 3 based on a video signal V. A digital audio signal D1 is converted into a data block DB1 by a block-processing circuit 5. A date data block DB1 is converted into a data block BP1, to which protection data are added at a protection data addition circuit 6, and the data BP1 are given to a scrambling circuit 7, where scrambling processing to replace odd number blocks and even number blocks of the BP1 adjacent to each other is conducted so as to obtain scrambled data block BPS ← 1. The scrambled data block BPS ← 1 are given to a block-processing release circuit 8, where the block BPS1 is converted into a scrambled digital audio signal D2 and a D/A converter circuit 9 receiving the signal D2 provides an output of a scrambled analog audio signal A2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an audio signal processing device.

[0002]

2. Description of the Related Art In the prior art disclosed in Japanese Patent Application No. 8-283750, a noise suppression is performed in a scramble system in which an audio signal is digitized, divided into arbitrary data blocks, and adjacent odd and even blocks are interchanged and output. As a method, there has been a method in which the number of data is forcibly increased or decreased so that a block break and a zero voltage point coincide with each other.

In the case of this method, noise generated at the break of a block can be suppressed, but distortion is forcibly generated in an audio signal, so that sound quality is deteriorated.

[0004]

SUMMARY OF THE INVENTION The present invention relates to a data block in which a discontinuous section occurs in the above-described scramble method in order to prevent a deterioration in sound quality due to a discontinuous section of an analog audio signal occurring around a data block break. By adding the protection data around the break and then scrambling, processing is performed so that a discontinuous section occurring on the analog audio signal occurs in the protection data portion. Accordingly, an object of the present invention is to provide a signal processing apparatus for an analog audio signal in which original audio signal data is protected and deterioration of sound quality is prevented.

[0005]

In order to solve this problem, an audio signal processing apparatus according to the present invention converts an analog audio signal into a digital audio signal at the time of scrambling and then blocks the digital audio signal, thereby replacing adjacent odd-numbered blocks and even-numbered blocks. After adding the protection data before and after the data block, the D / A conversion sampling clock is faster than the A / D conversion sampling clock.
/ A conversion.

At the time of descrambling, an A signal having the same frequency as the sampling clock for D / A conversion at the time of scrambling is used.
After the digital audio signal digitized by the / D conversion sampling clock is blocked and replaced, the added protection data is deleted, and the scramble A /
The D / A conversion is performed by the D / A conversion sampling clock having the same frequency as the D conversion sampling clock.

According to this method, in a scrambled analog audio signal, a discontinuous section near a block break can be generated in a protected data portion (a signal is deteriorated in a protected data portion). Thereby, the information of the original analog audio signal is retained.

Further, in the descrambled analog audio signal, by deleting a protection data portion near the block break (a protection data portion in which the signal has deteriorated),
Deterioration of sound quality can be prevented.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first aspect of the present invention is a synchronous signal detecting means for detecting a synchronous signal from a video signal, and a PLL for outputting a signal processing reference clock synchronized with the video signal from the synchronous signal and a phase comparison clock. Means for outputting a phase comparison clock to the PLL means and inputting the A / D conversion and D
A timing control means for outputting a sampling clock for A / A conversion and a system clock for signal processing; an A / D conversion means for converting an analog audio signal into a digital audio signal based on the sampling clock for A / D conversion; Blocking means for dividing a signal into data blocks based on the system clock, and protection data addition means for generating protection data added data blocks by adding protection data of an arbitrary number of data before and after the data blocks, A scrambler for generating a scrambled data block by exchanging adjacent odd blocks and even blocks of the protected data added data block, and a scrambled digital block by unblocking the scrambled data block. An unblocking means for generating an audio signal; and a D / A conversion means for generating a scrambled analog audio signal from the scrambled digital audio signal based on the D / A conversion sampling clock. In the audio signal, there is an effect that processing is performed so that a discontinuous section occurring near the block break occurs in the protection data portion.

According to a second aspect of the present invention, there is provided a synchronizing signal detecting means for detecting a synchronizing signal from a video signal, a PLL means for outputting a signal processing reference clock synchronized with the video signal from the synchronizing signal and a phase comparing clock, Timing control means for outputting a comparison clock to the PLL means and outputting a sampling clock for A / D conversion and D / A conversion and a signal processing system clock from the signal processing reference clock inputted; A / D conversion means for converting an analog audio signal into a scrambled digital audio signal based on the A / D conversion sampling clock, and blocking means for dividing the scrambled digital audio signal into scrambled data blocks based on the system clock And the scrambled data block A descrambling means for generating a descrambled data block by exchanging an odd block and an even block adjacent to each other, and deleting the protected data added before and after the descrambled data block. Protected data deleting means for generating a descrambled digital audio signal, protected data deleting means for generating a descrambled digital audio signal, and deblocking means for generating a descrambled digital audio signal by deblocking the protected data deleted data block. And a D / A conversion means for generating an original analog audio signal based on the D / A conversion sampling clock, thereby having an effect of performing a descrambling process on the audio signal in which deterioration of sound quality is prevented.

[0011] The third invention is the first invention, wherein D is
By making the frequency of the sampling clock for A / D conversion higher than the frequency of the sampling clock for A / D conversion, the total clock time of the audio signal after the protection data is added is prevented from changing.

[0012] A fourth aspect of the present invention is the above-mentioned second aspect, wherein A
By making the frequency of the sampling clock for / D conversion higher than the frequency of the sampling clock for D / A conversion, there is an effect that the total time of the audio signal after the protection data is deleted does not change.

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a block diagram of an audio signal processing device according to an embodiment of the present invention.

In FIG. 1, 1 is a synchronous signal detector, 2 is a PLL circuit for generating a signal processing reference clock based on a synchronous signal, and 3 is a timing for controlling A / D conversion, D / A conversion and signal processing timing. A control circuit, 4 an audio signal A / D conversion circuit, 5 a blocking circuit, 6 a protection data adding circuit, 7 a scramble circuit, 8 a deblocking circuit, and 9 an audio signal D / A conversion circuit. is there.

FIG. 2 is a block diagram showing an audio signal processing apparatus according to an embodiment of the present invention. In FIG. 2, 1 is a synchronous signal detector, 2 is a PLL circuit, 3 is a timing control circuit, 4 is an audio signal A / D conversion circuit, 5 is a block circuit, 10 is a descramble circuit, and 11 is a protected data deletion circuit. , 8 is a deblocking circuit, 9 is a D / A for audio signal
It is a conversion circuit.

FIG. 3 shows three types of analog audio signal waveform diagrams. FIG. 3A shows an original analog audio signal waveform, and FIG.
(B) is a waveform of an analog audio signal after scrambling, and FIG.
FIG. 3C shows the analog audio signal waveform after descrambling (solid line) and the original analog audio signal waveform (dotted line).
The difference between the solid line and the dotted line in (c) indicates signal degradation due to the occurrence of a discontinuous section.

FIG. 3 shows that after the original analog signal is scrambled, a discontinuous section of the signal occurs at the block delimiter. Therefore, a difference occurs between the descrambled analog audio signal and the original analog audio signal. This difference is the noise to be solved by the present invention.

FIG. 4 shows a waveform of a scrambled analog audio signal when the protection data according to the present invention is added.

In FIG. 4, protection data is assigned to a place where a discontinuous section occurs.

FIG. 5 is a schematic diagram showing a scrambling operation in one embodiment of the present invention, and FIG. 6 is a schematic diagram showing data processing in a descrambling process in one embodiment of the present invention.

In FIG. 5, the digital audio signal D1
Is an example composed of digitized audio signal data, and the numbers in the figure indicate the time-series order. The data block DB1 is a time series of a data block obtained by grouping the digital data into n blocks. At both ends of this data block DB1, as an example of implementation,
A data block BP1 to which m pieces of digital data before and after the data block are added as protection data is a data block BP1 to which protection data has been added. The scrambled data block BPS1 is generated by exchanging the odd block and the even block adjacent to this BP1. Thereafter, by unblocking, a scrambled digital audio signal D2 is created.

In FIG. 6, a scrambled data block DB2 is obtained by blocking the scrambled digital audio signal D2 again. By swapping adjacent odd-numbered blocks and even-numbered blocks in DB2, a descrambled data block BPS2 is generated. A data block in which the protected data is deleted from the BPS2 is a protected data deleted data block BP2, and a descrambled digital audio signal D3 is generated by canceling the blocking.

The processing procedure will be described with reference to FIGS. (Embodiment 1) In FIG. 1, a video signal V is inputted to a synchronous signal detector 1, and an analog audio signal A1 is inputted to an A / D conversion circuit 4.

The synchronization signal detector 1 detects a vertical synchronization signal VL from the video signal V. The PLL circuit 2 includes a phase comparison clock CB1 supplied from the timing control circuit 3.
Is supplied to the timing control circuit 3 by synchronizing with the vertical synchronizing signal VL. The timing control circuit 3 converts the A / D conversion sampling clocks C1 and D1 from the signal processing reference clock CB2.
A / A conversion sampling clock C2 and a signal processing system clock C3 are output.

At this time, the frequency of the D / A conversion sampling clock C2 needs to be set to a frequency of (n + 2m) Ｃn × C1 in order to create an area to which protection data is added.

The analog audio signal A1 is converted into a digital audio signal D1 in an A / D conversion circuit 4 based on an A / D conversion sampling clock C1. The digital audio signal D1 is input to the blocking circuit 5, and is divided into a data block DB1 having n data pieces as one block.

Thereafter, in the protected data adding circuit 6, as shown in FIG. 5, m digital audio signal data is added as protected data before and after each data block, thereby outputting the protected data added data block BP1 and the scramble circuit. 7

The scramble circuit 7 outputs a scrambled data block BPS1 by exchanging adjacent odd and even blocks of the protected data added data block BP1.

Thereafter, the deblocking is released by the deblocking circuit 8 to output a scrambled digital audio signal D2.

Finally, the D / A conversion circuit 9 converts the scrambled digital audio signal D2 into an analog audio signal A2 based on the D / A conversion sampling clock C2.

As described above, according to this embodiment, the original analog audio signal is lost by collecting discontinuous sections that may occur when the analog audio signal is scrambled into the added protection data portion. Can be prevented.

(Embodiment 2) In FIG. 2, a video signal V is inputted to a synchronous signal detector 1, and a scrambled analog audio signal A2 is inputted to an A / D conversion circuit 4.

The synchronization signal detector 1 detects a vertical synchronization signal VL from the video signal V. The PLL circuit 2 supplies the signal processing reference clock CB4 to the timing control circuit 3 by synchronizing the phase comparison clock CB3 supplied from the timing control circuit 3 with the vertical synchronization signal VL.
The timing control circuit 3 includes a signal processing reference clock CB.
4 to A / D conversion sampling clock C4, D / A
It outputs a conversion sampling clock C5 and a signal processing system clock C6.

At this time, the frequencies of the A / D conversion sampling clock C4 and the D / A conversion sampling clock C5 must be set to C4 = C2 and C5 = C1.

The scrambled analog audio signal A2 is
Based on the A / D conversion sampling clock C4,
The signal is converted into a scrambled digital audio signal D2 in the D conversion circuit 4.

The scrambled digital audio signal D2
Are input to the blocking circuit 5 and are divided into a scrambled data block DB2 obtained by blocking the same number of (n + 2m) digital data as in the first embodiment.

The descramble circuit 10 supplies the descrambled data block BPS2 by exchanging the adjacent odd and even blocks of the scrambled data block DB2.

The protected data deleting circuit 11 deletes the protected data added to the scrambled data block DB2 as shown in FIG. 4 (e), that is, m digital data from the beginning and the end, thereby deleting the protected data. The data block BP2 is output.

After that, the deblocking circuit 8 releases the block, thereby outputting the descrambled digital audio signal D3.

Finally, the D / A conversion circuit 9 converts the descrambled digital audio signal D3 into a descrambled analog audio signal A3.

As described above, according to the present embodiment, the original analog audio signal can be reproduced by deleting the protection data added when the analog audio signal is descrambled.

When an analog audio signal is temporally blocked and replaced, a discontinuous section is generated at a data connection, as shown in FIG. 3B. In the signal processing described above, by adding protection data to both ends of a block where data may be destroyed due to the occurrence of a discontinuous section, the discontinuous section generated as shown in FIG. Can be collected. At the time of descrambling, by deleting this protection data, the original analog audio signal can be retained and the occurrence of noise can be prevented.

[0043]

According to the present invention, deterioration of sound quality can be prevented by absorbing the occurrence of noise based on the discontinuous section of the analog audio signal in the protection data portion.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an audio signal processing device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an audio signal processing device according to an embodiment of the present invention.

FIG. 3 is a conceptual diagram of generation of a discontinuous section in an analog audio signal waveform to be solved by the present invention.

FIG. 4 is a conceptual diagram of an acceptable section of a discontinuous section in a scrambled analog audio signal waveform.

FIG. 5 is a schematic diagram of signal processing of the audio signal processing device shown in FIG. 1;

FIG. 6 is a schematic diagram of signal processing of the audio signal processing device shown in FIG. 2;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Synchronous signal detector 2 PLL circuit 3 Timing control circuit 4 A / D conversion circuit 5 Blocking circuit 6 Protection data addition circuit 7 Scramble circuit 8 Deblocking circuit 9 D / A conversion circuit 10 Descramble circuit 11 Protected data deletion circuit A1 analog audio signal A2 scrambled analog audio signal A3 descrambled analog audio signal BP1 protected data added data block BP2 protected data deleted data block BPS1 scrambled data block BPS2 descrambled data block CB1 Clock for phase comparison of scramble circuit CB2 Reference clock for signal processing of the scramble circuit CB3 Clock for phase comparison of the descramble circuit CB4 Reference clock for signal processing of the descramble circuit C1 / Sampling clock for D / A conversion C2 Sampling clock for D / A conversion of scramble circuit C3 System clock for signal processing of scramble circuit C4 Sampling clock for A / D conversion of descramble circuit C5 Sampling clock for D / A conversion of descramble circuit C6 System clock for signal processing of descrambling circuit D1 Digital audio signal D2 Scrambled digital audio signal D3 Descrambled digital audio signal DB1 Data block DB2 Scrambled data block V Video signal VL Vertical synchronization signal

Claims (4)

[Claims] 1. A synchronizing signal detecting means for detecting a synchronizing signal from a video signal; a PLL means for generating a signal processing reference clock synchronized with the video signal from the synchronizing signal and a phase comparing clock; Is output to the PLL means, and from the input signal processing reference clock, A
Timing control means for generating a sampling clock for / D conversion and D / A conversion and a system clock for signal processing, and A / D conversion means for converting an analog audio signal into a digital audio signal based on the A / D conversion sampling clock Blocking means for dividing the digital audio signal into data blocks based on the system clock; and protection for generating a protected data added data block by adding protection data of an arbitrary number of data before and after the data block. Data adding means, a scramble means for generating a scrambled data block by exchanging adjacent odd-numbered blocks and even-numbered blocks of the protected data added data block, and by unblocking the scrambled data block, Audio signal processing comprising: deblocking means for generating a scrambled digital audio signal; and D / A conversion means for converting the scrambled digital audio signal into a scrambled analog audio signal based on the D / A conversion sampling clock. apparatus. 2. A synchronizing signal detecting means for detecting a synchronizing signal from a video signal; a PLL means for generating a signal processing reference clock synchronized with the video signal from the synchronizing signal and a phase comparing clock; Is output to the PLL means, and from the input signal processing reference clock, A
Timing control means for generating a sampling clock for D / A conversion and D / A conversion and a system clock for signal processing, and an A for converting a scrambled analog audio signal into a scrambled digital audio signal based on the A / D conversion sampling clock / D conversion means; blocking means for dividing the scrambled digital audio signal into scrambled data blocks based on the system clock; and descrambling of the scrambled data blocks by replacing adjacent odd and even blocks. A descrambling means for generating a data block, and a protected data deleting means for generating a protected data deleted data block by deleting protected data added before and after the descrambled data block, Deblocking means for generating a descrambled digital audio signal by deblocking the protected data deleted data block; and converting the descrambled digital audio signal into the D / A signal.
An audio signal processing device having D / A conversion means for converting an original analog audio signal based on a conversion sampling clock; 3. The audio signal processing apparatus according to claim 1, wherein the frequency of the D / A conversion sampling clock is higher than the frequency of the A / D conversion sampling clock. 4. The audio signal processing apparatus according to claim 2, wherein the frequency of the A / D conversion sampling clock is higher than the frequency of the D / A conversion sampling clock.