JP2590723B2 - Digital transmission system for video signals - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital transmission system for video signals, and more particularly to an analog baseband NTS.
The C video signal is PCM-coded by A / D conversion,
The present invention relates to a digital transmission system for transmitting CM encoded data via a digital line.

[0002]

2. Description of the Related Art A sampling clock used for A / D (analog / digital) conversion of a video signal uses a clock synchronized with a color burst signal in order to avoid the influence of beat noise generated in a reproduced video signal. Has become commonplace. Therefore, when this digitized video signal is transmitted using a digital line, the standardized clock is asynchronous with the transmission line clock, and the receiving device must reproduce the standardized clock on the transmitting side by some means. is there.

As an example, the Television Society of Japan (I
TEJ) Technical Report Vol. 16 No. 62 p
p. 61 to 66 (issued in October, 1992) include a digital transmission system, and FIG. 3 shows a system block diagram thereof.

In the figure, a transmitting apparatus 100 extracts a color subcarrier frequency signal from a color burst fSS of an input video signal using a burst lock oscillator 2 to obtain a sampling clock. This sampling clock has a frequency that is four times the color subcarrier frequency fSS and is 4 fSS.

The input NTSC video signal is digitized by the A / D converter 3 at this sampling clock 4fSS, and this digital data is written to the buffer memory 4 in synchronization with the sampling clock. Data reading from the buffer memory 4 is performed in synchronization with the transmission line clock fS1 from the oscillator 9.

At this time, since the sampling clock and the transmission line clock, which is the oscillation frequency of the oscillator 9, are asynchronous, the stuffing insertion unit 5 calculates the stuff amount according to the asynchronous amount of both clocks, and The stuff processing is performed in the unit 6, and the coded video data is multiplexed into the transmission line frame using the transmission line clock. The encoding unit 7 performs data transmission to a digital line.

[0007] In the receiving device 200, the digital data from the transmission line is received by the decoding unit 15 and the transmission line clock fR1 is extracted. Stuffing terminal 1
In step 4, the amount of stuff multiplexed in the transmission path frame is calculated, the video coded data is separated from the transmission path frame in the demultiplexer 13, and after the end of staff (destuff processing), it is written into the buffer memory 11. Will be. Writing to the buffer 11 is performed in synchronization with the extracted transmission line clock fR1.

The phase lock oscillator 12 generates a clock synchronized with the frequency of the stuff-terminated data, and this clock becomes the sampling clock 4fRS on the receiving side. The data read out from the buffer memory is sent to the D / A converter 10. Is converted to an analog video signal. Buffer 1
The reading of 1 is performed in synchronization with the sampling clock 4fRS.

In the configuration shown in FIG. 3, the receiving side reproduces the sampling clock on the transmitting side and reproduces the digitally transmitted video signal into an analog signal.

On the other hand, JP-A-1-132286 and JP-A-1-241235 disclose that a color burst frequency of a video signal to be transmitted is synchronized with a transmission line clock, and a sampling clock is obtained from the video signal. Is disclosed, and FIG. 4 shows a block diagram of the transmitting side.

In the figure, a black burst signal generator 45 generates a black burst signal in synchronization with a transmission line clock and sends it to a television camera 41. The video signal from the television camera 41 is input to the A / D converter 42 and converted into data. At this time, the sampling clock is synchronized with the synchronization signal separated by the synchronization separator 46 from the video signal from the camera 41 Sampling clock generator 47 using signal
The clock generated by is used.

The digital data from the A / D converter 42 is coded with high efficiency by an encoder 43, and is buffered by a buffer memory 44.
And transmitted to the transmission line in synchronization with the transmission line clock.

With this configuration, the transmission line clock and the sampling clock are in a synchronized state, so that the receiving side can easily reproduce the sampling clock using the transmission line clock.

[0014]

In the transmitting / receiving system shown in FIG. 3, the sampling clock 4fRS on the receiving side is synchronized with the sampling clock 4fSS on the transmitting side from a macro perspective. However, microscopically, the frequency of the sampling clock is low near the transmission line frame where the stuff is inserted, and the frequency of the sampling clock is high near the frame where the stuff is not inserted. Sampling clock jitter will occur.

Although there is a method of reducing the clock jitter by devising the stuff position in the transmission line frame or using a buffer memory, the occurrence of clock jitter is unavoidable in principle. As a result, jitter of the color burst of the reproduced video signal is caused, which causes color fluctuation and color unevenness of the reproduced image. When the system shown in FIG. 3 is connected in multiple stages, jitter is accumulated in the subsequent stages, which further causes deterioration of image quality.

In the configuration shown in FIG. 4, since the output of a video signal source such as a television camera is synchronized with the transmission line clock, it is necessary to synchronize all the various video signal sources with the transmission line clock. There is a problem of lack of versatility.

An object of the present invention is to provide a video signal digital transmission system capable of reproducing a stable sampling clock on the receiving side without generating jitter superimposed on the sampling clock due to stuff transmission in principle. is there.

Another object of the present invention is to provide a digital transmission system capable of obtaining good image quality without color fluctuation and color unevenness in a reproduced image on the receiving side.

Still another object of the present invention is to provide a versatile digital transmission system which does not require synchronizing all video signal sources with a transmission line clock.

[0020]

A video signal digital transmission system according to the present invention comprises means for generating a sampling clock synchronized with a color burst of an input video signal, and converting the input video signal into a digital signal by the sampling clock. There is provided a transmission device including: a conversion unit; a transmission line clock generation unit that generates a transmission line clock synchronized with the sampling clock; and a transmission unit that transmits the digital signal to a transmission line using the transmission line clock. And the transmission path
The clock generating means divides the sampling clock by N (N
Is a positive integer) and N dividing means, and the transmission line clock is
M dividing means for dividing by M (M is a positive integer);
Means for comparing the phase of each output of the M frequency dividing means, and the phase ratio
Voltage control for oscillating the transmission line clock according to the comparison output
And oscillating means .

In another digital video signal transmission system according to the present invention, a sampling clock generating means for generating a sampling clock synchronized with a transmission line clock included in a signal received from the transmission line; And a means for converting the received signal into an analog signal.

[0022]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a system block diagram of an embodiment of the present invention, and the same parts as those in FIG. 3 are denoted by the same reference numerals. In the figure, the main signal system, which is a video signal system, is the same as the conventional system of FIG.

In the transmitting apparatus 100, a sampling clock 4fSS is generated from the color burst of the video signal by the burst clock oscillator 2, and this sampling clock becomes the sampling clock of the A / D converter 3 and the buffer memory 4 And the operation clock of the stuffing insertion unit 5.

The transmission line clock fS1 is generated by using a phase lock oscillator 8 in synchronization with the sampling clock 4fSS. The transmission line clock fS1 is read out from the buffer memory 4 by a stuffing insertion unit 5, a multiplexing unit. 6 and each operating clock of the encoding unit 7.

FIG. 2A shows a specific example of the phase lock oscillator 8 for generating the transmission line clock fS1. The sampling clock 4fSS is divided by N by a frequency divider 301 (N
Is a positive integer), and the divided output and the M divider 302 (M
Is a positive integer) and the phase comparator 303 compares the phases.

This phase comparison output is supplied to a VCO (voltage controlled oscillator) 305 via an LPF (low pass filter) 304.
Therefore, the oscillation output of the VCO 305 is controlled in accordance with the phase difference between the two clock inputs of the phase comparator 303. The output of this VCO 305 is the transmission line clock fS1
The frequency divider 302 divides the frequency by M and becomes one input of the phase comparator 303.

If the relationship between the frequency division numbers N and M of the frequency dividers 301 and 302 is such that | 4fSS / fS1-N / M | = 0 (1), the transmission path The clock and the sampling clock can be completely synchronized.

However, the color subcarrier frequency fSS in the NTSC system is 3.579545 MHz, and the frequency fs1 of the transmission clock is, for example, 19.44M.
Hz, and the frequency division numbers N and M are both integers (need to be integers due to the hardware configuration of the frequency divider), so that equation (1) cannot be completely “0”. , Is almost a value close to “0”.

For this reason, it is practically impossible for the sampling clock and the transmission line clock to be in an ideally synchronized state. Therefore, stuffing processing is required. Is the same as the conventional example.

However, according to the present invention, the sampling clock is transmitted and reproduced without being affected by the stuff / destuff on the transmission line frame in both the transmitting device and the receiving device. It becomes the clock which was done.

The clock system of the receiving device 200 will be described. The transmission line clock fR1 is extracted from the received data by the decoding unit 15, is used as an operation clock for the stuffing termination unit 14 and the separation unit 13, and is also a write clock for the buffer memory 11.

The sampling clock is reproduced by the phase lock oscillator 12 so as to be synchronized with the transmission line clock fR1.
This becomes the sampling clock 4fRS of the / A converter 10.

FIG. 2B is a block diagram showing a specific example of the phase lock oscillator 12 of FIG. The transmission line clock fR1 is frequency-divided by M in the frequency divider 401, and the frequency of the frequency-divided clock and the frequency-divided N clock of the sampling clock 4fRS by the frequency divider 402 are compared in phase by the phase comparator 403.

This phase comparison output is a control voltage of the VCO 405 via the LPF 404.
The oscillation output of No. 5 becomes the sampling clock 4fRS and is reproduced.

On the receiving side as well, by satisfying the relationship of | 4fRS / fR1-N / M | = 0 (2), the transmission line clock and the sampling clock are completely synchronized. , Earlier (1)
As described in the equation, the frequency values of fRS and fR1, N, M
Due to restrictions such as the integer value of, it cannot actually be “0”, but is limited to a value close to almost zero.

[0037]

As described above, according to the present invention, the transmission side generates the transmission line clock from the sampling clock extracted from the color burst of the video signal, and the reception side reproduces the sampling clock from the transmission line clock. In principle, jitter superimposed on the sampling clock due to stuff transmission does not occur, and stable reproduction of the sampling clock is possible, enabling high quality reproduction without color fluctuation and color unevenness,
There is an effect that a versatile digital transmission system can be obtained.

[Brief description of the drawings]

FIG. 1 is a system block diagram of an embodiment of the present invention.

2 (A) is a block diagram of a phase lock oscillator 8 of the transmission device of FIG. 1, and FIG. 2 (B) is a block diagram of a phase lock oscillator 12 of the reception device.

FIG. 3 is a block diagram showing an example of a conventional video signal digital transmission system.

FIG. 4 is a block diagram showing another example of a conventional video signal digital transmission system.

[Explanation of symbols]

 Reference Signs List 2 burst lock oscillator 3 A / D conversion unit 4, 11 buffer memory 5 stuffing insertion unit 6 multiplexing unit 7 encoding unit 8, 12 phase lock oscillator 10 D / A converter 13 separation unit 14 stuffing termination unit 15 decoding unit

Claims (4)

(57) [Claims] 1. A means for generating a sampling clock synchronized with a color burst of an input video signal, a means for converting the input video signal into a digital signal using the sampling clock, and a transmission line synchronized with the sampling clock possess a line clock generating means for generating a clock, a transmitting apparatus and a sending means for sending the digital signal to the transmission line by using the line clock, the line clock generating means, the sampling clock To
N dividing means for dividing by N (N is a positive integer);
Means for dividing the clock by M (M is a positive integer);
Means for comparing phases of respective outputs of the N and M frequency dividing means;
The transmission line clock is oscillated according to the phase comparison output.
And a voltage-controlled oscillating means . 2. A transmission means comprising: memory means for writing the digital signal in synchronization with the sampling clock and reading in synchronization with the transmission line clock; and a phase difference between the sampling clock and the transmission line clock. Means for performing a stuffing process on a read signal from the memory means in accordance with the above, and means for multiplexing the stuffed signal into a transmission line frame using the transmission line clock and transmitting the multiplexed signal. The digital transmission system according to claim 1 . 3. Sampling clock generation means for generating a sampling clock synchronized with a transmission line clock included in a reception signal from the transmission line, and means for converting the reception signal into an analog signal by the sampling clock. Furthermore digital transmission system according to claim 1, wherein further comprising a receiving apparatus including a. 4. The sampling clock generating means includes an M frequency dividing means for dividing the transmission line clock by M, an N frequency dividing means for dividing the sampling clock by N, and N and M frequency dividing means. 4. The digital transmission system according to claim 3 , further comprising: means for comparing the phases of the outputs of the means; and voltage-controlled oscillating means for oscillating the sampling clock in accordance with the phase comparison output.