JP2605435B2 - PCM transmission device, PCM reception device, digital audio interface format data transmission device, and digital audio interface format data reception device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PCM transmission device for transmitting or receiving an audio signal or its receiving device, or a digital interface format data transmitting device or a receiving device.

2. Description of the Related Art With the development of various transmission techniques, multiplex transmission techniques for video signals and audio signals have been remarkably developed in recent years. In particular, with the development of optical transmission technology, high-quality long-distance transmission of digitized video and audio signals has been realized. Optical transmission technology is also being adopted in the field of video equipment for broadcasting.

In the case of digitizing an audio signal, a sampling frequency of 48 kHz is now becoming a standard as seen in a digital audio tape recorder (hereinafter abbreviated as DAT). Also, the standard of the quantization bit number is 16 bits or more.

Next, the sampling frequency of the video signal is the color subcarrier frequency fsc (about 3.58 MHz) in the case of the NTSC composite signal.
Double 4fsc (about 14.3MHz) is most often used. In the case of component signals, 13.5 MHz sampling is becoming standard (for example, see CCIR recommendation 601).

When a video signal and an audio signal are multiplexed and transmitted, the normal audio signal is transmitted according to the transmission speed of the video signal. Therefore, conventionally, any one of the following three types has been used.

(1) A method in which the sampling frequency of an audio signal is set to an integer fraction of the sampling frequency of a video signal.

In this case, the audio signal may be transmitted once for every K video signals (K is an integer), so that the circuit configuration is simplified. For example, if the sampling frequency of the audio frequency is 1/72 of fsc, it is about 49.2 kHz. In the case of 49.2 kHz sampling, the audio transmission band is almost the same as 48 kHz and there is no difference in actual sound quality, but there is a problem that the sampling frequency is non-standard.

(2) A method in which a clock having a sampling frequency of 48 kHz for audio signals is created from a sampling frequency of video.

The 48 kHz clock and the video sampling clock are not in an integer ratio, but rather in N / M fractions.

Now, as a clock for serial transmission of audio
Consider the case of using 3072 kHz, which is 64 times the 48 kHz clock. The audio data is also 3072 kbps serially. 3072 kHz and the color sub-carrier frequency fsc are 11264/13125
Ratio. fsc divided by 13125 and 3072kHz by 1.
The frequency divided by 1264 becomes the same (3 / 11kHz). Therefore, a voltage-controlled oscillator that oscillates at a frequency of 3072 kHz is used, the output frequency is divided by 11264, and the fsc is set to 1312.
The phase can be compared with that of the frequency-divided signal by a PLL circuit, and the comparison output can control the voltage-controlled oscillator to achieve synchronization. From the viewpoint of data, it is only necessary to send 11264 pieces of 3072 kbps data to 13125 pieces of video signals and send out the remaining 1861 pieces including non-data. There are various methods for such transmission, and for example, a method of forming and transmitting a multi-frame is often used. In this way, it is possible to transmit 48 kHz data in synchronization with the video reference clock fsc.

However, this method uses the video reference clock and 48
If the input of the kHz system is asynchronous, that is, if the input is an external clock, it cannot be handled. In such a case, the following staff synchronization technique is used.

(3) Staff synchronization method When the video reference clock and the 48kHz input are asynchronous,
That is, when the audio signal is a 48 kHz system but is an external clock, that is, when the audio signal is asynchronous with the video clock, a method called stuff synchronization is used. In this method, a multi-frame is constituted by a video clock, and
In this method, the number of 48 kHz clocks is counted between frames, and the data corresponding to the number is transmitted.

Now, when sending 3072 kbps data, the speed increase rate is fs
c / 3072 = 1.16 ... Therefore, if one frame length is 17
If it is 5, the data will be 175 / 1.16 = 150.86 ... Therefore, there are 150 frames in one frame and 151 frames in another frame. In the case of transmitting 151 pieces in one frame, a stuff bit indicating that the stuff processing has been performed is set so that the receiving side can determine. In this way, it is possible to perform stuffing (stuffing) on asynchronous data, and synchronize and transmit the data.

Note that the above story applies to all composite signals
The case where fsc is used has been described, but the concept is completely the same when a frequency of 13.5 of 13.5, 3.375 MHz, corresponding to a component signal is used (naturally, each numerical value is different).

Accordingly, when the 48 kHz data is synchronized with the video reference clock, when the data is asynchronous, when the fsc corresponding to the composite signal is used as the reference clock of the video signal, and when the 3.375M corresponding to the component signal is used.
For each case where Hz is used, there are four combinations shown below.

(A) 48kHz audio input synchronized with video clock fsc
(b) When transmitting a 48 kHz audio input that is asynchronous with the video clock fsc at the rate of fsc.

(C) When transmitting a 48 kHz audio input synchronized with a video clock of 3.37 MHz at a rate of 3.375 MHz.

(D) 48kHz which is asynchronous with the video clock 3.375MHz
When transmitting audio input at a rate of 3.375 MHz.

Also, the transmission data of the digital audio interface format with a sampling frequency of 48 kHz is 48 kHz x 64 bits = 3072 kbps as data, but it is 6144 kbps doubled as seen as an NRZ signal because it performs biphase modulation. . The data in the digital audio interface format is naturally an asynchronous input, and the stuff synchronization method (3) is used. In this case, the transmission clock is also 2 fsc (about 7.16).
MHz) or 6.75 MHz (3.375 MHz × 2).

Problems to be Solved by the Invention Conventionally, when transmitting 48 kHz audio with a video reference clock, a frame configuration corresponding to each of the above cases (a), (b), (c), and (d) is provided. The realization circuit for that was used. Conversely, if any one configuration is adopted, it cannot cope with other cases. Therefore, in order to deal with all of the above, it is necessary to have all of the above four circuit configurations. Further, in transmission in actual video equipment, it is important to support all of the above four combinations.

Also, when transmitting data in the digital audio interface format of 49 kHz sampling, the data amount and the transmission clock are the same as those in (a) and
Since it is twice as large as in the cases of (b), (c) and (d), in this case, it must be realized with a frame configuration and a circuit configuration completely different from the case of 3072 kbps transmission.

Means for Solving the Problems The PCM transmission device of the present invention has fsc and 1 as a transmission clock.
A first selector for selecting 3.5 / 4 MHz, and the number of bits 175 per frame when the first selector selects fsc, and the number of bits 165 for one frame when 13.5 / 4 MHz is selected. A multi-frame counter for composing a multi-frame with 75 frames, and an output of a voltage-controlled oscillator for oscillating a clock of an integral multiple of 3072 kHz.
A PLL circuit configured by controlling the voltage-controlled oscillator by comparing the phase of the divided-by-4 output with the output of the multi-frame counter, and synchronously transmits 3072 kbps data or asynchronously (stuff synchronization) A second selector for selecting whether to transmit data, a stuff control circuit for counting the number of data input during one cycle of the frame counter, and a buffer provided for reading out data input at 3072 kHz clock with a transmission clock. When the memory and the second selector select synchronous transmission, 151-bit data is inserted into 14 out of 75 frames of the multi-frame and 150-bit input data is inserted into the remaining 61 frames. When the second selector selects asynchronous transmission, the number of data to be inserted in one frame is determined by the stuff control circuit. The problem in the conventional example described above is solved by using a frame configuration circuit that selects and inserts 150 bits and 151 bits according to the output.

Further, the PCM receiving apparatus of the present invention uses f
a first selector for selecting sc and 13.5 / 4 MHz, and counting the number of bits 175 in one frame when the first selector selects fsc, and selecting a bit for one frame when selecting 13.5 / 4 MHz. A frame counter for counting the number 165, a multi-frame counter for composing 75 multi-frames with the frames, and a frame for receiving transmission data transmitted from the frame configuration circuit according to the above aspect (1). Reconstructing circuit, a second selector for specifying whether the received data is transmitted synchronously or asynchronously (stuff-synchronously), and a second selector for specifying the second data from the reconstructed frame. If the selector selects synchronous transmission, 151 from 14 frames
Bit data, and 150-bit data from the remaining 61 frames. If the second selector selects asynchronous transmission, the stuff bit indicating stuff processing in the transmission data is checked, and stuff is present. In the case of (1), the number of data to be extracted is 151 bits, and if there is no stuff, the output is from a deframe circuit that selects 150 bits and the output of a voltage-controlled oscillator that oscillates a clock that is an integral multiple of 3072 kHz.
Looking at the first frequency dividing circuit that divides the frequency by 264 and the stuff bit detected by the deframe circuit in the case of asynchronous transmission,
A second frequency divider that divides the output of the voltage-controlled oscillator by 151 if there is stuff, and a 150 that if there is no stuff, and a case where the second selector selects synchronous transmission. Selects the output of the first frequency divider, and the third selector, which selects the output of the second frequency divider when the second selector selects asynchronous transmission, is synchronized with the third selector. Multi-frame if transmission is selected
When the counter output is selected, and when the second selector has selected asynchronous transmission, the output of the third selector and the output of the fourth selector for selecting the frame counter output are compared in phase. The PLL circuit configured by controlling the voltage-controlled oscillator with an output and a buffer memory provided for reading data input at 3072 kHz by a transmission clock have the above-described problems in the conventional example. Is the solution.

The digital audio interface format data transmission device of the present invention inputs data that will be 6144 kbps when viewed as an NRZ signal obtained by converting 48 kHz sampling audio data into a digital audio interface format, and A clock extracting circuit for extracting the clock of the clock circuit, a frequency dividing circuit for dividing the output of the clock circuit by 、, and a digital audio interface format data of 6144 kbps by the output of the frequency dividing circuit into two systems of 3072 kbps. A demultiplexer for sharing data, a first output of the demultiplexer and a first PCM transmission device for inputting a 3072 kHz clock from the frequency divider, and a second output of the demultiplexer and the frequency divider. From 3072kH
It comprises a second PCM transmission device for inputting the clock of z, and solves the problems in the above-mentioned conventional example.

A digital audio interface format data receiving device according to the present invention comprises first and second PCM receiving devices for respectively receiving data of two transmission clocks from a digital audio interface format data transmitting device. A clock generating circuit for generating a 6144 kHz clock from a 3072 kHz clock obtained from the first PCM receiving device and the second PCM receiving device, and an output of the first PCM receiving device and the second PCM receiving device. It comprises a multiplexer for multiplexing certain 3072 kbps data to reproduce a signal of a 6144 kbps digital audio interface format, and solves the above-mentioned problems in the conventional example.

According to the PCM transmission apparatus of the present invention, for a synchronous input / asynchronous input data of 3072 kbps, by realizing the frame configuration according to the present invention even when the video reference clock is selected to be fsc or 13.5 / 4 MHz as the transmission clock, For the above four combinations, transmission can be realized in any case with a common and simple circuit configuration.

In the PCM receiving apparatus of the present invention, even if the transmission data from the PCM transmission apparatus is 3072 kbps data synchronous / asynchronous with the transmission clock, and the video reference clock is either fsc or 13.5 / 4 MHz as the transmission clock, By realizing the frame configuration according to the present invention, the circuit configuration is largely shared for the above four combinations, and the original 3072 kbps can be obtained from the received transmission signal in any case with a simple configuration.
Can be reproduced.

The digital audio interface format data transmission device of the present invention converts a digital audio interface format signal of 48 kHz sampling into two systems of 3072 kbps data,
Transmission can be achieved by using two PCM transmission devices. In addition, with this configuration, each PCM
2 channels of 3072 kbps data by switching the mode and input of the transmission device (any combination of synchronous and asynchronous is possible)
And four types of asynchronous data in a 6144 kbps digital audio interface format.

The digital audio interface format data receiving apparatus of the present invention is capable of receiving 2 bits from the transmitting apparatus.
The transmission data of the system is received, the reception processing of each transmission data is performed by using two PCM receivers, and after the processing, a large amount is again transmitted, thereby transmitting the data of the digital audio interface format of 48 kHz sampling. Is made possible. Also,
With this configuration, the mode of each PCM transmission device,
By switching the input, it is possible to cope with two kinds of data of 3072 kbps data (any combination of synchronous / asynchronous is possible) and asynchronous data of 6144 kbps digital interface format.

Examples Hereinafter, examples of the present invention will be described.

First, the frame configuration used in the present invention will be described,
Next, an embodiment of a PCM transmission circuit and a PCM receiving circuit that converts 3072 kbps data into a video reference clock in this frame configuration and transmits and receives the video reference clock will be described with reference to the drawings.

First, consider a case where synchronous transmission is performed for a frame configuration.

Video reference clock fsc, 3.375MHz (13.5 / 4MHz
Frequency divided by 4) and audio clock 3072kHz (48k
Hz x 64), fsc = 30 x 525 x 455/2 x 1000/1001 = 2 ³ x 3 ² x 5 ⁷ x 7/11 (Hz) = 3 ² x 5 ⁴ x 7/11 (KHz)… (1) 3072kHz = 3 × 2 ¹⁰ (kHz)… (2) 3.375MHz = 3 ³ × 5 ³ (kHz)… (3) Therefore, the equations (1), (2) and (3) If the multi-frame frequency is selected to be 3/11 kHz as a common value, the data of the clock frequency fsc is 3 × 5 ^{4 in} one multi-frame.
× 7 = 13125, data with a clock frequency of 3.375 MHz is 3 ²
× 5 ³ × 11 = 12375 data with 3072kHz clock frequency
2 ¹⁰ × 11 = 11264 pieces will be included. Therefore, when selecting fsc as the video reference clock, the clock frequency f
It is sufficient to insert 11264 pieces of data having a clock frequency of 3072 kHz into 13125 pieces of data of sc. Similarly, when 3.375 MHz is selected as the video reference clock, 11264 data at the clock frequency of 3072 kHz may be inserted into 12375 data at the clock frequency of 3.375 MHz.

Adopts multi-frame configuration, fsc and 3.375
If the number of frames per multi-frame is 75, which is the greatest common divisor of 13125 and 12375, so that it can be shared with the case of MHz, the number of data per frame is 1 when fsc
In the case of 75 and 3.375 MHz, it becomes 165. This corresponds to selecting a frame counter period of 175 or 165 depending on the selection of fsc or 3.375 MHz when specifying the video reference clock.

Therefore, the number of 3072 kHz data stored per frame is 11264/75 = 150.18..., And it is sufficient to set 61 frames for 150 data and 14 frames for 151 data. Of course, this value is fsc, 3.375M
Hz is exactly the same.

For fsc, 3072 kbps data out of 175 is 150 or 151, and for 3.375 MHz, 3072 kb out of 165.
The data of ps becomes 150 or 151 pieces. Therefore, in the case of fsc in order to achieve commonality, the 10-bit difference in the number of data may be a dummy bit in which no data is inserted. Therefore, information necessary for transmission may be added to 165−151 = 14 data.

Information for that purpose includes a multi-frame synchronization pattern and a frame synchronization pattern. Further, an error correction code for correcting an error occurring during transmission may be inserted. In this configuration, any combination is possible as long as the total is 14 pieces.

To synchronize the video reference clock with the clock of 3072 kHz, the frame frequency obtained by dividing the video reference clock by 175 (when fsc is selected) or 165 (when 3.375 MHz is selected) is further increased by 75 minutes. The frequency is obtained by synchronizing the frequency of 3/11 kHz and the frequency of 3/11 kHz obtained by dividing the 3072 kHz clock by 11264 using a PLL circuit.

Next, consider a case where the video reference clock and 3072 kbps data are asynchronous. In such a case, a method called stuff synchronization is used as described in the conventional example.

Now, when 3072 kbps data is sent at the speed of fsc, the speed increase rate is fsc / 3072 = 1.1522. Therefore, assuming that one frame length is 175, as in the case of the synchronization, the data is 175 / 1.1652... = 150.186. Similarly, 3
If the data of 072 kbps is transmitted at a speed of 3.375 MHz, the rate of increase is 3375/30722 = 1.0986. Therefore, in this case, if the length of one frame is 165, the data is 165 in this.
/1.0986=150.186 ... Therefore, in either case, 1
The number of data in the frame becomes 150 or 151. Therefore, the number of 3072 kHz clocks counted in one frame is counted, and when 151 clocks are transmitted, a stuff bit indicating that stuff processing has been performed is set so that the receiving side can determine. This stuff bit may be used from among the above 14 data.

In this way, the frame configuration can be used for asynchronous transmission,
It can be realized in exactly the same way as in the case of synchronous transmission. In the case of asynchronous transmission, it is determined using a stuff detection circuit whether 150 or 151 pieces of 3072 kbps data are put in one frame, and in the case of synchronous data, the number of frames to be put in 151 pieces may be set to 14 pieces. .

 Table 1 shows an example of a frame configuration according to the present invention.

In the example of Table 1, the synchronization bit of the multi-frame is set to 1
Bits, 3 bits for frame synchronization, 1 bit for stuff bits, and 9 bits for error correction code, any combination is possible as long as the total is 14 bits as described above. It is.

Hereinafter, the first invention of the PCM transmission apparatus will be described in the first section.
This will be described with reference to the drawings.

In FIG. 1, 101 is a first selector, 102 is a frame counter, 103 is a multi-frame counter, 104
Is a voltage controlled oscillator, 105 is a clock output circuit, 106 is a frequency divider circuit, 107 is a PLL circuit, 108 is a second selector, 109 is a stuff detection circuit, 110 is a buffer memory, and 111 is a frame configuration circuit.

The first selector 101 sets the transmission clock to 3.58 MHz.
Select 3.375MHz. In the frame counter 102,
When the first selector 101 selects 3.58 MHz as the transmission clock, it counts 175 as the number of bits in one frame, and when it selects 3.375 MHz, it counts 165 as the number of bits in one frame. The multi-frame counter 103 comprises 75 multi-frames,
Perform 5 counts.

The second selector 108 selects whether to transmit 3072 kbps data synchronously or asynchronously (stuff synchronization). When synchronous transmission is selected by the second selector 108, the oscillation frequency 3072 kHz of the voltage controlled oscillator 104 needs to be synchronized with the transmission clock. For this purpose, the 3/11 kHz clock output from the multi-frame counter 103 and the 3/11 kHz clock obtained by dividing the 3072 kHz clock from the voltage controlled oscillator 104 by 11264 with the frequency dividing circuit 106 are used. The synchronization is achieved by controlling the voltage-controlled oscillator 104 with the output obtained by comparing the phases in the PLL circuit 107. 3072kHz for sending 3072kdps data for synchronous transmission
Since a clock is required, the clock is output from the clock output circuit 105. Next, in the case of asynchronous transmission, 3072 kHz from outside
z is input to the stuff detection circuit 109, and the number of external 3072 kHz clocks in one frame period is counted. If there are 151 3072 kHz clocks in one frame, a stuff bit is set.

The input data of 3072 kbps enters the buffer memory 110 and is read by the transmission clock. Buffer memory 11
The data of the transmission clock speed read from 0 enters the frame configuration circuit 111. In the frame configuration circuit 111,
When synchronous transmission is selected by the second selector 108, 15 out of 75 frames in one multi-frame
One bit data is inserted, and 150 bits of input data are inserted into the remaining 61 frames. When the second selector 108 selects asynchronous transmission, the number of data to be inserted in one frame is selected from 150 bits and 151 bits based on the output from the stuff detection circuit 109 and inserted. Then, a frame synchronization pattern necessary for transmission and a multi-frame synchronization pattern are added and transmitted.

Next, with regard to the PCM receiving apparatus according to the second invention,
This will be described with reference to the drawings.

In FIG. 2, 201 is a first selector, 202 is a frame counter, 203 is a multi-frame counter, 204
Is a frame decomposition circuit, 205 is a second selector, 206 is a deframe circuit, 207 is a voltage controlled oscillator, 208 is a clock output circuit, 209 is a first frequency divider, 210 is a second frequency divider,
211 is a third selector, 212 is a fourth selector, 213 is a PLL
The circuit 214 is a buffer memory.

The first selector 201 sets the transmission clock to 3.58 MHz.
Specify 3.375MHz. In the frame counter 202,
When the first selector 201 specifies 3.58 MHz as the transmission clock, 175 is counted as the number of bits in one frame, and when 3.375 MHz is commanded, 165 is counted as the number of bits in one frame. Multi-frame
The counter 203 comprises 75 multiframes, so 75
Perform a count. The second selector 205 specifies whether to perform synchronous transmission or asynchronous (stuff-synchronous) transmission in 3072 kbps data transmission.

The data transmitted from the PCM transmission apparatus of the present invention detects the frame synchronization pattern and the multi-frame synchronization pattern in the frame decomposition circuit 204, and resets the frame counter 202 and the multi-frame counter 203 with the synchronization pattern. Decomposes the transmitted frame.

In the deframe circuit 206, from the frames decomposed by the frame decomposing circuit 204, if the second selector 205 specifies synchronous transmission, 151-bit data from 14 out of 75 frames in one multi-frame and the remaining 61 150-bit data is extracted from the frame. When the second selector 205 specifies asynchronous transmission, the stuff bit indicating the stuff processing in the transmission data is checked.
If "1", the number of data to be extracted is 151 bits, and if "0", it is 150 bits.

Next, the clock system outputs the output 307 of the voltage controlled oscillator 207 when the second selector 205 specifies synchronous transmission.
The third selector 211 selects 3/11 kHz obtained by dividing the frequency of 2 kHz by 11264 with the first frequency dividing circuit 209. Also,
In the fourth selector 212, the multi-frame frequency (3 / 11k
Hz). At this time, in the PLL circuit 213, the 3/11 kHz clock output from the multi-frame counter 203 and the 3072 kHz clock from the voltage controlled oscillator 207 are divided by the first frequency dividing circuit 209 into 11264 to obtain. 3 / 11kHz
By controlling the voltage-controlled oscillator 207 with the output obtained by comparing the phase of the
Synchronize clocks.

When the second selector 205 is instructing asynchronous transmission, the output 3072 kHz clock of the voltage controlled oscillator 207 is checked by the second frequency divider 210 by the stuff bit detected by the deframe circuit 206. If it is “1”, the output of the voltage controlled oscillator 207 is divided by 151, and if it is “0”, the output whose frequency is divided by 150 is selected by the third selector 211. The fourth selector 212 selects a frame frequency. At this time, the PLL circuit
At 213, the frame frequency output from the frame counter 202 is compared with the clock obtained by dividing the 3072 kHz clock from the voltage controlled oscillator 207 by 150 or 151 by the second frequency dividing circuit 209. By controlling the voltage-controlled oscillator 207 with the output obtained by
Synchronize the 072kHz clock. In both cases of asynchronous transmission and synchronous transmission, the clock output circuit 208 outputs a clock of 3072 kHz to the outside. The data extracted by the deframe circuit 206 is obtained by converting the data input by the transmission clock to 3072 kHz.
3072kb through buffer memory 214 to read in z
Output as ps data.

 Next, examples of the third and fourth inventions will be described.

The present invention is a PCM transmission apparatus and a PCM receiving apparatus according to the first and second inventions by transmitting data as digital audio interface format data of 48 kHz sampling and transmitting data as two systems of 3072 kbps asynchronous data. The transmission is performed by using.

FIG. 3 shows an embodiment of the third invention, wherein 301 is a clock extracting circuit, 302 is a frequency dividing circuit, 303 is a demultiplexer, 30
4 is a first PCM transmission device (first invention), 305 is a second PCM transmission device
It is a transmission device (first invention).

6144kbps obtained by converting the input 48kHz sampling audio data to digital audio interface format (when viewed as an NRZ signal)
Is input to the clock extracting circuit 301 first.
Extract 4kHz clock. The actual configuration of the clock extraction circuit 301 is, for example, a voltage-controlled oscillator with a 6144 kHz output and an edge signal extracted from input data of 6144 kbps. It is obtained by controlling. The 6144 kHz clock obtained in this way is converted to a 3072 kHz clock by the frequency dividing circuit 302.

The 6144 kbps data is divided into two systems of 3072 kbps by the output of the frequency dividing circuit 302 and the output of the clock extracting circuit 301. These two signals are respectively transmitted to the first PCM transmission device 304.
And enters the second PCM transmission device 305. Each PCM transmission device 304,3
At 05, asynchronous transmission is performed with a 3072 kHz clock from the frequency dividing circuit 302. The output of each of the PCM transmission devices 304 and 305 is transmitted, for example, by being multiplexed with a video signal.

FIG. 4 shows an embodiment of the fourth invention, wherein 401 is a first PCM.
A receiving device (second invention), 402 is a second PCM receiving device (second invention), 403 is a clock generation circuit, and 404 is a multiplexer.

Data of two transmission clocks from the digital audio interface format data transmission device according to the third invention is input to a first PCM receiving device 401 and a second PCM receiving device 402. The data of these two systems is asynchronous transmission. First PCM receiving device 401 and second PC
The clock of 3072 kHz obtained from the M receiving device 402 generates a clock of 6144 kHz in the clock generation circuit 403. The clock generation circuit 403 can be realized using, for example, a PLL circuit. The 3072 kbps data output from the first PCM receiver 401 and the second PCM receiver 402, respectively, are multiplexed by a multiplexer 404 using clocks of 3072 kHz and 6144 kHz, and output in a 6144 kbps digital audio interface format signal. Is played.

As described above, two sets of 3072 kbps asynchronous data are transmitted using two sets of the PCM transmission apparatus and the PCM reception apparatus according to the first and second inventions, so that 48 kHz sampling digital audio interface format data can be obtained. Can be transmitted. Further, with this configuration, by switching the mode and input of each PCM transmission device, two channels of 3072 kbps data (the arbitrary combination of synchronous / asynchronous is possible) with the same configuration and 6144
It is possible to deal with four types of asynchronous data in the digital audio interface format of kbps.

Effects of the Invention As described above, according to the PCM transmission apparatus of the first invention, for synchronous input / asynchronous input data of 3072 kbps,
3.58MHz, 3.37MHz video reference clock as transmission clock
Even when 5 MHz is selected, by realizing the frame configuration according to the present invention, the circuit configuration can be shared for the above four combinations, and transmission can be realized in any case with a simple configuration. .

Further, in the PCM receiving apparatus of the second invention, even if the transmission data from the PCM transmission apparatus is synchronous / asynchronous with the 3072 kbps data and the transmission clock, the video reference clock is 3.58 MHz and 3.375 MHz as the transmission clock. In either case, by realizing the frame configuration according to the present invention, the circuit configuration can be largely shared for the above four combinations, and the original 3072 kbps of the received transmission signal can be obtained in any case with a simple configuration. It is possible to reproduce the data.

In the asynchronous transmission according to the present invention, the stuff ratio is 14/75.
And the staff data can be made sufficiently small,
The relative stability of the frequency between the input clock and the transmission clock is
It works even with 7000ppm.

The digital audio system according to the third and fourth aspects of the present invention.
The interface format data transmitter or its receiver is a 48 kHz sampling digital
6144kb audio interface format
The ps data is converted into two systems of 3072 kbps data and transmitted, and the transmission is enabled by transmitting and receiving the two sets of the PCM transmission device and the PCM reception device of the first and second inventions. Things. In addition, this configuration allows each PCM
Switch the mode and input of the transmission device and PCM receiving device, and
The same configuration can be used for the transmission of two channels of 072 kbps data (any combination of synchronous and asynchronous is possible) and the transmission of asynchronous data in the digital audio interface format of 6144 kbps. is there.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a PCM transmission device of the first invention, FIG. 2 is a block diagram showing a configuration of a PCM reception device of the second invention, and FIG. 3 is a digital audio device of the third invention. FIG. 4 is a block diagram showing the configuration of an interface format data transmission device, and FIG. 4 is a block diagram showing the configuration of a digital audio interface format data reception device according to the fourth invention. 101,201... First selector, 102,202... Frame counter, 103,203... Multi-frame counter, 10
4,207 voltage-controlled oscillator, 105,208 clock output circuit, 106,302 frequency divider circuit, 107,213 PLL circuit, 10
8,205 ... second selector 109 ... stuff detection circuit
110, 214 ... buffer memory, 111 ... frame configuration circuit, 204 ... frame decomposition circuit, 206 ... deframe circuit, 209 ... first frequency divider circuit, 210 ... second frequency divider circuit,
211... Third selector, 212... Fourth selector, 301
…… Clock extraction circuit, 303 …… Demultiplexer, 304
...... First PCM transmission device, 305 Second PCM transmission device, 4
01: First PCM receiving device, 402: Second PCM receiving device, 403: Clock generation circuit, 404: Multiplexer.

 ──────────────────────────────────────────────────続 き Continuing from the front page (54) [Title of the Invention] PCM transmission device, PCM reception device, digital audio interface format data transmission device, and digital audio interface format data reception device

Claims (4)

(57) [Claims] 1. A first selector for selecting a color subcarrier frequency fsc or a transmission clock of 3.375 MHz, and when the first selector selects fsc, the number of bits in one frame is counted as 175 and 3.375 MHz. Is selected, a frame counter for counting the number of bits 165 in one frame, a multi-frame count for forming 75 multi-frames in the frame, and a voltage control for oscillating a clock that is an integral multiple of 3072 kHz. Type oscillator output 11
A PLL circuit configured to control the voltage-controlled oscillator with an output obtained by transferring and comparing the output divided by 264 and the output of the multi-frame counter, and synchronously transmits 3072 kbps data or asynchronously (Staff Synchronization) A second selector for selecting whether to transmit, a stuff detecting circuit for counting the number of data input during one cycle of the frame counter, and a means for reading out data input at 3072 kHz clock with a transmission clock. The buffer memory provided, and when the second selector selects synchronous transmission, out of 75 multi-frames, 14 frames contain 151-bit data, and the remaining 61 frames contain 150-bit data. When input data is inserted and the second selector selects asynchronous transmission, the number of data to be inserted in one frame is determined by the stuff detection circuit. PCM transmission device comprising a frame configuration circuit to be inserted by selecting 150 bits and 151 bits by the force. 2. A first selector for selecting a color subcarrier frequency fsc or a transmission clock of 3.375 MHz, and when the first selector selects fsc, the number of bits of one frame is counted by 175 and 3.375 MHz. Is selected, a frame counter for counting the number of bits 165 in one frame, a multi-frame count for forming 75 multi-frames in the frame, and a frame for receiving transmission data and decomposing the frame A decomposition circuit, a second selector for specifying whether the received data is transmitted synchronously or asynchronously (stuff-synchronous), and a case where the second selector selects synchronous transmission Of the 75 frames of the multi-frame from the received frame signal, 151 bits of data are 14 frames and 150 bits of the remaining 61 frames are multi-frames. Removed over data, staff said second selector indicating a stuff processing in the transmission data if you select the asynchronous transmission
Looking at the bits, the output of a deframe circuit that selects 151 bits of data to be taken out if there is stuff and 150 bits if there is no stuff, and the output of a voltage-controlled oscillator that oscillates a clock that is an integral multiple of 3072 kHz for 11264 minutes The first frequency dividing circuit which circulates, and the stuff bit detected by the Te frame circuit in the case of asynchronous transmission, the output of the voltage-controlled oscillator is divided by 151 if there is stuff, if there is stuff, there is no stuff In the case of, the second frequency dividing circuit that divides the frequency by 150 and the output of the first frequency dividing circuit when the second selector selects synchronous transmission are selected, and the second selector is asynchronous. A third selector for selecting a second frequency divider circuit output when transmission is selected; and a multi-frame counter output when the second selector selects synchronous transmission, The second select Fourth selecting the frame counter output if but is selected asynchronous transmission
, A PLL circuit configured by controlling the voltage-controlled oscillator with an output obtained by comparing the phases of the outputs of the third and fourth selectors, and data read at 3072 kHz by a transmission clock. PCM receiver comprising: a buffer memory provided in a PCM. 3. A clock extracting circuit for inputting data of 6144 kbps when an NRZ signal obtained by converting audio data of 48 kHz sampling into a digital audio interface format and extracting a 6144 kHz clock; A frequency divider for dividing the output of the clock circuit by 1/2, a demultiplexer for dividing the data of the digital audio interface format of 6144 kbps into two data of 3072 kbps by the output of the frequency divider, and the demultiplexer And a first output for inputting a 3072 kHz clock from the frequency dividing circuit.
And a second PCM transmission device for inputting a second output of the demultiplexer and a clock of 3072 kHz from the frequency dividing circuit, wherein the first and second PCM transmission devices are provided.
A digital audio interface format data transmission device, wherein the transmission device is the PCM transmission device according to claim 1. 4. A first and second PCM receiving apparatus for respectively receiving two systems of transmission data, and a 6144k clock from a 3072 kHz clock obtained from the first and second PCM receiving apparatuses.
A clock generation circuit for generating a clock of 1 Hz;
Output of each of the PCM receiving device and the second PCM receiving device
A multiplexer for multiplexing data of 3072 kbps to reproduce a signal in a digital audio interface format of 6144 kbps, wherein the first and second PCs
A digital audio interface format data receiving device, wherein the M receiving device is the PCM receiving device according to claim 2.