JP2876878B2 - Data transmitter and data receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmitting apparatus and a data receiving apparatus for multiplexing and transmitting a digital audio signal and a digital video signal which are asynchronous with a digital video signal.

[0002]

2. Description of the Related Art In recent years, digital video equipment such as a digital VTR has been actively developed. Along with this, the development of equipment for multiplexing and transmitting video signals and audio signals by digital processing has been activated, and communication signal processing technology has been remarkably developed.

Conventionally, when a video signal and an audio signal are multiplexed by digital processing, transmission is performed such that the sampling frequency of the video signal and the sampling frequency of the audio signal have a relationship that can be expressed by some integer ratio.

A conventional data transmitting apparatus for multiplexing and transmitting a digital video signal of NTSC and a digital audio signal of 48 kHz sampling will be described below.

FIG. 4 is a block diagram showing an example of a conventional data transmission device. In FIG. 4, reference numeral 201 denotes a memory for storing digital voice data;
A write control circuit for controlling the writing of data; 203, a read control circuit for controlling the reading of the memory 201;
Sets the sampling clock of digital video to 1312
A frequency divider that divides the frequency by five, 204 is a PLL circuit that outputs a sampling clock of digital audio and a bit clock for taking in data, 206 is a limiter that limits possible values of input digital video data, and 2
Reference numeral 07 denotes a multiplexing circuit that multiplexes digital video data and digital audio data, adds a communication synchronization signal, and converts the data into a 1-bit serial signal.

[0006] The operation of the data transmission apparatus configured as described above will be described below.

First, a digital video sampling clock of 14.31818 MHz is input from a digital video sampling clock input terminal 211. The frequency divider 205 divides the digital video sampling clock by 13125 and outputs a clock of 1.090909 kHz.

In the PLL circuit 204, a phase frequency comparison is performed based on a clock (1.090909 kHz) output from the frequency divider 205, and a clock of 48.000000 kHz which is an integral multiple of 1.090909 kHz is converted to a digital audio sampling clock. To the output terminal 209,
A 3.0072000 MHz clock is output to the digital audio bit clock output terminal 210. This P
The LL circuit 204 will be described more specifically.

FIG. 5 is a block diagram showing a specific configuration of the PLL circuit 204. 5, reference numeral 301 denotes a reference clock input terminal, 302 denotes a phase frequency comparison circuit, 303
Is a low-pass filter, 304 is a voltage controlled oscillator, 305
Is a frequency divider, 306 is a digital audio sampling clock output terminal, and 307 is a digital audio bit clock output terminal.

In FIG. 5, a clock of about 12.288 MHz is output from the voltage controlled oscillator 304. The frequency divider 305 outputs to the digital audio bit clock output terminal 307 a clock of about 3.072 MHz obtained by dividing the clock of the output of the voltage controlled oscillator 304 by 4, and further obtains a digital audio sampling clock of about 48 kHz obtained by dividing the clock by 64. The clock is output to the clock output terminal 306, and a clock of about 1.09 kHz obtained by dividing the frequency by 44 is output to the phase frequency comparison circuit 302. The phase frequency comparison circuit 302 compares the phase of the clock of 1.090909 kHz input from the reference clock input terminal 301 with the clock of about 1.09 kHz output from the frequency divider 305, and converts the error signal into a low-pass filter. 303
Output to The low-pass filter 303 removes the high-frequency component of the error signal output from the phase frequency comparison circuit 302 and controls the oscillation frequency of the voltage-controlled oscillator 304 so that the error is minimized. In this way, an integer multiple clock of the reference clock is created.

Referring again to FIG. 4, the memory 201 is of a first-in first-out type (hereinafter abbreviated as FIFO) and has a digital audio data input terminal 2.
Data inputted from 08 is sequentially written, and data is read out and output in order from the previously written data.

In the write control circuit 202, the output of the PLL circuit 204 is 48.000000 kHz clock (digital audio sampling clock) and 3.007200 clock.
From the 0 MHz clock (bit clock of digital audio), the memory 2 recognizes the time position where the data exists among the signals input from the digital audio data input terminal 208 and writes the data only during the data period.
01 write control is performed.

Here, digital voice sampling and
FIG. 6 is a timing chart showing an example of the clock, bit clock, and data. (A) is a sampling clock, (b) is a bit clock, and (c) is data, which transmits and receives 48 kHz sampling, 20-bit quantization, and digital audio signals of two channels (Lch, Rch). Bits during one sampling period
The clock has 64 cycles, and 40 time slots out of 64 time slots are used as data.

The limiter 206 applies FF (hexadecimal; hereinafter abbreviated as h) and 00 to the quantized 8-bit data input from the digital video data input terminal 212.
h is prohibited, and the digital video data is output after the code conversion so that the upper limit value is FEh and the lower limit value is 01h.

In the multiplexing circuit 207, as shown in the bit map of FIG. 7, the digital video data output from the limiter 206, the digital audio data output from the memory 201 are packetized, and the communication synchronization signal is multiplexed. 8
The signal is converted into a bit parallel signal, further converted into a 1-bit serial signal, and output to the transmission output terminal 213. The communication synchronizing signal and the audio signal packet are inserted in the horizontal synchronizing period of the video signal, and the communication synchronizing signal is a digital video signal of 9 bits.
Four samples are inserted every ten samples. The multiplexing circuit 207 also outputs a packet timing signal indicating a time position where the audio signal packet is inserted.

The read control circuit 203 controls reading of audio data from the memory 201 based on the digital video sampling clock input from the digital video sampling clock input terminal 211 and the packet timing signal output from the multiplexing circuit 207. ing.

Next, a conventional data receiving apparatus will be described. FIG. 8 is a block diagram showing an example of a conventional data receiving device. In FIG. 8, reference numeral 214 denotes a separation circuit for separating digital video data and digital audio data from a received signal; 215, a memory for storing digital audio data; 216, a write control circuit for controlling writing in the memory 215; A read control circuit for controlling reading of the memory 215; a frequency divider 218 for dividing the digital video sampling clock by 13125;
A PLL circuit 219 outputs a sampling clock and a bit clock of digital audio.

The operation of the data receiving apparatus configured as described above will be described below.

First, in the separation circuit 214, the reception input terminal 2
Synchronization is achieved by detecting a communication synchronizing signal from the 1-bit serial received signal input from 20 to separate digital video data and digital audio data. The digital video data is output to a digital video data output terminal 225. The digital audio data is stored in the memory 215.
In addition, a write timing signal indicating a temporal position where the digital audio data exists is sent to the write control circuit 216.
The digital video sampling clock is connected to the digital video sampling clock output terminal 224,
The data is output to the write control circuit 216 and the frequency divider 218. However, the digital video data during the period in which the communication synchronization signal and the audio signal packet were present are subjected to data replacement so as to be at the level of the horizontal synchronization period.

In the frequency divider 218, the digital video sampling clock output from the separation circuit 214 is frequency-divided by 13125 and output as a clock of 1.090909 kHz.

In the PLL circuit 219, a phase frequency comparison is performed based on a clock (1.090909 kHz) output from the frequency divider 218, and a clock of 48.000000 kHz which is an integral multiple of 1.090909 kHz is converted to a digital audio sampling clock. To the output terminal 223,
A clock of 3.072000 MHz is output to the digital audio bit clock output terminal 222.

The memory 215 is a FIFO in which digital audio data output from the separation circuit 214 is sequentially written.
The data is read out in order from the previously written data and output to the digital audio data output terminal 221.

In the write control circuit 216, the separation circuit 2
The writing control of the memory 215 is performed by the digital video sampling clock of 14 outputs and the writing timing signal.

The read control circuit 217 controls the reading of the memory 215 so that data is output at the timing shown in FIG. 6 from the sampling clock of the digital audio output from the PLL circuit 219 and the bit clock of the digital audio. .

[0025]

However, in the above-mentioned conventional configuration, a bit clock and a sampling clock for digital audio are output from the data transmission device, and therefore, are asynchronous with other video signals. There is a problem that a digital connection cannot be directly obtained from a digital audio signal source (for example, DAT).

The present invention solves the above-mentioned conventional problems. In this invention, a bit clock and a sampling clock for digital audio are externally supplied to a data transmitting apparatus, and a digital clock which is not synchronized with a digital video signal is provided. An object of the present invention is to provide a data transmitting device and a data receiving device that can multiplex and transmit an audio signal and a digital video signal.

[0027]

In order to achieve the above object, a data transmitting apparatus according to the present invention comprises a digital audio sampling clock for digital video sampling.
An asynchronous sampling circuit for outputting a digital audio sampling clock signal (hereinafter, referred to as a digital audio sampling signal) that changes at the sampling timing of a digital video captured at a clock timing;
A read control circuit for reading data from a memory by a digital video sampling clock and a digital audio sampling signal output from an asynchronous sampling circuit;
A multiplexing circuit for multiplexing the digital audio data output from the memory, the digital audio sampling signal, and the digital video data for transmission.

Also, the data receiving apparatus of the present invention separates digital video data, digital audio data, and digital audio sampling signal from the received signal, and outputs the separated signal. A write control circuit for controlling writing of data in the memory by a sampling clock; a frequency divider for dividing the digital audio sampling signal output from the separation circuit by n (n is an integer of 1 or more) to output a divided clock; Circuit for outputting a digital audio bit clock and a sampling clock from a frequency-divided clock of a device output, and read control for controlling reading of digital audio data by the digital audio sampling clock and the bit clock of the PLL circuit output Composed of circuits That.

[0029]

According to the present invention, since a signal obtained by asynchronously sampling a digital audio sampling clock by a digital video signal sampling clock is transmitted by the above-described configuration, information on the digital audio sampling frequency is also transmitted. Therefore, since the sampling clock and the bit clock of the digital audio signal can be reproduced by the data receiving device, the digital video signal and the digital audio signal can be transmitted even when they are completely asynchronous.

[0030]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a data transmitting apparatus according to the first embodiment of the present invention. In FIG. 1, 101 is a memory for storing digital audio data, 102 is a memory write control circuit, 103 is a memory read control circuit, and 104 is a digital audio sampling clock for digital video sampling.
Asynchronous sampling circuit for performing asynchronous sampling with a clock; 105, a limiter for limiting possible values of input digital video data; 106, digital video data, digital audio signal data; output signals of the asynchronous sampling circuit 104; This is a multiplexing circuit that multiplexes a synchronization signal and converts it into a 1-bit serial signal.

The operation of the data transmission apparatus of the present embodiment configured as described above will be described below.

First, the digital audio data input terminal 10
The digital voice data input from 7 is sequentially written into the memory 101. The memory 101 is a FIFO, and data is read out in order from the previously written data to output digital audio data.

In the write control circuit 102, the digital audio bit clock (3.072000M) input from the digital audio bit clock input terminal 109 is input.
Hz) and the digital audio sampling clock (48.000000 kHz) input from the digital audio sampling clock input terminal 110, the time position where data exists in the signal input from the digital audio data input terminal 107 is recognized. Then, the writing control of the memory 101 is performed so that writing is performed only during a period in which data exists. The digital audio signal is input at the timing shown in FIG. 6, and 40-bit data is written in one sampling period of the digital audio.

In the asynchronous sampling circuit 104, the digital audio sampling clock input from the digital audio sampling clock input terminal 110 is
Digital video sampling clock input terminal 111
The digital video sampling clock (14.31818 MHz) is input at the rising edge of the digital video sampling clock, and the digital video sampling cycle is set to 1
The signal changes as a unit, that is, a digital audio sampling signal. However, 14.31818 MHz
As a result, the digital audio sampling signal has a maximum waveform distortion of 69.8 ns.
When this is used as a clock, it has a jitter of ± 34.9 ns. More specifically, the asynchronous sampling circuit 104 is constituted by one D flip-flop.

The read control circuit 103 reads out 40 bits using a digital video sampling clock every time the digital audio sampling signal output from the asynchronous sampling circuit 104 rises.

In the limiter 105, FFh and 00h are prohibited for the 8-bit quantized data input from the digital video data input terminal 112, and the upper limit value FE is set.
h and the lower limit value 01h, the code conversion is performed, and the digital video data is output.

In the multiplexing circuit 106, as shown in the bit map of FIG. 2, digital video data output from the limiter 105, digital audio data output from the memory 101, and a digital audio sampling signal output from the asynchronous sampling circuit 104 are output. Multiplexed communication synchronization signal, 10
The signal is converted into a bit parallel signal, converted into a 1-bit serial signal, and output to the transmission output terminal 108. The communication synchronization signal is inserted during the horizontal synchronization period of the video signal, and the communication synchronization signal is inserted every 910 samples of the digital video signal. The read control circuit 1 reads the communication synchronization position signal from the multiplexing circuit 106 so that the digital synchronization data is not read out while the communication synchronization signal is inserted when the digital audio data is read out.
03.

Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a block diagram showing a data receiving apparatus according to a second embodiment of the present invention. In FIG. 3, reference numeral 113 denotes a separation circuit for separating digital video data, digital audio data, and digital audio sampling signals from a received signal; 114, a memory for storing digital audio data;
A write control circuit for controlling writing of data; 116, a read control circuit for controlling reading of the memory 114;
Reference numeral 7 denotes a frequency divider that divides the digital audio sampling signal by 64, and reference numeral 118 denotes a PLL circuit that outputs a digital audio sampling clock and a bit clock.

The operation of the data receiving apparatus of the present embodiment configured as described above will be described below.

First, a 1-bit serial reception signal input from the reception input terminal 119 is separated by a separation circuit 113 into digital video data, digital audio data, and a digital audio sampling signal. To the video data output terminal 124,
The digital audio data is stored in the memory 114, the digital audio sampling signal is transmitted to the write control circuit 115 and the frequency divider 117, and the digital video sampling clock is transmitted to the digital video sampling clock output terminal 123, the write control circuit 115 and the frequency divider 117. Output to However, the digital video data during the period in which the communication synchronization signal was present is subjected to data replacement so as to be at the level of the horizontal synchronization period.

In the frequency divider 117, a digital audio sampling signal (48.000000k) output from the separation circuit 113 is output.
Hz) is divided by 64 by the digital video sampling clock output from the separation circuit 113 to be 750.00000H.
It is output as the clock of z.

In the PLL circuit 118, a phase frequency comparison is performed with reference to a clock (750.000 Hz) output from the frequency divider 117, and a clock of 48.000000 kHz which is an integral multiple of 750.000 Hz is converted to a digital audio sampling clock. 3.0 is connected to the output terminal 122.
72000MHz clock is used for digital audio bit
It is output to the clock output terminal 121.

The memory 114 is a FIFO in which digital audio data output from the separation circuit 113 is sequentially written.
The data is read out in order from the previously written data and output to the digital audio data output terminal 120.

In the write control circuit 115, the separation circuit 1
The writing control of the memory 114 is performed by 13 digital video sampling clocks and digital audio sampling signals. Each time the digital audio sampling signal rises, 40-bit data is written.

The read control circuit 116 controls the read operation of the memory 114 so that data is output at the timing shown in FIG. 6 from the sampling clock and bit clock of the digital audio output from the PLL circuit 118.

As described above, according to the present embodiment (first and second embodiments), the asynchronous sampling circuit 104 for asynchronously sampling the digital audio sampling clock with the digital video sampling clock to the data transmitting apparatus, By providing a multiplexing circuit 106 for multiplexing a digital audio sampling signal, which is an output signal of the sampling circuit 104, with digital video data and digital audio data, and providing a separating circuit 113 for outputting the digital audio sampling signal to a data receiving device, And a sampling clock for the data transmission can be supplied from the outside to the data transmitting apparatus. That is, even a digital audio signal that is not synchronized with a digital video signal can be transmitted accurately.

The digital audio sampling signal output from the separation circuit 113 has a maximum waveform distortion of 69.8 ns. That is, since the jitter becomes ± 34.9 ns, the clock accuracy for this is ± 1680 ppm.
(± 34.9 × 10 ⁻⁹ × 48 × 10 ³ ≒ ± 1680 × 1
0 ^-6 ). However, even if the frequency is divided by 64 by the divider 117, the waveform distortion of 69.8 ns at the maximum does not change, so that the clock accuracy of 750.000 Hz divided by 64 is ± 26.2.
ppm (± 34.9 × 10 ⁻⁹ × 750 ° ± 26.2 × 1
0 ⁻⁶ ), and the accuracy is improved. Since the sampling clock and the bit clock of the digital audio are generated by the PLL circuit 118 based on the clock of the output of the frequency divider 117, the precision of the clock can be improved by using the frequency divider 117. .

In the second embodiment, the frequency division ratio of the frequency divider 117 is set to 64. However, by further increasing the frequency division ratio, the sampling clock and bit clock of the digital audio signal output from the PLL circuit 118 are increased. Accuracy can be improved.

In this embodiment (first and second embodiments), a digital audio signal of 48 kHz sampling is transmitted. However, only by changing the clock frequency of the PLL circuit 118, 32 kHz sampling or 44.1 kHz sampling digital audio signal is transmitted. It is also possible to transmit audio signals.

Further, the present embodiment (first and second embodiments)
Transmitted 48 kHz sampling, 20-bit quantization, and 2-channel digital audio signals. However, if digital audio data is multiplexed and converted to a serial 1-bit signal, digital audio signals of more channels (for example, 4 channels) are transmitted. Clearly what you can do.

[0052]

As described above, the data transmitting apparatus and the data receiving apparatus of the present invention provide the data transmitting apparatus with a digital audio sampling clock and a digital video sampling clock.
An asynchronous sampling circuit that performs asynchronous sampling with a clock; a digital audio sampling signal that is an output signal of the asynchronous sampling circuit;
By providing a multiplexing circuit for multiplexing with digital audio data and providing a separating circuit for outputting a digital audio sampling signal to a data receiving device, even a digital audio signal that is not synchronized with a digital video signal can be transmitted accurately. Considering that various digital video and audio equipment can be connected, the practical effect is large.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a data transmission device according to a first embodiment of the present invention.

FIG. 2 is a bit map showing bit allocation when data is multiplexed into parallel 10 bits of the data transmitting apparatus according to the first embodiment;

FIG. 3 is a block diagram showing a configuration of a data receiving device according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a data transmission device in a conventional example.

FIG. 5 is a block diagram showing a specific configuration example of a PLL circuit;

6A is a timing diagram of a sampling clock showing an example of a digital audio signal. FIG. 6B is a timing diagram of a bit clock showing an example of a digital audio signal. FIG. 6C is a timing diagram of data showing an example of a digital audio signal.

FIG. 7 is a bit map showing bit allocation when data is multiplexed into parallel 8 bits in a data transmission device in a conventional example.

FIG. 8 is a block diagram showing a configuration of a data receiving apparatus in a conventional example.

[Explanation of symbols]

101, 114 Memory 102, 115 Write control circuit 103, 116 Read control circuit 104 Asynchronous sampling circuit 105 Limiter 106 Multiplexer 113 Separation circuit 117 Divider 118 PLL circuit 108 Transmission output terminal 119 Reception input terminal 107 Digital audio data input terminal 109 Digital audio bit clock input terminal 110 Digital audio sampling clock input terminal 111 Digital video sampling clock input terminal 112 Digital video data input terminal 120 Digital audio data output terminal 121 Digital audio bit clock output terminal 122 Digital audio sampling clock output Terminal 123 Digital video sampling clock output terminal 124 Digital video data output terminal

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04J 3/00-3/26 H04N 7/08

Claims (2)

(57) [Claims] A memory for storing digital voice data; a write control circuit for controlling writing of data in the memory with a bit clock for taking in digital voice data and a digital voice sampling clock; An asynchronous sampling circuit that captures a sampling clock at the timing of a digital video sampling clock and outputs a digital audio sampling clock signal that changes in units of the digital video sampling cycle; a digital video sampling clock and the asynchronous sampling circuit A read control circuit for reading data from the memory according to an output digital audio sampling signal; and a digital audio data output from the memory and an output from the asynchronous sampling circuit. Data transmission apparatus and a multiplex circuit for transmitting the multiplexed data of the digital audio sampling clock signal and the digital image to be changed in the sampling period unit of the digital video. 2. A separation circuit for separating and outputting digital video data, digital audio data, and a digital audio sampling clock signal that changes in units of a digital video sampling period from a received signal, and a digital output of the separation circuit. A memory for storing audio data, a write control circuit for controlling data writing to the memory by a digital audio sampling clock signal and a digital video sampling clock that change in units of a digital video sampling cycle output from the separation circuit; A frequency divider that divides a digital audio sampling clock signal that changes in units of a sampling period of a digital video output from the separation circuit by n (n is an integer of 1 or more) and outputs a divided clock; With respect to the divided clock of A PLL circuit for outputting a sampling clock and the bit clock of the digital audio Te, sampling the digital audio of the PLL circuit output
A data receiving device comprising: a read control circuit that controls reading of digital voice data by a clock and a bit clock.