JP3129866B2 - Aspect ratio converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to broadcasting systems having the same broadcasting standards.
The present invention relates to an aspect ratio conversion device that converts the aspect ratio of video signals having different aspect ratios, that is, horizontal and vertical size ratios of a screen.

[0002]

2. Description of the Related Art Recently, in television receivers (hereinafter referred to as "receivers"), various techniques have been devised for more powerful and realistic imaging. A video screen having an aspect ratio of 16: 9 has already been realized in a video medium such as a high-definition broadcast. However, the broadcast standard is the same as the conventional one, and only the aspect ratio is different.

For example, in the case of an NTSC signal, the number of scanning lines is 525, the horizontal scanning frequency and the vertical scanning frequency are 15.734 KHz and 59.94 Hz (interlace), respectively. 16: 9, which is different from the conventional aspect ratio of 4: 3.

FIG. 11 shows video screens having different aspect ratios, (a) shows a video screen having an aspect ratio of 4: 3,
(B) also shows a 16: 9 video screen. Since the video signal used for this is a conventional NTSC signal, a common signal processing circuit can be used until the image is formed, and only the picture tube is different.

In a receiver compatible with the new aspect ratio of 16: 9, not only the video signal for the aspect ratio of 16: 9 but also the conventional video signal for the aspect ratio of 4: 3 can be displayed without loss of color. And a signal processing circuit. However, a problem occurs when a video signal for an aspect ratio of 16: 9 is received by a receiver that does not support the aspect ratio of 16: 9, which already exists in many markets. In this case, reception is possible because the broadcast standard of the video signal is the same, but an unnatural video that is elongated vertically appears because the aspect ratio is different.

FIGS. 12A and 12B show images of the respective receivers when an image signal for an aspect ratio of 16: 9 is received. FIG. 12A shows an image of a receiver having an aspect ratio of 16: 9, and FIG. Video when received by a receiver with an aspect ratio of 4: 3,
(C) is an image in a wide mode in which the aspect ratio of an image signal is converted so that the entire image screen shown in (a) becomes part of a screen having an aspect ratio of 4: 3, and (d) is (a)
The images in the zoom mode in which the aspect ratio conversion of the image signal is performed so that a part of the image screen shown in FIG.

Next, a description will be given of a conventional aspect ratio conversion apparatus for converting the aspect ratio of the video signal in the wide mode or the aspect ratio of the video signal in the zoom mode. FIG. 13 is a block diagram showing a configuration of an aspect ratio conversion processing system including a conventional aspect ratio conversion device.

In FIG. 13, reference numeral 10 denotes an input video luminance signal (hereinafter, referred to as Yin signal), 11 denotes an input video color signal (hereinafter, referred to as Cin signal), and 3 denotes an aspect ratio conversion process. Aspect ratio conversion device, 30, 3
Reference numeral 1 denotes a converted image luminance signal and image color signal. 4
Numeral 0 denotes an operation controller, which uses the mode changeover switch 43 to set the aspect ratio conversion processing to, for example, the wide mode method shown in FIG. 12C, the zoom mode method shown in FIG.
As shown in (b), it is determined whether to output without conversion.

Reference numerals 51 and 52 denote selections for selecting any set of a Yin signal and a Cin signal or a video luminance signal (Yout signal) 30 and a video color signal (Cout signal) 31 output from the aspect ratio converter 3. The selected signal is an output luminance signal (hereinafter referred to as a Yout signal).
20 and an output color signal (hereinafter referred to as Cout signal) 21 are output. The operation controller 40 is configured to output a control signal 41 for mode instruction to the aspect ratio converter 3 and output an output switching signal 42 to the selectors 51 and 52.

FIG. 14 is a block diagram showing the internal configuration of the aspect ratio converter 3 shown in FIG. 14, the Yin signal 10 is connected to the input port of the control device 300 via the A / D converter 330. Cin signal 11
Are input to a decoder 320 and decoded, become color difference output BY signals 321 and RY signals 322, and are connected to input ports of the control device 300 via A / D converters 331 and 332, respectively.

The control device 3 connected to the memory 310
One output signal from 00 is input to the D / A converter 340 as a luminance signal, and becomes a Yout signal 30. Also,
The BY and RY color difference data output from the control device 300 is D
The signals are input to the A / A converters 341 and 342, and are input to the encoder 350 as BY color difference signals 351 and RY color difference signals 352, respectively, where they are encoded to become the Cout signal 31.

The control signal 41 is input to the control device 300. Also, clock generators 360 and 370
Outputs clock signals 361 and 371, respectively, as a read system clock (hereinafter, referred to as RCLK) 302, and a write system clock (hereinafter, referred to as RCLK) via a clock selector 380 controlled by a clock selection signal 303.
Called WCLK. ) 301 is input to the control device 300.

Next, the operation will be described. First, an operation (wide mode operation) of converting a video signal for an aspect ratio of 16: 9 into a video signal shown in FIG. 12C will be described. FIG. 15 shows that the reduction operation should be performed in the vertical direction. This conversion processing will be described with reference to FIG.

In FIG. 15, reference numeral 1001 denotes an image having an aspect ratio of 16: 9, 1002 denotes a vertical image signal thereof,
Reference numeral 1003 denotes a vertical video signal after reduction conversion;
Is a video image formed into a screen having an aspect ratio of 4: 3 using the video signal 1003. In order to convert the video 1001 having the aspect ratio of 16: 9 into the video 1004 having the aspect ratio of 4: 3, the vertical direction may be reduced to 3/4 if the horizontal direction is left as it is. The vertical start point B _VS and the end point B _VE of the image 1001 correspond to A _VS and A _VE respectively,
The video signal 1003 is obtained by reducing the video area of the video signal 1002 to ／ overall.

[0015] Incidentally, S _V is a vertical synchronization signal, the remaining portion corresponding to this period of 1/4 C _VS ~A _VS, C _VE ~A
Filling is performed with a gray or black fixed pattern as a _VE section, and as a result, an image 1004 is obtained.

Next, the principle of the vertical image reduction will be described in more detail with reference to FIG. FIG. 16 shows the principle state of scanning line thinning in which the number of original scanning lines is reduced to 16 and reduced to 12 scanning lines. If every four original scanning lines are converted into three scanning lines, it can be reduced to ／, and the thinned scanning lines are shown as thinned scanning lines in FIG. In the case where the positions of the thinned scanning lines are located between the original scanning lines, the positions may be obtained by, for example, proportional calculation from the original scanning lines that are positioned vertically above and below.

After the scanning lines are thinned out, the difference from all the scanning lines (the number of all the scanning lines is 16 and the number of the thinning scanning lines is 12, so four lines) is supplemented by two each for the upper and lower sides, and the image is output. As a result, a reduced image is obtained as shown in the lower part of FIG. 16 without changing the total number of scanning lines (that is, without changing the video signal standard). A _l and C _l indicate scanning lines supplemented with black levels or gray levels, and B _l indicates scanning lines obtained by thinning out original scanning lines.

Next, a description will be given of how a video signal for an aspect ratio of 16: 9 is expanded in the horizontal direction and converted into a video signal for display as shown in FIG. 12D (zoom mode operation). FIGS. 17A and 17B are diagrams for explaining the aspect ratio conversion operation of expanding in the horizontal direction. FIG. 17A shows the video signals before and after conversion, and FIG. 17B shows the aspect ratio before conversion.
A region from which a 6: 9 video is extracted is shown, and FIG. 3C shows a video having an aspect ratio of 4: 3 due to the extracted region.

In FIG. 17, 1005 is a video signal for an aspect ratio of 16: 9, and 1006 is an aspect ratio of 4: 3.
A video signal 1007 converted to a video signal 1005 is a video output on a screen having an aspect ratio of 16: 9 by the video signal 1005, 1010
08 denotes an image output on a screen having an aspect ratio of 4: 3 by the image signal 1006.

[0020] In the video signal 1005 and video 1007, an intermediate portion A of the section B _HS .about.B _HE between the horizontal sync signal S _H
HS to A _HE withdrawn, the horizontal sync signal S _H section C _HS between
~ C _HE is extended horizontally to produce a video signal 1006,
An image 1008 is displayed on a screen having an aspect ratio of 4: 3.

The principle of the horizontal extension will be described with reference to FIG. In FIG. 18A, for easy understanding, 2
Although the image is shown to be expanded by a factor of two, in actuality, if the image signal is expanded by a factor of 4/3, a video signal for an aspect ratio of 16: 9 can be converted to a video signal in a zoom mode for an aspect ratio of 4: 3. The video signal 1005, which is the original signal, is
_1, W _2, ..., we sampled at the position of W _9, R _1, R ₂ in a period longer than the sampling period of the resulting sample data at RCLK, ..., video signal by reading out at the position of R ₉ 1006 is obtained.

In FIG. 18A, the frequency of WCLK is set to R
CLK is set to twice, so that a picture expanded twice in the horizontal direction can be obtained. FIG. 18B shows the relationship with the actual video.

Next, the conventional aspect ratio conversion operation will be described in more detail with reference to FIGS. 13 and 14 based on the principle of the above aspect ratio conversion processing. Yin signal 10
Are converted into digital data by the A / D converter 330 and input to the control device 300. The Cin signal 11 is a BY (a difference between the signal of the blue (B) component and the luminance signal Y. The same applies hereinafter) by the decoder 320.
RY (meaning the difference between the signal of the red (R) component and the luminance signal Y. The same shall apply hereinafter.) After being demodulated into a color difference signal 322, control is similarly performed via A / D converters 331 and 332, respectively. Input to the device 300.

The above A / D conversion operation is performed by WCLK 301 which is an input clock to control device 300.
This WCLK 301 is a clock selector 380 controlled by a clock selection signal 303 from the controller 300.
Is input to the control device 300 from one of the clock generators 360 and 370.

The control device 300 writes the Y data and the respective color difference data of BY and RY input as described above into the memory 310, reads out the read data with the RCLK 302, performs a predetermined conversion operation, and converts the Y data into a D / D signal. A converter 3
40, the BY / RY color difference data is converted to a D / A converter 341;
342 respectively. Y data is D / A converter 3
The output of 40 is output as Yout signal 30 as it is,
The BY and RY color difference data are supplied to D / A converters 341 and 342.
, And BY analog signals 351 and 35, respectively.
2 and modulated by encoder 350
It is output as the t signal 31.

The video color signal passes through the decoder 320 and the encoder 350 because the time axis is changed by the aspect ratio conversion operation. Therefore, the signal is once converted into a color difference signal, subjected to a predetermined time axis operation, and then modulated again.

The clock generator 360 oscillates at a frequency 4/3 times the clock frequency of the clock generator 370, and is selected by the clock selector 380 controlled by the clock selection signal 303 from the control device 300. The signal is supplied to the control device 300 as WCLK301. Further, the clock signal 371 from the clock generator 370 is input to the control device 300 as the RCLK 302. Control device 300 performs a conversion operation based on the mode command received by control signal 41.

First, the operation when the wide mode conversion process shown in FIG. 12C is performed will be described in more detail. In this case, since the time operation in the horizontal direction is not performed,
Control device 300 controls clock selector 380 so as to select the clock from clock generator 370 as both WCLK 301 and RCLK 302.

The controller 300 samples each of the Y, RY, and BY data with the WCLK 301 and stores the data in the memory 310 once. Thereafter, the control device 300 reads the data from the memory 310 while reading the data shown in FIG.
The thinning operation for reducing the number of scanning lines shown in FIG. As a result, the control device 300 _obtains A _l and C in FIG.
After adding supplemental scan data corresponding to the thinning scan data corresponding to the B _l of 16 to _l, D at RCLK302 /
The signals are sent to A converters 340, 341 and 342, respectively.
As a result, a Yout signal 30 and a Cout signal 31 are output, and the video signal 1002 shown in FIG.
The operation of converting the aspect ratio to the mode 003 in the wide mode is completed.

Next, the operation for performing the zoom mode conversion processing shown in FIG. 12D will be described in more detail. In the zoom mode conversion processing, the clock generator 36 is used as the WCLK 301 in order to extend the time axis in the horizontal direction.
The clock signal 361 output from 0 is selected by the clock selector 380 and input to the control device 300.
The control device 300 uses the WCLK 301 and the RCLK 302 having a frequency that is three-fourths the frequency of the WCLK 301 as shown in FIG.
A horizontal axis extension operation based on the principle shown in FIG. As a result, a Yout signal 30 and a Cout signal 31 are output, and the video signal 1005 shown in FIG.
6 is completed. Other data flows, operations, and the like are the same as those described above, and thus description thereof is omitted.

FIG. 19 shows a video signal when jitter is mixed and a video screen after aspect ratio conversion in the above operation. In FIG. 19, (a) shows video signals S ₁ , S ₂ , and S ₃ mixed with jitter, respectively, and (b) and (c) show the case where the video signal is horizontally expanded and visualized. 3 shows a video screen showing a deviation from the original image. In FIG. 19 (a), the dashed arrow indicates a sample timing, data for a period of t ₁ ~t ₂ is used as the valid sample data.

It should be noted that the video signal S ₁ shows the case where the interval between the horizontal synchronizing signals is a normal length, S ₂ shows the case where it becomes shorter, and S ₃ shows the case where it becomes longer. The effective sample data is subjected to a horizontal expansion operation in the same manner as the above operation, and is imaged as shown by solid lines in FIGS. 19 (b) and (c).

FIG. 19B shows an image in the case where the jitter frequency is low, and the image is slightly distorted as compared with the original image in the case where there is no jitter indicated by the broken line in the figure. FIG. 19C shows an image when the jitter frequency is high, which is slightly distorted compared to the original image. As can be understood from FIGS. 19B and 19C, the jitter component is emphasized by the horizontal expansion ratio. In addition, regarding the jitter, not only in the case of the above-mentioned horizontal expansion, but in general, when the sampling process is performed,
It tends to be noticeable. For this reason, also during the vertical reduction conversion operation, jitter interference is similarly noticeable, and the image becomes very unsightly.

[0034]

Since the conventional aspect ratio conversion apparatus is configured as described above, for example, when a video signal for an aspect ratio of 16: 9 contains jitter, the image after the aspect ratio conversion is converted. When a jitter component contained in a video signal is amplified and displayed on a screen having, for example, an aspect ratio of 4: 3, there has been a problem that the image becomes very unsightly with the jitter emphasized.

In particular, in a home camera integrated video, 1
In the case of shooting using a 6: 9 conversion lens, jitter tends to occur and tends to increase due to the influence of the temperature of the element and the like due to the downsizing of the device, and the image after the aspect ratio conversion processing during reproduction is likely to occur. There was a problem that the image was very unsightly.

The present invention has been made in order to solve the above-mentioned problems, and has an aspect ratio conversion having a jitter suppressing function and enabling a satisfactory aspect ratio conversion even for a video signal containing jitter. The aim is to obtain a device.

[0037]

According to a first aspect of the present invention, there is provided an aspect ratio converting apparatus for performing an aspect ratio conversion of a video signal, comprising: a horizontal synchronizing signal separating means; N times the frequency and k ₁
n times (where the aspect ratio before conversion is a ₁ : b ₁ and the aspect ratio after conversion is a ₂ : b ₂ , k ₁ = a ₁ b ₂ / (a
Each clock frequency of ₂ b ₁₎ first, second WCLK
, And second PLL means for outputting a clock having a frequency of n times as RCLK, and sampling the input video signal to one of the first and second WCLKs in the aspect conversion mode. And output is performed by RCLK.

According to a second aspect of the present invention, there is provided the aspect ratio conversion device according to the first aspect, wherein the aspect ratio a ₁ : b _{1 is set.}
= 16: 9, a ₂ : b ₂ = 4: 3.

According to a third aspect of the present invention, there is provided the aspect ratio converting apparatus, wherein the first PLL means comprises a third PLL means and first and second frequency dividing means for dividing the output thereof. This is constituted by the second frequency dividing means.

According to a fourth aspect of the present invention, there is provided the aspect ratio conversion apparatus, wherein the aspect ratio conversion apparatus locks the phase of the input video signal to the chrominance subcarrier burst signal.
Fourth PLL means which oscillates at a frequency which is m times the frequency fsc (m is an integer) and also serves as the second PLL means, and A / D conversion which performs a demodulation operation of the color signal with this output clock Means, digital demodulation means, digital modulation means and D / A conversion means.

[0041] The aspect ratio converting apparatus of the present invention according to claim 5, comprising the above-mentioned aspect ratio converting device, fixed to the second PLL unit at n times f _H of television standard frequency of the horizontal synchronizing signal A third frequency dividing means is provided which substitutes an oscillating means and divides the output of the oscillating means and outputs it as a reference signal.

According to a sixth aspect of the present invention, there is provided the aspect ratio converting apparatus, wherein at least one of a horizontal and a vertical synchronizing signal is replaced or added to the synchronizing signal portion after the aspect ratio conversion. A synchronization signal updating means is provided.

[0043]

According to the first aspect of the present invention, the first and the first phase locked to the horizontal synchronizing signal output from the first PLL means.
Since the input video signal is sampled by the selected one of the second WCLK, the number of sampling data within one horizontal synchronization period is always constant, and the output operation is performed by the RCLK output from the second PLL means. Since the average input / output data rate can be kept equal, it is possible to provide an image which can be subjected to favorable aspect ratio conversion without being affected by jitter contained in the input video signal.

According to the second aspect of the present invention, there is provided an operation of the apparatus, wherein the first aspect ratio of the input video signal is set to 1
As 6: 9 or 4: 3, an aspect ratio conversion process that matches existing broadcasting standards such as high definition broadcasting can be realized.

According to the third aspect of the present invention, there is provided an operation of the above-mentioned device, wherein the first PLL means comprises one PLL system and two PLL systems.
Since the frequency divider is constituted by one frequency divider, the PLL system for each WCLK can be shared, and the cost of the entire device can be reduced.

According to the fourth aspect of the present invention, in the operation of the above apparatus, the fourth PLL means locks the phase of the chrominance subcarrier burst signal of the input video signal, and outputs the phase locked signal. The apparatus performs the demodulation operation of the chrominance signal with a clock having a frequency of m times the chrominance signal subcarrier frequency fsc, and uses the second PLL means as the fourth PLL means to use the clock as RCLK. Becomes even cheaper.

According to the fifth aspect of the present invention, there is provided an operation of the above device, wherein the second PLL means oscillates fixedly with a clock having a frequency n times the frequency of the television standard of the horizontal synchronization signal. And the clock is divided by 1 / k ₃ by the third frequency dividing means to be used as a reference signal for matching the input and output data rates, thereby further reducing the cost of the apparatus.

According to the sixth aspect of the present invention, there is provided an operation of the apparatus, wherein a stable horizontal and / or vertical synchronizing signal is replaced or added to a synchronizing signal portion of a video signal after aspect ratio conversion. In particular, even when a video signal having a poor S / N is used, or when used in connection with a receiver having a poor synchronization separation performance, a stable video free from jitter interference can be obtained.

[0049]

[Embodiment 1] FIG. 1 shows the configuration of an aspect ratio conversion apparatus according to an embodiment of the present invention, in which the same or corresponding parts as those of the conventional example are denoted by the same reference numerals as those of FIG. Will be described. 360
a is a clock generator that locks in phase with the separated horizontal synchronization signal and generates a first WCLK 361a, 360b
Are phase locked to the separated horizontal sync signal and the second W
A clock generator for generating CLK 361b, 370a
Is phase locked to the separated horizontal sync signal, and RCLK
A clock generator for generating 302, 500 is a Yin signal 1
The synchronization signal separation device separates and extracts the horizontal synchronization signal 510 from 0, and sends out the extracted horizontal synchronization signal 510 to the clock generators 360a, 360b and 370a.

The clock generator 360a receives the horizontal synchronizing signal 5
The clock generator 360b oscillates at a frequency n times as large as 10 (n is an integer), and the clock generator 360b oscillates at a frequency of 4n / 3 times the horizontal synchronization signal 510. These first and second WCLKs 361a,
361b is input to the clock selector 380 and is selected to become WCLK301. The clock generator 370a oscillates at a frequency n times the horizontal synchronization signal 510, and its RCL
K302 is sent to the control device 300. Each of these clock generators 360a, 360b, and 370a has the configuration shown in FIG.
To output's locked-loop) of the hanging clock.

In FIG. 2, reference numeral 600 denotes a reference input signal (in this embodiment, a separated horizontal synchronizing signal), reference numeral 610 denotes a phase comparator for comparing the phase of an output of a frequency divider 640 described later with the reference input signal 600, Reference numeral 620 denotes a low-pass filter (hereinafter, referred to as LPF) downstream of the phase comparator 610, 630 denotes a voltage-controlled oscillator (hereinafter, referred to as VCO) downstream of the LPF 620, and 640 denotes a clock output 650 of the VCO 630.
Is a frequency divider that divides the frequency and outputs it to the phase comparator 610.

Next, the operation of clock generator 360a will be described with reference to FIG. The VCO 630 oscillates at substantially n times the reference input signal 600 (n is an integer).
The frequency of the clock output 650 of the VCO 630 is divided by 1 / n by the frequency divider 640, and then the phase is compared with the reference input signal 600 by the phase comparator 610. The phase error signal 611 corresponding to the phase error is Output from the comparator 610.

The phase error signal 611 is looped back to the VCO 630 via the LPF 620. Thus, the clock output 650 of the VCO 630 is always a signal accurately oscillated and output at n times the frequency of the reference input signal 600. The clock output 650 corresponds to the first WCLK 361a in this case. When sampling the video signal by a first WCLK361a of the clock output 650, FIG. 3 (a), (b), the period or the like of the horizontal synchronizing signal S _H of the video signal 1005 attempts to change the jitter thereof First WCL according to cycle
Since the cycle of K361a, that is, the sampling cycle changes, (FIG. 3A shows a case where the cycle becomes longer and FIG.
Indicates a case where the length has become shorter. For example, in the case of the same video signal, the relative positional relationship between the sample positions of the same sample is the same, and signal sampling at the same level is possible.

The arrows shown in FIGS. 3A and 3B indicate sampling positions, 1, 2, 3,..., And n indicate the order of sampling in that cycle. The number is just n and constant.

The clock generator 360b operates in the same manner as described above, except that in FIG. 2, the VCO 630 oscillates at a frequency of 4n / 3 times the reference input signal 600.
The frequency divider 640 sets the clock output 650 of the VCO 630 to 3
/ (4n) frequency division. Other operations are the same as those of the clock generator 360a, and a description thereof will be omitted. In this case, the clock output 650 is always the reference input signal 600
When the video signal is sampled using the second WCLK 361b output from the clock generator 360b as a result, the frequency becomes 4n / 3 times that of FIG.
As in (b), the number of samples in the horizontal synchronization period is 4n / 3.

The clock generator 370a operates in the same manner as the clock generator 360a.
The time constant of PF 620 is set to be larger than that of clock generator 360a, and similar clock RCLK 302 is output to control device 300. The horizontal synchronization signal 510 separated by the synchronization signal separation device 500 as the reference input signal 600
(S _H) the clock generator 360a using the first WCLK361a a respective output of the 360b, the second WCLK
361b is the clock selection signal 30 from the control device 300
One of them is selected by the clock selector 380 under the control of No. 3 and input to the control device 300 as WCLK301. The other operations of the control device 300 and the like operate in the same manner as in the conventional example, and a description thereof is omitted.

Next, the reason why the time constant of the LPF 620 differs between the clock generators 360a and 360b and the clock generator 370a will be described. If WCLK does not react sensitively to the jitter of the input video signal, the number of samples during the horizontal synchronization period cannot be made constant. However, if the response speed is too fast because of the feedback system, overshoot and undershoot of control occur, and similarly, the stability of the number of samples is also lacking.

Therefore, clock generators 360a, 360a
In the case of 60b, the time constant of the LPF 620 must be appropriately reduced to some extent. For example, 2 in horizontal scanning line
In order to deal with a jitter having a period corresponding to zero lines, a time constant that is equal to or less than half the period may be set. In this case, since the horizontal scanning cycle is about 15.7 KHz, 15.
A cycle of a frequency of about 7/10 = 1.57 (KHz) is about 0.1.
The time constant should be set to about 637 msec.

On the other hand, since RCLK reacts sensitively to input jitter, a jitter component included in the input video signal is added to the output again. Therefore, it is better to use a fixed clock. However, in order to match the total amount of input / output data, it is necessary to match the total amount of input / output data within a certain period, for example, within several times the vertical scanning period, but this adjustment cannot be performed with a fixed clock.

Therefore, it becomes necessary to control the phase of the output signal with respect to the input video signal in a long period, and this is realized by the PLL system of the clock generator 370a. For example, in order to provide the LPF 620 with a time constant twice as long as the vertical synchronization period, if the vertical synchronization period is 16.67 msec, the time constant may be 23.34 msec. The short-term difference between the input data acquisition rate and the transmission rate with respect to the jitter is smoothed in the long term by temporarily storing and buffering the data in the memory.

As described above, for example, when performing wide mode conversion, the clock selector 380 sets the first WCLK
361a is selected as the WCLK 301. The control device 300 that inputs the first WCLK 361a performs a process of reducing the video signal to 3/4 (scanning line compression ratio) in the vertical direction, thereby removing a jitter component included in the input video signal while widening the image signal. Enable mode conversion.

When performing zoom mode conversion, the clock selector 380 sets the second WCLK 361b to WCL
Select as K301. This second WCLK 361b
The control device 300 that inputs the input video signal performs the video signal processing of the time axis expansion in the horizontal direction by 4/3 times, thereby enabling the zoom mode conversion while removing the jitter component included in the input video signal.

By adopting the device configuration shown in FIG.
When the first WCLK 361a is selected as the LK301 and the control device 300 performs the output operation of the video signal without performing the vertical reduction processing such as the wide mode, the video signal shown in FIG. It is very easy to have a jitter removal function.

In the conventional example, the video after the aspect ratio conversion in the zoom mode is a video in which jitter is hindered as shown in FIGS. 19B and 19C. Even if jitter is included, the image after the aspect ratio conversion in the zoom mode has no jitter interference as shown in FIG. This is because, even if the period of the horizontal synchronizing signal S _H and the video signal of the period fluctuate in jitter, the periods of the WCLK 301 and the RCLK 302 change with each time constant according to the period. In other modes as well, an image free of jitter interference can be obtained in the same manner as described above.

In the prior art, as shown in FIG. 13, selectors 51 and 52 for selecting a system for bypassing the aspect ratio converter 3 are provided. However, in the device of the present embodiment,
In addition to eliminating the need for a switch for bypass, FIG.
It also has a jitter removing function for a normal mode video as shown in FIG. Also in this embodiment, the operation controller 40 and the mode changeover switch 43 are necessary. The same applies to the following embodiments.

Embodiment 2 FIG. FIG. 4 shows a configuration of an aspect ratio conversion apparatus according to Embodiment 2 of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals, and redundant description will be avoided. In FIG. 4, 360c receives the horizontal synchronization signal 510 separated by the synchronization signal separation device 500, and receives the first WCLK 36.
This is a WCLK generator that generates 1a and the second WCLK 361b and outputs them to the clock selector 380. In the first embodiment, two clock generators are used. In the present embodiment, the detailed configuration is shown in FIG. Example 1 is the point of integration as shown.
And different.

In FIG. 5, the same or corresponding parts as those in FIG. 2 of the first embodiment are denoted by the same reference numerals, and the description thereof will not be repeated.
However, the VCO 630 oscillates at a frequency of 4n times the reference input signal 600, and the frequency divider 640 divides the frequency by 1 / (4n). Reference numeral 660 denotes a first frequency divider for dividing the frequency of the output signal of the VCO 630 to 1/4, and 661 denotes a VC
This is a second frequency divider that divides the frequency of the output signal of O630 by ３.

Next, the operation of the WCLK generator 360c shown in FIG. 4 will be described with reference to FIG. 5, but the description of the overlapped portions described in FIG. 2 will be omitted. The VCO 630 is 4n of the frequency of the reference input signal 600 (the frequency f _{H of the} horizontal synchronization signal).
Oscillates at a multiple of the frequency 4 · n · f _H. This VCO 630
Is input to the first and second frequency dividers 660 and 661, is also frequency-divided by the frequency divider 640 at a frequency division ratio of 1 / (4 · n), and is fed back to the phase comparator 610. You.

On the other hand, the first frequency divider 660 divides the frequency of the input signal by １ ／, and sets the frequency of n · f _H to the first frequency.
Is output. Also, the second frequency divider 3
61 divides the frequency of the input signal by １ ／, and
The second WCLK 361b having a frequency of n · f _H / 3 is output.

First and second WCLKs 361a and 361b
Are used as the WCLK 301, and as described with reference to FIG. 2, it is better that the response speed to the input signal is appropriately high, so that the time constant of the LPF 620 can be reduced in common. Therefore, the first and second WCLKs 36
In order to generate 1a and 361b, there is no need to use two PLL systems as in the first embodiment.
The LL system can be commonly used. Therefore, in the present embodiment, compared to the first embodiment, the performance of the WCLK generation circuit is not impaired at all, and the WC is reduced by about half the circuit scale and the number of parts.
An LK generation circuit can be realized, and a large cost reduction can be realized.

Other operations of the apparatus shown in FIG.
Since it is the same as above, its duplicate explanation is avoided.

Embodiment 3 FIG. FIG. 6 shows a configuration of an aspect ratio conversion apparatus according to Embodiment 3 of the present invention. The same or corresponding parts as those in FIG. 4 are denoted by the same reference numerals, and redundant description will be avoided. In FIG. 6, reference numeral 700 denotes a 4f clock that generates a four-times frequency 4fsc which is phase-locked to a burst signal of the chrominance signal subcarrier frequency fsc ≒ 3.58 MHz of the Cin signal 11.
The output signal of the sc oscillator is sent to the controller 300 by RCLK.
It is supplied as 302 and output to a color signal processing device 710 described later.

Reference numeral 710 denotes a color signal processing device connected to the control signal lines 711 and 713, and 720 denotes a Cin signal 11
730 is a digital demodulator for demodulating the digital color difference data from the A / D converter 720 and inputting it to the control device 300.
Reference numeral 0 denotes a digital modulator that modulates digital color difference data output from the control device 300 and converts it again into a carrier color signal. Reference numeral 750 denotes a D / A converter that converts the output signal of the digital modulator 740 into an analog signal. . The color signal processing device 710 is connected to each control input terminal of the A / D converter 720 and the digital demodulator 730 via a signal line 711, and is connected to the digital modulator 740 via a signal line 713. It is connected to each control input terminal of the A converter 750.

FIG. 7 shows signal waveforms and the like of the apparatus shown in FIG. 6, and shows, in order from the top, an input waveform, a demodulated signal waveform, RY data sample timing, and BY data sample timing.

Next, the operation of the third embodiment will be described with reference to FIGS. The Cin signal, which is a carrier color signal of the NTSC television signal, is a signal obtained by modulating both of the color difference signals RY and BY by the following equation. Cin = RY × cos (2πfsc · t) + BY × sin (2πfsc · t) As shown in FIG. 7, the input waveform is Cin, which is a composite value of the color difference signals represented by the respective functions of cos and sin.

When the Cin signal is sampled by a clock having a frequency of 4 fsc, data at each of the points a to h is obtained. Of the obtained sampling data, a,
It can be understood that points c, e, and g are data relating to the color difference signal RY, and points b, d, f, and h are data relating to the color difference signal BY.

Further, as shown in the sample timing of the RY data shown in FIG. 7, for example, when sign inversion is performed when obtaining data on the RY at points c and g in the obtained data, A, C, E,
A G signal can be obtained. Similarly, B, D, F, and H can be obtained as BY demodulated data. Therefore,
Each color difference demodulated data can be obtained from the Cin signal.

The color signal processing device 710 uses a clock having a frequency of 4 fsc obtained from the 4 fsc oscillator 700 to generate C
The A / D converter 740 controls the in signal to be sampled, and the digital demodulator 720 performs conversion by calculating at the clock timing of the frequency of 4 fsc described above with reference to FIG. Through. The control device 300 performs the aspect ratio conversion on the color difference demodulated data obtained as described above, and the process is the same as that described in the first and second embodiments.

The control device 300 converts the color difference data after the aspect ratio conversion once stored in the memory 310 into 4f data.
RCLK having a frequency of 4 fsc obtained from the sc oscillator 700
The signal is read out using the signal 302 and output to the digital modulator 740. The color signal processing device 710 includes a 4 fsc oscillator 70
The color difference data is calculated and modulated by the digital modulator 740 at the timing of the clock with the clock having the frequency of 4 fsc obtained from 0 and converted into a digital carrier color signal. It is converted into an analog carrier color signal and output as a Cout signal 31.

The conversion from the chrominance data after the aspect ratio conversion into the carrier color signal as described above can be realized by performing the operation completely opposite to the demodulation operation described above with reference to FIG. That is, the controller 300 sends the digital modulator 74
0, RY color difference data and BY color difference data alternately,
Moreover, when the signal is sent to the D / A converter 750 while changing the code sequentially and output with a clock having a frequency of 4 fsc, the signal can be modulated again to the carrier color signal.

Specifically, when the RY color difference data is represented by RY and the BY color difference data is represented by BY, the data is arranged in the digital modulator 740 in the order of RY → BY → −RY → −BY → RY →. Change the output. Since the above-mentioned demodulation operation is only the rearrangement of the data order and the code conversion, it can be realized with very simple hardware.

Next, the clock having a frequency of 4 fsc is RCL
The reason for being usable as K302 will be described. Between the horizontal synchronizing signal frequency f _H and a color signal subcarrier frequency fsc, in the NTSC system, fsc = 455f _H / 2 relational expression is satisfied. Since this oscillation frequency fsc is required to have a very high oscillation frequency (3595745 ± 10 Hz in the standard), it has sufficient stability as RCLK and RCL
K can be used.

In a normal VTR reproduction system, the frequency f _H
The tape drive system and the rotary head control system, which are the references for the reproduction of the horizontal synchronization signal, are highly stable fsc used for color signal processing.
The phase is controlled using a clock having a frequency fsc obtained from an oscillator. For this reason, since the frequency f _H of the reproduced horizontal synchronizing signal and the frequency f sc of the carrier color signal are completely phase-controlled for a long period of time, the write data rate and the read data rate described in the first embodiment are equal. Therefore, no problem occurs as a conversion operation. At this time, the first WCLK 361a has a frequency of 910 times (455 × 4/2 times) the frequency of the input horizontal synchronization signal, and the second WCLK 361b has a frequency of 4 × 910/3.
Set to twice the frequency.

As described above, it is possible to realize an aspect ratio conversion device which is not affected by jitter even by the configuration and operation, and a jitter removal device which can remove jitter even when the aspect ratio conversion operation is not performed. Moreover, in this embodiment, the number of A / D and D / A converters can be reduced as compared with the first and second embodiments, and a dedicated color signal demodulator, modulator, RCL
K oscillator is 4fsc oscillator 700, color signal processor 7
Since the data converter 10 is replaced with a data converter having three simple configurations of the digital demodulator 730 and the digital modulator 740, an extremely inexpensive aspect ratio converter can be realized.

Embodiment 4 FIG. FIG. 8 is a block diagram showing a configuration of a circuit that can be replaced with clock generator 370a shown in FIG. In FIG. 8, reference numeral 370b denotes an ordinary crystal oscillator which outputs an RCLK 302 having a frequency of 4 fsc.
An fsc fixed oscillator 800 is a frequency divider for dividing RCLK output from the 4fsc fixed oscillator 370b to 1/2388875, and 810 is an output signal of the frequency divider 800.

The RCLK 302 output from the 4fsc fixed oscillator 370b is input to the control device 300 and
It is used as CLK. However, in this case, as described above, there is a possibility that the write data rate and the read data rate of the aspect ratio conversion device are different due to the fixed oscillation. Therefore, in order to prevent this, the frequency divider 800
Is obtained by dividing the clock frequency of 4 fsc output from the 4 fsc fixed oscillator 370 b by 1/2388875, and using the divided output signal 810 having a frequency equivalent to the frequency of the vertical synchronization signal as a reference signal of the vertical synchronization signal. Yin signal 1
The 0, Cin signal 11 is sent to an input video signal source device (not shown) for input to the aspect ratio conversion device.

Normally, a VTR has a servo mode in which the phase is locked to an external vertical synchronizing signal to perform a reproducing operation. Utilizing the function, VT as an example of an input video signal source device
If R performs reproduction control with reference to the output signal 810 of the frequency divider 800 as an external vertical synchronization signal, the problem of the data rate in the aspect ratio converter can be solved. In particular, when an aspect ratio conversion device is built in a VTR or the like,
Not only the problem of the data rate can be solved very easily, but also a simple fixed oscillator is required for the oscillator for generating RCLK, so that a very inexpensive aspect ratio converter can be realized.

Embodiment 5 FIG. FIG. 9 is a diagram showing a configuration of a luminance signal output unit of an aspect ratio conversion apparatus according to Embodiment 5 of the present invention. The configuration and operation of other color signal processing are the same as those of the above-described embodiment. FIG. 10 is a signal waveform diagram for explaining a main part of the operation of the fifth embodiment of the present invention.

Reference numeral 300 denotes the aforementioned control device, 340 denotes a D / A converter connected to the output port of the control device 300,
0 is a switch which is switched by a control signal 910 from the control device 300, 920 is a fixed voltage level generator that outputs a fixed voltage, and 921 is an output line of the fixed voltage level generator 920. The switch 900 has two stator terminals connected to the output terminal of the D / A converter 340 and the output line 921, respectively.

Next, the main part of the operation of the fifth embodiment will be described with reference to FIGS. If a signal recorded on a tape or a signal recorded on a tape with a large number of reproductions is reproduced by a VTR by repeating dubbing, the reproduced signal has a poor S / N.

When the reproduced signal having a poor S / N is input to the aspect ratio conversion device, the horizontal synchronizing signal particularly becomes as shown in FIG. 10 (a). FIG.
In (a), p indicates the waveform rounding at the edge of the horizontal synchronization signal, and q indicates noise mixed into the horizontal synchronization signal. Even if the video signal in this state is output after being converted in aspect ratio, a synchronizing failure occurs in an image output device (image receiving device) that receives and outputs the output signal, and jitters appear in the output video. . Even if jitter removal as described above in the above embodiment is performed, when an image output device having poor synchronization separation capability of an image output device, particularly an image output device having poor noise immunity performance, is used, the jitter removal effect is reduced. I can't hope.

Therefore, in this embodiment, as shown in FIG. 10B (ts is a horizontal synchronizing signal period, tv is a video signal period), the horizontal synchronizing signal is eliminated by the switch 900 without noise, and Is replaced with a sharp horizontal synchronizing signal, an image free of jitter can be obtained regardless of the capability of the image output device.

Next, the operation of replacing the horizontal synchronizing signal will be described. The control device 300 controls the horizontal synchronization signal period t
The control signal 910 of “H” level shown in FIG. As a result, the switch 900 selects the fixed voltage (equivalent to the horizontal sync signal sync tip level) set in the fixed voltage level generator 920. During the period when the control signal 910 is at the “L” level, the switch 900 outputs the output 340 a of the D / A converter 340.
Select Thus, the signal selected by the switch 900 becomes the signal shown in FIG.
Output as 0.

As described above, when outputting an image signal having a poor S / N by converting the aspect ratio, an image can be output with a more stable image signal. Further, according to the present embodiment, it is not necessary to store the horizontal synchronization signal portion in the input video signal in the memory 310 in order to replace and operate the horizontal synchronization signal, so that the memory capacity can be reduced,
Since only inexpensive components such as the switch 900 and a fixed voltage level generator 920 composed of, for example, a volume are added, the entire aspect ratio conversion device can be realized at lower cost.

Embodiment 6 FIG. In Example 3 shown in FIG.
Although a clock having a frequency of fsc is used for RCLK or the like, the present invention is not limited to this frequency. Even if a clock having a frequency that is an integral multiple of the chrominance signal subcarrier frequency fsc is used as RCLK or the like, the same effect as in the third embodiment can be obtained. Needless to say, this occurs. Of course, also in this case, the frequency of WCLK is set to RCL
Needless to say, it is set corresponding to that of K.

Embodiment 7 FIG. In Example 4 shown in FIG.
A signal having the same frequency as the vertical synchronization signal obtained by dividing RCLK is used as a reference as an external vertical synchronization signal. However, the present invention is not limited to this. Even when a signal having the same frequency as the frequency of the synchronization signal is used, the same effect as that of the fourth embodiment can be obtained. When this aspect ratio conversion device is incorporated in a VTR or the like, a signal of the color subcarrier frequency fsc used in color signal processing can be used as a reference vertical synchronization signal.

Embodiment 8 FIG. Example 5 shown in FIGS. 9 and 10
In the above, the replacement of the horizontal synchronization signal was performed, but the replacement operation of the horizontal synchronization signal was performed including, for example, the front porch portion and the back porch portion other than the video signal portion (the period of tv in FIG. 10B). Has the same effect. However,
In the case of this embodiment, a circuit for generating the level of the porch and a switch terminal for switching to this level are required.

Also, by replacing the burst signal portion with the color signal, the stability of the color signal can be improved in the case of a color signal having a poor S / N ratio, as in the case of replacing the horizontal synchronizing signal. It goes without saying that the above-mentioned effect is achieved. The operation of replacing the horizontal synchronizing signal is D / A
The operation is not limited to after the conversion, and the operation of replacing the horizontal synchronization signal with digital data is also possible.
It may be performed between converters. It is of course possible to incorporate this operation function into the control device.

Further, the operation of replacing the synchronizing signal is not limited to only the horizontal synchronizing signal, and the same effect as in the above embodiment can be obtained even when applied to the vertical synchronizing signal.

[0100]

According to the first aspect of the present invention, the first and second WCLKs and RCLKs are phase-locked to the horizontal synchronization signal and output, and the selected one of the first and second WCLKs and the RC are selected.
Since the aspect ratio conversion processing is performed by using the LK, a video signal having a good aspect ratio conversion processing can be obtained even with respect to a video signal containing jitter, and an image without jitter can be realized. Even when the conversion is not performed, it can be used as a jitter removing device.

According to the second aspect of the present invention, by setting the aspect ratio of the input video signal to 16: 9 or 4: 3, the aspect ratio conversion processing conforming to the existing broadcasting standard such as high definition broadcasting can be performed. And can be easily applied.

According to the third aspect of the present invention, the first WC
Since the respective PLL systems for LK and the second WCLK are configured to be shared by one PLL system, the cost of the entire device can be reduced.

According to the fourth aspect of the present invention, a clock having a frequency which is m times as high as the frequency fsc is generated by phase-locking the chrominance signal subcarrier burst signal of the input video signal. Since the modulation operation is performed and the RCLK is also used, an inexpensive device can be realized.

According to the fifth aspect of the present invention, a fixed oscillation clock of n times the television standard value of the horizontal synchronization frequency of the input video signal is used as RCLK, and this clock is divided for data rate matching. Since it is configured to output, a further inexpensive device can be realized.

According to the sixth aspect of the present invention, at least one of the horizontal and vertical synchronizing signals is replaced or added to the synchronizing signal portion after the aspect ratio conversion. , Or when used in connection with a receiver having poor synchronization separation performance, a stable image free from jitter interference can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an aspect ratio conversion device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a clock generator according to Embodiment 1 of the present invention.

FIG. 3 is a diagram for explaining an operation according to the first embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of an aspect ratio conversion device according to a second embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a WCLK generator according to Embodiment 2 of the present invention.

FIG. 6 is a diagram showing a configuration of an aspect ratio conversion device according to a third embodiment of the present invention.

FIG. 7 is an explanatory diagram showing a color signal demodulation operation according to Embodiment 3 of the present invention.

FIG. 8 is a block diagram showing a configuration of an RCLK generating unit as a main part of an aspect ratio conversion apparatus according to Embodiment 4 of the present invention.

FIG. 9 is a diagram showing a configuration of a synchronization signal updating unit as a main part of an aspect ratio conversion apparatus according to Embodiment 5 of the present invention.

FIG. 10 is a signal waveform diagram illustrating an operation principle according to a fifth embodiment of the present invention.

FIG. 11 is a diagram for explaining an aspect ratio of a video signal.

FIG. 12 is a diagram for explaining an aspect ratio conversion operation.

FIG. 13 is a diagram showing an overall configuration of a conventional aspect ratio conversion device.

FIG. 14 is a diagram showing a detailed configuration of a conventional aspect ratio conversion device.

FIG. 15 is a diagram for explaining an aspect ratio conversion operation in a wide mode.

FIG. 16 is a principle explanatory view showing the principle of scanning line reduction in the wide mode.

FIG. 17 is a diagram for explaining an aspect ratio conversion operation in a zoom mode.

FIG. 18 is a principle explanatory diagram for explaining the principle of time axis expansion in the zoom mode.

FIG. 19 is an explanatory diagram showing that the effect of jitter appears when the aspect ratio conversion processing is performed by the conventional device.

[Explanation of symbols]

 10 Yin signal 11 Cin signal 30 Yout signal 31 Cout signal 41 Control signal 300 Control device 330,331,332 A / D converter 340,341,342 D / A converter 360a, 360b, 370a Clock generator 360c WCLK generator 370b 4fsc fixed oscillator 380 Clock selector 500 Synchronous signal separator 660,661 frequency divider 700 4fsc oscillator 710 color signal processor 720 digital demodulator 740 A / D converter 750 D / A converter 800 frequency divider 810 output signal 900 switch 920 fixed voltage level generator

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 5/46 H04N 7/01

Claims (6)

(57) [Claims] 1. A first video signal for a _first aspect ratio (a ₁ : b ₁ ), which is a ratio between a horizontal size and a vertical size of a video screen, is inputted, and a first writing system clock and a second writing system clock are inputted. By selecting any one of the write system clocks, storing the video signal based on the selected write system clock, and reading out the stored video signal based on the read system clock, the first video signal for the first aspect ratio can be obtained. 1 video signal is converted to a _second aspect ratio (a ₂ :
b ₂ ) an aspect ratio conversion device for converting a second video signal into a second video signal; a horizontal synchronization signal separating means for separating and extracting a horizontal synchronization signal from the first video signal; A clock having a frequency n times (n is an integer) the frequency of the horizontal synchronizing signal that follows with a time constant is output as the first write system clock, and the time constant is relatively small with respect to the horizontal synchronizing signal. K ₁ · n times the frequency of the horizontal synchronization signal that follows (k ₁ = a ₁ b ₂ /
First PLL means for outputting a clock having a frequency of (a ₂ b ₁ ) as the second write system clock, and n times the horizontal synchronization signal following the horizontal synchronization signal with a relatively large time constant An aspect ratio conversion device comprising a second PLL means for outputting a clock having a frequency of 1 as the read system clock. 2. The method according to claim 1, wherein the first video signal has a first aspect ratio of 16: 9 or 4: 3, the second video signal has a second aspect ratio of 4: 3, and The horizontal synchronization frequency and the vertical synchronization frequency of the two video signals are equal to each other, the second writing system clock frequency output from the first PLL means is set to 4n / 3 times the horizontal synchronization frequency, and the second writing is performed. 2. The aspect ratio conversion device according to claim 1, wherein the scanning line compression ratio when a system clock is used is 3/4. 3. The third PLL means for oscillating and outputting a clock having a frequency of 4n times the frequency of the horizontal synchronizing signal from the first PLL means, and a clock output from the third PLL means. Divides the clock output from the third PLL unit into 1 / (4k ₂ ) (k ₂ is an integer) and the second frequency divider divides the clock output from the third PLL unit into 1 / (3k ₂ ). The output clock of the first frequency divider is used as the first write system clock, and the output clock of the second frequency divider is used as the second write system clock. The aspect ratio conversion device according to claim 1 or 2, wherein 4. A clock having a frequency of mfsc (where fsc is a color signal subcarrier frequency and m is an integer) is oscillated and output while being phase-locked to a color burst signal of a color signal of the first video signal. Fourth that also serves as PLL means of 2
And the first video signal is sampled by a clock output from the fourth PLL means,
A / D conversion means for converting to digital data, digital demodulation means for performing an operation in accordance with the output clock timing of the fourth PLL means and converting the digital data to color difference data, and converting the color difference data to the fourth PLL
Digital modulation means for performing an operation in accordance with the timing of the output clock of the means and converting it again to second video signal digital data; and converting the second video signal digital data again to an analog color signal of the second video signal D / A
Converting means for setting the frequency of the first write system clock to m × 455/2 times the horizontal synchronization frequency and setting the frequency of the second write system clock to k ₁ × m of the horizontal synchronization frequency
4. The method according to claim 1, wherein the value is x455 / 2 times.
The aspect ratio conversion device according to any one of the above. 5. An oscillator for fixedly oscillating at n times the frequency of a television standard of a horizontal synchronizing signal is provided by the second PLL.
Means, and the output clock of this oscillation means is 1 / k ₃ (k
5. The apparatus according to claim 1, further comprising third frequency dividing means for dividing the frequency into ₃ (an integer) and outputting the divided signal as a reference signal. 6. A synchronization signal updating means for replacing or adding at least one of a horizontal synchronization signal and a vertical synchronization signal to a synchronization signal portion of the read second video signal. The aspect ratio converter according to any one of claims 1 to 5.