JPH06292151A - High vision signal converter - Google Patents

Abstract

PURPOSE:To realize the improvement of performance of a video and audio system and the small sized converter and the low cost by rationalizing the synchronization system of complicated video and audio processing system in a MUSE/NTSC converter. CONSTITUTION:The converter is provided with a MUSE signal processing circuit comprising a MUSE synchronization processing circuit 4 and a scanning line conversion circuit 6, a means 7 converting data rate from the MUSE system into the NTSC system, an NTSC signal processing circuit 8, an NTSC encoder 10, audio processing circuits 18-20, a phase error signal generating means 5 to generate all synchronization clocks required for the video/audio signal processing, a phase error signal generating means 5, a voltage controlled oscillator 16 for generating a master clock, and a clock generating circuit 17. Moreover, the clock generating circuit 17 is made up of a phase data accumulation means for a desired clock frequency, a latch circuit, a phase-amplitude conversion means and a waveform shaping means. The circuit above is applied to the MUSE/NTSC converter to make the performance stable, to make the converter small remarkably and to reduce the cost.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a television signal converter, and more particularly to a synchronous processing system of a signal processor for converting a MUSE video signal into an NTSC video signal.

[0002]

Hi-vision broadcasting is transmitted by satellite waves after being compressed by the MUSE method. Regarding the principle of this MUSE system, the signal processing system, the configuration of the receiving device, etc.
"NHK Technical Research, Vol. 39, No. 2, pp 18-53
"Development of MUSE method", (1987) ", and its characteristics are that the number of scanning lines is 1125 and the aspect ratio of the screen is 16: 9. To receive this, a MUSE decoder or, more simply, a MUSE / NTSC converter for converting a high-definition MUSE signal into a current NTSC signal is required, and the development of these products is currently in progress. Of these, the latter MU
Regarding the method of converting SE signal to NTSC signal,
"Journal of TV Society, VOL.44, NO.6pp705-5-7
12 "Development of MUSE-525 Converter", (19
90) ”.

The signal processing of this MUSE / NTSC converter is roughly divided into the MUSE signal processing section, M
NTS for converting the USE system to the NTSC system in the time axis conversion processing section, for performing the scan line conversion and the aspect conversion processing, and for converting to the NTSC format signal
It is composed of a C system signal processing unit and the like. Aspect ratio 1
Original image of MUSE of 6: 9 and NTS of aspect ratio 4: 3
As a method of displaying on the C display, 1) 16:
Nine images are compressed horizontally and displayed vertically. (Full mode) 2) The 16: 9 landscape image is displayed as it is, and the top and bottom of the screen are blank areas. (Wide mode) 3) 1
The left and right parts of the 6: 9 image are cut off, and the central part is extracted and enlarged. There is (zoom mode).

On the other hand, the audio signal is multiplexed and transmitted as digital data in the vertical blanking period of the video signal. On the receiver side, audio data is extracted from the MUSE signal, time-extended, and PCM demodulated.

[0005]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In the video processing unit of the NTSC converter, as the synchronization clock of the synchronization processing unit, in addition to the master clock generation circuit (usually 32.4 MHz) in the MUSE synchronization processing unit, NT
A read clock generation circuit from the memory for performing SC system data rate conversion is required. Since the reproduction data rate is different in each of these display modes, it is necessary to switch the read clock frequency rate corresponding to these plural kinds of display modes. Therefore, a plurality of PLLs or clock generators are required. Is provided. In addition, a color subcarrier signal (3.58 MHz clock, subcarrier) generation circuit necessary for encoding an NTSC color difference signal into a chroma signal is required. Also, in the audio decoder, M of 16.2 MHz
For the USE signal sampling data, a clock generation PLL is required to obtain a PCM output signal synchronized with the USE signal sampling data.

Since these clocks required for the MUSE / NTSC converter described above require frequency stability with extremely high accuracy, a high-performance PLL is used for the generation circuit thereof.
Using a circuit. Therefore, a large number of PLL circuits including an expensive crystal oscillator are required, which causes problems such as an increase in circuit scale and an increase in cost.

The object of the present invention is to solve the above-mentioned problems, and
Rationalize complex video and audio processing synchronization system in USE / NTSC converter, stabilize performance,
An object of the present invention is to provide a high-definition signal conversion device that enables downsizing and cost reduction.

[0008]

In order to achieve the above object, according to the present invention, there is provided a MUSE signal processing circuit comprising a MUSE synchronous processing circuit and a scanning line conversion circuit, and a MUSE system to NT.
It has means for converting data rate to SC system, NTSC signal processing circuit, NTSC encoder, and audio processing circuit,
In order to generate all the synchronous clocks required for the above-mentioned video / audio signal processing, a phase error signal generating means, a voltage controlled oscillator for generating a master clock, and a clock generating circuit are provided. Further, the clock generating circuit includes a phase data accumulating unit of a desired clock frequency, a latch circuit, and
It is composed of an amplitude converting means and a waveform shaping means.

[0009]

In the MUSE synchronization processing circuit, the phase error signal generating means detects the phase error of the MUSE processing synchronization clock and inputs it to the voltage controlled oscillator to generate a master clock of a predetermined high frequency. In the clock generation circuit, all the synchronous clocks required by the MUSE / NTSC converter are synthesized based on the master clock. That is, in addition to the MUSE processing synchronous clock, the NTSC data rate conversion clock, the chroma modulation subcarrier clock, and the audio output processing clock are all supplied. Since all these clocks are synchronized with the master clock, separate clock generators and PLL circuits are not required, and performance stabilization, circuit miniaturization, and cost reduction can be realized.

[0010]

The present invention will be described in detail below with reference to the drawings. FIG. 1 is a diagram showing an embodiment of a MUSE / NTSC converter to which the present invention is applied. In FIG. 1, 1 is an input terminal for a MUSE signal, 2 is an A / D converter for converting the MUSE signal into a digital signal with a sampling frequency of 16.2 MHz, 3 is a MUSE input processing circuit, and here, de-emphasis processing, ALC (Automatic Level C
ontrol) Perform actions, etc. 4 is a MUSE synchronous processing circuit, 5
Is a phase error signal generation circuit, which is a synchronization processing circuit 4
Built into. In the circuit 5, as will be described later in detail, M
This is for detecting the phase difference of the USE sync signal from the reference position and providing it for the synchronous reproduction of the master clock necessary for signal processing. The synchronization processing circuit 3 creates various clocks and timing signals necessary for signal processing described later, with reference to the clock generated by the clock generation circuit described below and the detected synchronization signal. Reference numeral 6 denotes a scanning line conversion circuit, and here, a vertical filter and an interpolation processing circuit 11 are used.
Convert 25 scan lines to 525.

A data rate conversion circuit 7 converts the MUSE data rate to the NTSC data rate. This typically uses a few megabits of field memory. In the circuit 7, the video data Dw from which the number of scanning lines is converted from the scanning line conversion circuit 6 is
At the same time as writing with the MUSE system data write clock CKw from the MUSE synchronous processing circuit 4, a clock CKn from a clock generation circuit described later is input as an NTSC system data read clock and is read as rate-converted data Dr to the NTSC system. . Reference numeral 8 is an NTSC processing circuit. In the NTSC processing circuit 8, the video signal from the circuit 7 and the luminance (Y) signal and the color difference (RY, B-) are inputted.
Y) Separation into signals, decoding of color-difference signals transmitted line-sequentially TCI (Time-Compressed Integration) according to the MUSE transmission standard, and conversion into video signals so that the projected image has a predetermined aspect display. Processing such as adding blanking is performed. A D / A converter 9 receives the digital luminance signal Y and the color difference signals RY and BY from the NTSC processing circuit 8 and converts them into analog signals. An NTSC encoder 10 outputs a luminance signal Y, a chroma signal C in the NTSC format, or a composite video signal C.Video from the luminance signal and the color difference signal from the D / A converter 9, and terminals 12 and 13 respectively. , 14 are Y signal, C signal,
Output as C.Video signal. Reference numeral 11 denotes a chroma modulation circuit in the encoder 10, which will be described later, but the color difference signal R
-Y and BY are modulated using a clock CKsc from a clock generation circuit described later to generate the chroma signal C.

Next, the configuration of the clock generation system will be described. , 15 are low-pass filters, which smooth the signal from the phase error signal generation circuit 5 described above. 16 is a voltage-controlled oscillator, which receives the signal from the filter 15
For example, it oscillates a signal of 97.2 MHz. Reference numeral 17 denotes a clock generation circuit, which supplies a clock required for the above-described various signal processings based on the oscillation signal from the oscillator 16. That is, the MUSE supplied to the MUSE synchronization processing circuit 4
System master clock CKM, clock CKn supplied to the data rate conversion circuit 7 and NTSC processing circuit 8, subcarrier clock CK supplied to the chroma modulation circuit 11
sc. Further, the audio processing clock CKa is also supplied to the PCM decoder of the audio processing unit described later.

Next, the voice processing section will be described. Reference numeral 18 is a voice demodulation circuit. In the circuit 18, the A / D converter 2
The digital audio signal multiplexed in the vertical blanking period is extracted from the MUSE signal from the above, and the time is extended. 19 is P
This is a CM decoder, which performs error correction, PCM decoding, and predetermined audio output processing of the digital audio signal from the circuit 18. Further, in the decoder 19, as will be described later, the clock CKa from the clock generation circuit 17 described above.
Based on the above, a 4-channel digital audio signal of a predetermined format is output, and at the same time, a bit clock, a timing signal, a system clock and the like necessary for the digital filter processing in the subsequent stage are generated. Reference numeral 20 denotes a D / A converter, which converts the digital audio signal from the decoder 19 into an analog signal and converts the 4-channel audio signal (ch1, ch2, ch1).
ch3, ch4), and the terminals 21 and
Supply to 22, 23, 24.

As described above, the MUSE /
The NTSC converter is characterized in that all the synchronization clocks necessary for video / audio signal processing can be supplied by one oscillator 16 and one clock generation circuit 17. Next, the detailed configuration of the clock generation circuit 17 will be described. FIG. 2 shows an embodiment of the clock generation circuit 17. In the figure, reference numeral 25 is an input terminal of the oscillation clock CKo from the oscillator 16.
Reference numeral 26 is a frequency dividing circuit. The circuit 26 generates the MUSE clock CKM and outputs it to the terminal 27. 28, 3
Reference numerals 3, 40, and 46 are registers for setting a digital data value representing a phase increment value suitable for the output frequency. Reference numerals 29, 34, 41 and 47 are adders, which sequentially add the phase increment value indicated by the digital value from the register to the previously output value. Three
Reference numerals 0, 35, 42 and 48 are latch circuits, and clock C
Each time Ko is input, the phase cumulative data (digital value) from the adder is output. 31, 36, 43, 49
Is a sine wave converter, which calculates an amplitude value corresponding to each phase data from the latch circuit and converts it into a sine wave. The converter is usually constructed by using a ROM (Read Only Memory). 32, 37, 44, and 50 are waveform shaping circuits, which shape the clock from the sine wave converter,
It is converted into a rectangular wave of a predetermined level so that it can be interfaced with digital signal processing in the subsequent stage. The waveform shaping circuit includes a low pass filter, a level converter, a comparator and the like. 38 is a selector, which is a waveform shaping circuit 32,
Two types of NTSC processing system clock C output from 37
Let Kn1 and CKn2 be points a and b of the selector 38, respectively.
Lead to a point, select one of them and lead to terminal 39. These clocks are switched according to two types of screen display modes. That is, as will be described later, the clock CKn1 is used in the full mode display and the clock CKn2 is used in the wide mode display. 45 and 51 are waveform shaping circuits 44 and 51, respectively.
It is a terminal for guiding the clock from 50, and outputs the subcarrier clock CKsc to the terminal 45 and the audio processing clock CKa to the terminal 51.

Next, in the clock generation circuit 17,
The clock generation operation will be described with reference to a specific example of frequency generation. First, the clock frequency required for the MUSE / NTSC converter of the present invention will be briefly described. MUSE
The sampling frequency of the signal is 16.2 MHz, and 32.4 MHz is MUSE as its master clock CKM.
It is supplied to the synchronization processing circuit 4. Therefore, the original oscillation CKo of the oscillator 16 is set to 97.2 MHz, and the frequency dividing circuit 26 performs the 1/3 frequency dividing operation. The NTSC system read clock used in the data rate conversion circuit 7 is the MU described above.
The optimum sampling frequency differs depending on the SE / NTSC converter output display mode. According to the embodiment of the present invention, in order to correctly display the display area and the aspect ratio in the above two kinds of display modes, the number of samples in the full mode should be 898 dots per horizontal scanning. When the frequency of CKn1 is calculated, the horizontal scanning frequency is 31.5 kHz.
It becomes 1.5 kHz = 28.287 MHz. Similarly, the number of samples in the wide mode is preferably 920 dots per horizontal scanning, and the frequency of the sampling clock CKn2 is
920 × 31.5 kHz = 28.98 MHz. Also, as is known, the clock CKsc used in the chroma modulation circuit 11 is 4 at the color subcarrier frequency of 3.58 MHz.
Double frequency is set to 14.318 MHz. Further, since the digital audio processing clock CKa is normally used as a system clock for 8 times oversampling digital filter, which is 384 times the sampling frequency, 384 × 48 kHz = 18.432 MHz.

Various clocks CKn1 and CK described above
Since the method of generating n2, CKsc, and CKa has the same principle, the next one is shown by a broken line portion 52 in FIG.
A method of generating the clock CKsc will be described. Assuming that the phase increment value (integer) stored in the register 40 is Δφ and the frequency resolution is 2 Hz, the desired frequency Fsc
Is expressed by Fsc = 97.2 MHz × Δφ / (2 to the power of X). Here, X may take a minimum value such that Δφ is an integer. Therefore, since Fsc = 14.318 MHz now, Δφ = 12653336235 with X = 33. Therefore, the frequency of the clock CKsc is Fsc =
97.2 MHz × Δφ / (2 to the 33rd power) = 14.318 M
Obtained like Hz. At this time, as shown in FIG. 3, the original clock 97.2 MHz has one cycle of the desired clock.
Since it is divided into 4.318 / 97.2 = 1 / 6.79,
Per phase increment, ie register 4 above
The phase data Δφ given to 0 corresponds to 53 °.
Therefore, the phase information output from the latch circuit 42 of FIG.
Every time the clock is input, it is incremented by 53 °. That is, in FIG. 3, assuming that the initial state is 0 = 0 °, = 53 ° → = 106 ° → = 1 each time a clock is input.
59 ° → = 212 ° → = 265 ° → = 318 ° →
It changes like 0 = 371 ° (11 °). All of these calculations are performed in the state of a digital signal corresponding to the phase amount. Therefore, although the phase shifts slightly for each cycle, if the amplitude value corresponding to the transition of each phase is output as shown in FIG. 3B, the sine wave clock CK of the desired frequency is output.
sc is obtained. The circuit having this sine wave conversion function is the conversion circuit 43. Incidentally register 40, an adder 41, all the output signals from the latch circuit 42, since the maximum value is a digital phase data of 2 ^33, of course their signal transmission paths becomes 33-bit bus. The other clock generation operations are similar to this. For example, in order to generate the NTSC system clock CKn1, Δφ = 1249915020
Then, this value is stored in the register 28, and 97.2 MHz ×
Δφ / 2 ³² = 28.287 MHz is synthesized. In order to generate the clock CKn2, Δφ = 12805365
This value is stored in the register 33 as 46, and 97.2M
Hz × Δφ / 2 ³² = 28.98 MHz is synthesized. To generate the audio processing clock CKa, Δφ = 16289
This value is stored in the register 46 as 06097, and 9
7.2 MHz × Δφ / 2 ³³ = 18.432 MHz is synthesized.

Next, an outline of an embodiment of signal processing based on each clock generated as described above in the MUSE / NTSC converter of the present invention will be described. FIG. 4A is a diagram showing an embodiment of the phase error signal generation circuit 5 for the reproduced clock in FIG. In the figure, 53 is a MUSE signal input terminal from the MUSE input processing circuit 3,
54 and 55 are 2-sample delay circuits, 56 is an adder circuit, 5
7 is a 1/2 multiplier, 58 is a subtractor, 59 is an absolute value signal forming circuit, 60 is a latch circuit, 61 is an input terminal for the horizontal synchronizing signal HD, 62 is a D / A converter, and 63 is a phase error signal. It is an output terminal. Next, the operation will be described. The phase error of the reproduction clock is obtained from the phase error of the horizontal synchronizing signal HD. H
As shown in FIG. 4B, the D waveform is inverted every line and either rises or falls at sample number 6, and this level is 128/256. Therefore, with this point as a reference, the sum of sample numbers 8 and 4 two samples apart before and after is taken by the adder 56, this value is multiplied by 1/2 by the multiplier 57, and then the difference with the sample number 6 is subtracted. Take with container 58. This value is the phase error that is fixed once for each line. Since the polarity of the HD signal is different for each line, the phase error signal has a positive and negative value, and is thus converted to an absolute value by the absolute value forming circuit 59. This signal is output by the latch circuit 60 every time an HD signal arrives, and the D / A
After being converted into an analog signal by the converter 62, the analog signal is output to the terminal 63. The phase error signal is then fed back to the voltage controlled oscillator 16 via the low pass filter 15 to regenerate the synchronous clock CKo.

FIG. 5 shows an embodiment of the data rate conversion circuit 7. In the figure, 64 is a field memory. The video signal data from the scanning line conversion circuit 6 is input from the terminal 65 and written by the write clock from the address counter 70. In this case, the write clock CKm is the terminal 6
7 is input, and after being gated by the AND gate 69 by the signal from the terminal 68, it is input. Although not described in detail, this gate circuit is necessary to perform write control corresponding to the display area because the display area during one horizontal scanning in the screen display mode is different. On the other hand, the NTSC system read clock CK from the clock generation circuit 17
n is input from the terminal 74 to the field memory 64 via the address counter 73, and the read data of the NTSC rate is output to the terminal 66. 71 and 75 are reset input terminals for writing and reading, 72,
Reference numerals 76 are enable signal input terminals for writing and reading, respectively.

FIG. 6A shows an embodiment of the chroma modulation circuit 11. In the figure, reference numeral 77 denotes an input terminal of the subcarrier clock CKsc from the clock generation circuit 17, 78,
79 is the color difference signal B from the NTSC processing circuit 8 respectively.
-Y, RY input terminals. 80 is a subcarrier generation circuit, 92 is a 90 ° phase shifter, 81 and 82 are balanced modulators, 83 is a mixer, 84 is a bandpass filter, and 85
Is a chroma signal output terminal after modulation. The general operation is that the color difference signals BY and RY are the subcarrier generation circuit 8
A subcarrier signal from 0 and a subcarrier signal from the phase shifter 92 having a phase difference of 90 ° with the subcarrier signal are balanced-modulated by the modulators 81 and 82 and combined by the mixer 84 to create a chroma signal. FIG. 6B shows another embodiment of the chroma modulation circuit 11. The difference from the above embodiment is that two types of subcarrier signals having a phase difference of 90 ° are directly supplied from the clock generation circuit 17, and the subcarrier generation circuit 80 and the phase shifter 92 are provided in the modulation circuit 11. do not have. 8
Reference numerals 6 and 87 are input terminals for a subcarrier signal of 3.58 MHz and a signal having a phase difference of 90 ° with the subcarrier signal. FIG. 7 shows an embodiment of the subcarrier clock generation unit 52 in the clock generation circuit 17 in this case. The same functional components as those in the embodiment shown in FIG. 2 are designated by the same symbols.

In the figure, reference numeral 86 is an input terminal for the original clock CKO. Reference numeral 93 denotes a control signal input terminal for generating a 90 ° phase difference signal, and inputs the control signal to the converter 87. It Although 87 is a sine wave conversion circuit, the difference from the conversion circuit 43 of FIG. 2 is that it outputs two types of sine waves having different 90 ° phases. These two types of signals are passed through waveform shaping circuits 88 and 89, respectively, to terminals 90,
Two subcarrier signals with a phase difference of 90 ° are output to 91.

FIG. 8A is a diagram showing an embodiment of the voice processing unit. Components having the same functions as those shown in FIG. 2 are indicated by the same symbols. In the figure, the PCM decoder 19 indicated by the broken line is D
It is composed of a PCM decoder 96, an output processing circuit 97, and a digital filter 98. Reference numerals 93 and 94 denote input terminals for the digital audio data input from the audio demodulation circuit 18 and the synchronous clock, respectively. These data and clock are synchronized with the 16.2 MHz synchronous clock created by the MUSE synchronous processing circuit 4, that is, the MUSE clock CKM generated by the clock generation circuit 17. In the decoder 96, the audio data is subjected to processing such as synchronization signal detection, error correction, and PCM demodulation of differential PCM. In the output processing circuit 97, the audio processing clock CK from the terminal 95
The digital audio signal is converted into a predetermined output format based on a, and the digital filter 9 in the subsequent stage is used.
The channel identification signal LR and the bit clock BCK necessary for the processing in 8 are output. The clock CKa is supplied from the clock generation circuit 17 and is synchronized with the data from the terminals 93 and 94 and the clock. The digital filter 98 performs, for example, 8-fold oversampling filter processing based on the audio data and clock from the circuit 97 and the clock CKa from the terminal 95 that functions as a system clock. The subsequent operation after D / A conversion is as described above. FIG. 8B shows a timing waveform diagram of the signal LR from the output processing circuit, the bit clock BCK, the clock CKa acting as the system clock, and the output audio data. As described above, even in the audio processing system, the clock generation circuit 17 does not have an oscillator or a PLL circuit as its synchronous processing operation.
All the audio synchronization processing can be performed only with the clock CKa directly supplied from.

[0022]

As described above, the present invention can be applied to MUSE /
Stabilization of performance by applying to NTSC converter,
It is effective in greatly reducing the size and cost of the device.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a clock generation circuit that is a component of the present invention.

FIG. 3 is a diagram illustrating a clock generation mechanism that is a component of the present invention.

FIG. 4 is a diagram illustrating a phase error signal generation circuit that is a component of the present invention.

FIG. 5 is a diagram showing an embodiment of a data rate conversion circuit which is a constituent element of the present invention.

FIG. 6 is a diagram showing a chroma modulation circuit that is a component of the present invention.

FIG. 7 is a diagram showing a subcarrier signal generation circuit that is a component of the present invention.

FIG. 8 is a diagram illustrating a voice processing circuit that is a component of the present invention.

[Explanation of symbols]

 4 ... MUSE synchronous processing circuit, 5 ... Phase error signal generation circuit, 6 ... Scan line conversion circuit, 7 ... Data rate conversion circuit, 8 ... NTSC system processing circuit, 10 ... NTSC encoder, 16 ... Voltage controlled oscillator, 17 ... Clock generation circuit, 19 ... PCM decoder.

Claims (5)

[Claims] 1. An apparatus for receiving a high-definition signal, converting it into the number of scanning lines and aspect ratio of a standard television signal, and outputting a standard television video signal, the high-definition synchronization processing means and the synchronization processing means detecting the same. The phase error signal generating means for the synchronizing signal, the scanning line number converting means, the means for converting the high-definition rate signal to the data rate of the standard television signal, and the chroma encoder are included and are converted into the predetermined format video signal of the standard television. An oscillating means for generating a master clock of a predetermined frequency based on the phase error signal from the phase error signal generating means, and an oscillating means. Based on the clock from the above, the clock that generates a plurality of clocks that are necessary for the video and audio processing devices and are synchronized with each other. HDTV signal converting apparatus being characterized in that a click generating means. 2. The apparatus according to claim 1, wherein the clock generation means includes at least a high-definition signal processing synchronous clock, a standard television signal processing synchronous clock, and a subcarrier generation clock in the chroma encoder. , A high-definition signal converter which generates all or a plurality of types of synchronous clocks for audio signal output processing. 3. An apparatus for receiving a high-definition signal, converting it into the number of scanning lines and aspect ratio of a standard television signal, and selectively outputting a plurality of types of standard television image signals having different screen display states, a high-definition synchronization process. Means, a phase error signal generating means for the synchronization signal detected by the synchronization processing means, a scanning line number converting means, a means for converting a high-definition rate signal into a data rate of a standard television signal, and a chroma encoder It has a video processing device consisting of means for converting into a predetermined format video signal of a television and an audio processing device, and based on the phase error signal from the phase error signal generating means, a master clock of a predetermined frequency Based on the generated oscillation means and the clock from the oscillation means, high-definition signals that are at least synchronized with each other And for processing the synchronous clock and the standard television signal processing synchronous clock, and further a clock for the sub-carrier generation in the chroma encoder,
The standard television signal processing synchronous clock provided with clock generating means for generating a synchronous clock for audio signal output processing, and output by the clock generating means,
A high-definition signal conversion device, wherein clocks of a plurality of types of frequencies are generated corresponding to the plurality of screen display modes, and the clocks are switched and supplied according to the display modes. 4. The apparatus according to claim 1, wherein the clock for generating the subcarrier generated by the clock generating means is a first clock having a predetermined subcarrier frequency, and the first clock and the first clock. Second with a phase difference of °
A high-definition signal converter that generates two types of clocks. 5. The apparatus according to claim 1, wherein the clock generation means stores and outputs phase data related to a clock having a desired frequency, and the phase data is generated each time the master clock arrives. , A means for converting the accumulated phase data into a predetermined amplitude signal corresponding to a data value, and a means for shaping the amplitude signal in a plurality of types. Converter.