JP2850964B2 - Picture-in-picture circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a picture-in-picture (Picture-in-Picture) built in video equipment such as a color television receiver (hereinafter, referred to as a television) or a video tape recorder (hereinafter, referred to as a VTR). The present invention relates to a circuit, and more particularly to a picture-in-picture circuit suitable for obtaining two or more types of PIPs having different aspect ratios.

[0002]

2. Description of the Related Art In general, a PIP displays another child image different from the parent image in a part of the parent image, and the synchronization signal between the parent image and the child image is not synchronized. Since the child image size is general and smaller than the parent image size, at least the child screen is written to an image memory such as a field memory or the like by a write clock synchronized with the child screen (write clock is hereinafter referred to as WCK). Is read by a read clock synchronized with the main screen (hereinafter, a read clock is referred to as RCK) and is read out and displayed on the main screen by digital technology.

As a method of controlling the aspect ratio of a small screen, (1) a vertical (hereinafter, vertical is represented by V) size is controlled. (2) The horizontal (hereinafter, horizontal is represented by H) size is controlled. (3) Control both vertical and horizontal sizes. There are three means. A child screen by the NTSC system with an aspect ratio of 4: 3 or an HDTV with an aspect ratio of 16: 9 in the main screen
When a small screen is displayed by the method, it is desirable to change the H size without changing the V size for display quality. The most effective means for changing the H size is to change the frequency of the RCK.

FIG. 2 is a block diagram of a conventional PIP circuit, particularly a general PIP circuit having an aspect ratio switching function.
It is a block diagram of an IP circuit. First, the writing of the small-screen information to the image memory 27 will be described with reference to FIG. A composite video signal (hereinafter, referred to as a child signal) of a small screen is separated into a luminance signal Y and a chroma signal C by a YC separation circuit 22, and the chroma signal C is demodulated into color difference signals BY and RY. . These Y, BY, RY
The signal is input to an image memory 27 through an analog / digital converter (hereinafter, referred to as A / D) 25. The child horizontal synchronization signal SH obtained by the child synchronization separation circuit 24,
The child vertical synchronization signal SV is input to the WCK control circuit 26, and the child screen information is written to the image memory 27 by the WCK synchronized with the child screen.

Next, reading of the small-screen information from the image memory 27 will be described with reference to FIG. The general delay circuit C2 mainly includes an H delay circuit 35 and a V delay circuit 36, and the horizontal synchronization signal (MH) of the main screen and the vertical synchronization signal (MV) of the main screen are displayed at PIP display positions on the main screen. Delay circuit 35 and V delay circuit 3 for controlling
6 is input to the RCK control circuit 38 as the horizontal synchronizing signal MH1 and the vertical synchronizing signal MV1, and the child screen information stored in the image memory 27 is read out by the RCK synchronized with the main screen, that is, the RCKM. The signal is converted into an analog RGB signal via a digital / analog converter (hereinafter, referred to as D / A) 28 and a matrix circuit 29 and mixed with the parent RGB signal by the high-speed switch 30 to become a parent-child composite RGB signal. The switching of the high-speed switch 30 is controlled by a signal from a terminal 66 in FIG. 3, which will be described later.

The main role of the integrated delay circuit C2 shown in FIG. 2 will be described. A display position control signal including an H delay control signal and a V delay control signal is applied to the terminals 33 and 34. Then, in response to the H-delay control signal applied to the terminal 33, the H-delay circuit 35 supplies the original horizontal synchronizing signal M of the parent image.
Then, a synchronization signal MH1 delayed from H is generated and input to the RCK control circuit 38. Similarly, in response to a V delay control signal applied to the terminal 34, the V delay circuit 36 A synchronous signal MV1 delayed from the vertical synchronous signal MV is input to the RCK control circuit 38, and the operation start time of the RCK control circuit 38 is controlled by the display position control applied to the terminals 33 and 34. The main function of the general delay circuit C2 is to arbitrarily change it by a signal.

FIG. 3 is a general block diagram of the RCK control circuit 38. The synchronization signals MH1 and MH1 delayed by the H delay circuit 35 and the V delay circuit 36 shown in FIG.
MV1 is an H delay circuit 53, a V delay circuit 54 shown in FIG.
The H delay circuit 53 outputs a synchronization signal MH2 using the output of the RCK oscillator as a clock, and the V delay circuit 54 outputs a synchronization signal MV2 using the synchronization signal MH2 as a clock. Thus, the synchronization signal MH
1 and MV1 are given respective predetermined delay amounts.

The synchronizing signal MH2 and the output signal MV2 of the V delay circuit 54 are input to a horizontal monostable multivibrator (H-MSM) 55 and a vertical monostable multivibrator (V-MSM) 56, respectively. You. The output signals MH3 and MV3 of the H-MSM 55 and V-MSM 56 are both AND circuits (AND).
Circuit 57, and the output signal is output to a terminal 66, which is a control signal for the switch 60. That is, the signal at the terminal 66 turns on the output signal of the RCK oscillator 59.
/ OFF switch 60 is controlled.
Is output to a terminal 62 and becomes a signal applied to the image memory 27, that is, RCKM. The H delay circuit 53 and the V delay circuit 54 shown in FIG.
The temporal position of V1 is corrected, and the child screen (PI
The position P) is determined, and a fixed-count-value counter is generally used.

The two monostable multivibrators 5
Reference numerals 5 and 56 operate with the synchronization signals MH2 and MV2 as trigger signals, and generate pulses for setting the display width of the PIP in the H and V directions, respectively. The monostable multivibrator 5 using the synchronization signal MH2 as a respective clock.
The widths of the output pulses of 5, 56 are determined, and P
The horizontal display period and the vertical display period of the IP are determined. Therefore, by controlling the frequency of the RCK oscillator 59, that is, controlling the aspect ratio switching signal, the horizontal display period changes. On the other hand, the display period in the vertical direction does not change.

On the other hand, the RCK control circuit 38 performs field discrimination based on the relative phase between the synchronization signal MH1 and the synchronization signal MV1, and reads out a child screen of a field that matches the current field of the parent screen. If the field discrimination is not performed correctly, the nth horizontal line and the (n + 1) th horizontal line of the sub-screen will be upside down, and the image quality will be degraded. When switching the oscillation frequency of the RCK oscillator 59 to switch the H size of the child image and switch the aspect ratio of the child screen, the clock frequency applied to the H delay circuit 53 also changes according to the above principle, The display position also changes.

Therefore, it is necessary to correct the phase of the synchronization signal MH1 by the H delay circuit 35 so that the horizontal position of the PIP screen does not change at any RCK frequency. However, if only the H delay circuit 35 is corrected for position correction here, the field discriminating circuit 58 in the RCK control circuit may malfunction. This will be described later with reference to FIGS.

Also, the H delay circuit 35 and the V delay circuit 36 are positively utilized to place the P at an arbitrary position on the main screen.
Although it is possible to display the IP, the same problem as described above occurs. In order to solve this, H shown in FIG.
The delay circuit 35 and the V delay circuit 36 may be changed simultaneously in the range of 0 to 262H so that the field discriminating circuit 58 in the RCK control circuit 38 does not malfunction. However, according to this method, since two delay circuits are usually constituted by a counter or a memory, a very large counter circuit is required or a large memory capacity is required, and it is very difficult to realize.

FIGS. 4, 5, and 8 show the above-described general P
5 is a time chart for explaining the operation of the IP circuit. FIG. 4 is a diagram for explaining the operation of the field determination circuit 58. For example, when the rising of the vertical synchronizing signal MV1 and the rising of the horizontal synchronizing signal MH1 are substantially equal, the current parent screen is in the first field, and the vertical synchronizing signal MV1 rises near the middle of an arbitrary horizontal synchronizing signal and the next horizontal synchronizing signal. If it has risen, it is determined to be the second field.

FIG. 5 is a diagram for explaining a malfunction of the field discriminating circuit 58. In FIG. 5, since the rising edges of the synchronization signals MH and MV substantially coincide, this field is an odd field, for example, the first field. However, after the synchronization signals MH1,
When the rise of MV1 is compared, according to the principle described with reference to FIG. 4, since the phase relationship is as if it were an even field, for example, the second field, the field determination circuit 58 makes an erroneous determination.

FIG. 7 is a diagram showing an example of a PIP screen, in which a child screen is displayed at the lower right of the parent screen. Regarding the display position and the display period of the child screen, in the vertical direction, the child screen is displayed during the time TV after the time VP has elapsed since the upper end display. In the horizontal direction, the display is performed for a time TH after a time HP has elapsed since the left end display. That is, the hatched portion in FIG. 7 is a small screen in the PIP.

FIG. 8 is a diagram showing the phase relationship between the signals during the PIP operation. The time chart shown in FIG. 8 shows the phase relationship of each signal on the PIP screen shown in FIG. 7, and the child screen is displayed only when the signal MV3
Is at the H level during the time TV and the signal MH3
Is in the period of the time TH at which the level becomes the H level. That is, FIG.
When the logical product output output to the terminal 66 shown in (1) is at the H level, the child screen is displayed.

[0017]

SUMMARY OF THE INVENTION The present invention relates to a sub-screen H
The present invention relates to a PIP system capable of changing a size by changing a frequency of RCK and displaying a child screen at an arbitrary position on a main screen.
When the delay time and the V delay time are arbitrarily set and the child screen is displayed at an arbitrary position on the parent screen, an H delay circuit and a V delay circuit that do not cause deterioration in image quality due to erroneous field determination can be easily provided. It is intended to be realized.

[0018]

The PIP circuit according to the present invention comprises:
Means for writing the signal of the sub-screen to the image memory; and means for reading the sub-screen signal from the image memory in synchronization with the main screen. The reading means comprises a read clock (RCK) oscillation circuit and a main screen of the main screen. A field discriminating circuit for comparing phases of horizontal and vertical synchronizing signals; a horizontal delay circuit and a vertical delay circuit; at least the horizontal delay circuit is a picture-in-picture (PIP) circuit operated by a clock synchronized with the RCK; A means for switching a plurality of RCK frequencies, a first horizontal delay circuit to which at least a main screen horizontal synchronization signal is input, a second horizontal delay circuit to which a main screen vertical synchronization signal is input, A vertical delay circuit to which an output of the second horizontal delay circuit is applied, wherein the first and second horizontal delay circuits are controlled in common and substantially Has one of the delay time, form a maximum value of the delay time to approximately one horizontal period, it is characterized in that an integral multiple of the delay time of one horizontal period of the vertical delay circuit.

[0019]

FIG. 1 is a block diagram of a total delay circuit C1 in a PIP circuit according to the present invention, which is mainly composed of two H delay circuits 1, 2 and one V delay circuit 3. The two H delay circuits 1 and 2 have substantially the same electrical characteristics. The horizontal synchronization signal MH of the main screen is one H
The signal is input to the delay circuit 1 via the terminal 31, and the output signal MH 1 is output to the terminal 6. On the other hand, the vertical synchronization signal MV of the main screen is input to the other H delay circuit 2, the output signal MV0 is input to the V delay circuit 3, and the output signal M
V1 is output to terminal 14. An H delay control signal common to the H delay circuit 1 and the H delay circuit 2 is applied to the terminal 12, and a predetermined delay amount is set. Therefore, the H delay circuit 1 and the H delay circuit 2 have the same delay time, and the control range of this delay time is a maximum of 1H (about 63.5 in the case of the NTSC system).
μs).

In the V delay circuit 3, one horizontal period (1
H) as a unit step and a maximum of 262H (about 525/2)
: In the case of the NTSC system) can be arbitrarily set by the V delay control signal applied to the terminal 13. Accordingly, the H delay circuit 1 and the H delay circuit 2 are delay circuits or memory circuits having the same structure, and a common horizontal synchronization clock CLK1 is applied to the terminals 4 and 8 of the H delay circuits 1 and 2 via the terminal 10. A common H delay control signal is applied to terminals 5 and 7. Also, the V delay circuit 3
This is a delay circuit that can obtain a delay amount of 1H step by the horizontal synchronization clock CLK2 applied from the terminal 11, and can be realized by a delay circuit or a memory circuit like the H delay circuits 1 and 2.

FIG. 6 is a time chart of the PIP circuit of the present invention. Since the rises of the horizontal synchronization signal MH and the vertical synchronization signal MV of the main screen are substantially the same, the current field is an odd field. Output MH of the H delay circuit 1
1. The output MV0 of the H delay circuit 2 is a signal that is delayed by the time T1 with respect to the synchronization signals MH and MV. The synchronization signal MV0 is a signal further delayed by the time T2 by the V delay circuit 3. Since this time T2 is an integral multiple of one horizontal period (1H), the rise of the synchronizing signal MV1 and the rising of the synchronizing signal MH1 substantially coincide, and according to the principle described with reference to FIG. An accurate determination is made that the field of the current screen is an odd field.

The H delay circuit 1 and the H delay circuit 2
Assuming that the clock frequency CLK1 is, for example, 64 times the horizontal frequency fh, each can be constituted by a hexadecimal counter, and the variable minimum step of the delay amount is about 1 μs (63.
5/64), which is a sufficiently fine variable step in the horizontal direction. If the V delay circuit 3 is a 262-base counter operated by the clock of fh, the variable step of the vertical delay amount is 1H unit, and the maximum delay time is Can be 262H.

As described in detail above, the PI of the present invention
The P circuit can achieve its intended purpose with a simple circuit configuration, and is very advantageous in terms of cost. Incidentally, in the total delay circuit C1 shown in FIG. 1, the horizontal synchronizing clock CLK1 and the vertical synchronizing clock CLK2 are
Whether the clocks are common or separate,
There is no problem under the condition that it sufficiently satisfies the horizontal position variable step.

[0024]

According to the PIP circuit of the present invention, when the H-delay time and the V-delay time are arbitrarily set and the child screen is displayed at an arbitrary position on the main screen, the image quality is degraded due to erroneous field discrimination. Therefore, the display position can be easily and accurately corrected when the aspect ratio is corrected by controlling the RCK.

[Brief description of the drawings]

FIG. 1 is a block diagram of a total delay circuit according to the present invention.

FIG. 2 is a block diagram of a conventional PIP circuit.

FIG. 3 is a block diagram of a conventional RCK control circuit.

FIG. 4 is a diagram illustrating the operation of a field determination circuit.

FIG. 5 is a diagram illustrating a malfunction of the field determination circuit.

FIG. 6 is a time chart of each signal in the PIP circuit of the present invention.

FIG. 7 is a diagram illustrating an example of a PIP screen.

FIG. 8 is a diagram illustrating a phase relationship between respective signals during a PIP operation.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 H delay circuit 2 H delay circuit 3 V delay circuit 22 YC separation circuit 23 color demodulation circuit 24 small screen synchronization separation circuit 25 A / D converter 26 WCK control circuit 27 image memory 28 D / A converter 29 matrix circuit 30 high speed Switch 38 RCK control circuit 53 H delay circuit 54 V delay circuit 55 Horizontal monostable multivibrator 56 Vertical monostable multivibrator 57 Integrator 58 Field discriminating circuit 59 RCK oscillator C1 General delay circuit C2 Conventional general delay circuit MH Main screen Horizontal sync signal of MV Vertical sync signal of main screen

Claims (1)

(57) [Claims] 1. A means for writing a signal of a child screen to an image memory, and said child screen signal is written from said image memory to a parent screen.
Read means for reading in synchronization with the horizontal synchronization of the main screen signal
Signal is delayed according to the horizontal display position of the sub screen.
A first horizontal synchronizing signal and a vertical synchronizing signal of the main screen signal
Is delayed according to the vertical display position of the child screen.
Total delay for supplying a vertical synchronization signal to the reading means
And a circuit, the reading means, corresponding to the aspect ratio switching signal circumferential
A read clock (RCK) oscillation circuit which outputs a wave number of the read clock (RCK), the first horizontal synchronizing signal
Signal and the first vertical synchronizing signal.
A field determination circuit for performing field determination;
A horizontal delay circuit for delaying a horizontal synchronization signal;
And a vertical delay circuit for delaying the vertical synchronizing signal, the horizontal delay circuit Oite the picture-in-picture (PIP) circuit that operates by a clock synchronized with the RCK, the overall delay circuit, said main picture signal Supplied to the first water
A first horizontal delay circuit for outputting a flat synchronization signal;
Second horizontal delay circuit to which a vertical synchronization signal of a plane signal is supplied
The output of the second horizontal delay circuit is supplied and the first
And a first vertical delay circuit for outputting a vertical synchronization signal of
For example, a table of the first, second horizontal delay circuits horizontal child screen
Signals that control the indicated position are controlled in common and have approximately the same delay time, and the maximum value of the delay time is set to approximately one horizontal period .
And the first vertical delay circuit displays a sub-screen in a vertical direction.
The delay time is controlled by a position control signal
, And the picture-in-picture circuit, characterized in that the delay time to an integer multiple of one horizontal period.