JPH0121676B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a television receiver (Picture in Picture; hereinafter abbreviated as P in P television) in which a screen of another channel can be inserted into a part of the screen.

In recent years, in order to effectively utilize the cathode ray tubes in television receivers, so-called P in P television has been announced, in which other television programs are displayed in a reduced size on a portion of the original television screen (Nikkei Electronics, 1977). December 26 issue, 127-134
pages, etc.). The concept of P in P is shown in Figure 1 below.
This will be briefly explained with reference to FIG.

Figure 1 is a conceptual diagram of P in P, where 1 is a television receiver, 2 is a cathode ray tube, 3 is a main screen section, and 4 is a sub-screen section into which another TV screen has been reduced and inserted. , the sub-screens are designed so that each channel can be selected independently.

FIG. 2 shows an example of a method for inserting a sub-screen. is the child screen before reduction, and is the parent screen into which the child screen was inserted. If the screen reduction rate is the scan period after reduction/the scan period of the original signal, then if the screen reduction rate of the sub screen is 1/3 vertically and horizontally, then one out of three scanning lines will be divided from the screen of the sub screen. , and after compressing the horizontal period to 1/3 on the time axis and synchronizing with the parent screen, insert it into the parent screen.
Scanning lines ~ show part of the scanning lines before and after reduction.

FIG. 3 shows the state of child screen insertion on a time axis.
is the video signal of the child screen before reduction, and is the video signal of the parent screen into which the child screen has been inserted. As shown in Figure 2, one out of every three scanning lines is extracted from the sub-screen video signal and written to an analog or digital field memory to determine the sub-screen insertion position (thick lined part) of the main screen video signal. A two-screen television signal can be obtained by reading out the signal using a clock that is three times as large as the clock signal.

FIG. 4 shows a configuration diagram of a conventional example of parts related to the present invention. 11 is an antenna, 12 is a small screen insertion circuit, 13 is a video processing circuit, 14 is a cathode ray tube, 2
1 is a main screen tuner, 22 is an IF/video detection circuit, 23 is a sync separation circuit, 31 is a sub screen tuner, 32 is an IF/video detection circuit, 33 is a sync separation circuit, 41 is a memory, and 42 is a write 43 is a read clock generating circuit.

The small screen video signal obtained by the tuner 31 and the IF/video detection circuit 32 is written into the memory 41 by the write clock generation circuit 42 whose timing is determined by the synchronization separation circuit 33. The video signal written in the memory 41 is read out by the clock of the reading clock generation circuit 43 whose insertion timing is determined according to the synchronization signal separated from the video signal of the main screen by the synchronization separation circuit 23. Screen insertion circuit 12
is inserted into the video signal of the main screen.

FIG. 5 is a configuration diagram of yet another conventional example,
The same numbers as in FIG. 4 indicate the same functional blocks. The purpose of FIG. 5 is to display the child screen as a color image. 101 is a television receiver, 24 is a color signal processing circuit, 25 is a video amplification circuit, 121 is a small screen brightness signal insertion circuit, 12
2 is a sub-screen color difference signal insertion circuit, and 26 is a matrix circuit. Further, 102 is a small screen generation circuit,
34 is a color signal processing circuit, 35 is a video amplification circuit, 4
11 is a luminance signal memory, 412 is a B-Y signal memory, 413 is a R-Y signal memory, and 36 is a G-Y signal matrix circuit. Since the processing of the luminance signal is the same as the operation shown in FIG. 4, the explanation will be omitted, and the processing of the chromaticity signal will be described below.

The small screen video signal obtained by the tuner 31 and the IF/detection circuit 32 is demodulated by the color signal processing circuit 34 to obtain two color difference signals, the RY signal and the BY signal. Thereafter, the two color difference signals are sent to the B-Y signal memory 412 and R at predetermined timings.
-Write to Y signal memory 413. The color difference signals written in the B-Y signal memory 412 and the R-Y signal memory 413 are read out in accordance with the synchronization signal of the main screen, and the G-Y signal is reproduced by the G-Y matrix circuit 36. It is connected to the child screen color difference signal insertion circuit 122 of the television receiver 101, and is combined with the color difference signal of the main screen. On the other hand, the brightness signal of the child screen is combined with the brightness signal of the main screen in a child screen brightness signal insertion circuit 121 and drives the cathode ray tube 14 via the matrix circuit 26.

As explained above, when displaying a colorized child screen, two color difference signals are processed by separate memory circuits, so a monochrome screen is displayed.
The required memory capacity is three times that of a screen TV, and this is a major obstacle in constructing a color two-screen TV.

Furthermore, when reducing the memory capacity by reducing the number of pixels for color difference signals, there is a cost performance problem because the memory circuit requires a memory with a different number of pixels from the luminance signal memory 411.

An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art, to reduce the number of pixels of a color difference signal to half that of a luminance signal, and to configure a color difference signal memory circuit with a memory circuit having the same number of pixels as the luminance signal memory. By doing so, cost performance is improved and economic efficiency is improved.

In order to achieve the above object, the present invention selectively writes two color difference signals into a memory circuit alternately at a predetermined writing frequency (of a sufficiently short cycle compared to one horizontal scanning period), and then A feature of the present invention is that a compressed child screen is constructed by alternately selecting a readout frequency that is a predetermined writing frequency multiplied by a child screen compression ratio for pixel information read from a memory circuit.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 6 is a block diagram of the present invention. Figures 4 and 5
Since the same numbers as those in the figure represent the same functions, the explanation will be omitted. 414 is a memory for R-Y/B-Y signals, and its configuration is the same as the memory 411 for luminance signals.
51 is a switch circuit for selecting the RY and BY signals, 52 is a phase shift circuit, and 53 and 54 are flip-flop circuits for storing and holding information for one picture element.
Further, A represents a sub-screen RY signal, B represents a sub-screen B-Y signal, and C is a switching signal of the switch circuit 51. D is R-Y/B-Y signal memory 41
4 represents the input signal, and F represents the output signal. E is R-
The read clock signals G and H of the Y/B-Y signal memory 414 are respectively provided by the flip-flop circuit 5.
This is the clock signal that drives the clocks 3 and 54. J,I
are the reduced sub-screen R-Y signal and B-Y signal, respectively.
It's a signal. FIG. 7 is a timing diagram of FIG. 6, and K indicates the display period of the child screen. Sub screen RY
Signal A and sub-screen B-Y signal B are alternately selected by switching signal C, which is a first clock signal with a cycle sufficiently shorter than one horizontal cycle. Therefore, when the switching signal C is at "H" level, R-Y
Assuming that the signal is selected, the R-Y/B-Y signal memory circuit input signal D is such that the B-Y signal and the R-Y signal are alternately selected in time as shown in the figure, and the memory 4
14.

On the other hand, the memory circuit output signal F read out at a predetermined timing by the read clock signal E, which is a second clock signal obtained by multiplying the first clock signal by the compression ratio of the child screen (three times in this example), is , a flip-flop circuit 53 constituting a one-pixel memory,
54. Flip-flop circuit 53
In the flip-flop circuit 54, only the RY signal is selected and written at the rising timing of the clock signal G, while only the B-Y signal is selected and written in the flip-flop circuit 54 at the rising timing of the clock signal H. Therefore, the flip-flop circuit 5
The output signals 3 and 54 are J and I, respectively, and continuous small screen signals are reproduced.

FIG. 8 is a configuration diagram showing another embodiment of the present invention. Since the same numbers as in FIG. 6 represent the same functions, the explanation will be omitted. 61 is a delay element for one picture element information, and 62 and 63 are switch circuits. The switch circuits 62 and 63 are switched by the switching signal M, and when the switch circuits 62 and 63 are switched to the illustrated position, the pixel information in the R-Y/B-Y signal memory 414 is transferred to the switch circuit 63. 62, picture element information obtained by delaying the picture element information in the RY/BY signal memory 414 by the number of picture elements is output. When the switch circuits 62 and 63 are switched in the opposite direction as shown in the figure, contrary to the above, the switch circuit 63 has the pixel information in the R-Y/B-Y signal memory 414 delayed by one pixel. The picture element information or the picture element information of the RY/BY signal memory 414 is output to the switch circuit 64, respectively. FIG. 9 is a timing diagram of FIG. 8, where F is the output signal of the memory circuit read out from the R-Y/B-Y signal memory 414 at a predetermined timing E, and L is the output signal F. This is a signal delayed by one picture element. M is a switching signal for switch circuits 63 and 64, which alternately selects the output signal F of the memory and the delayed signal L, and reproduces consecutive small screen signals such as N and O.

In the above two embodiments, the color difference signals are alternately switched by the switching signal and stored in the B-Y/RY signal memory, so the number of pixels for each color difference signal is 1/1/1 that of the luminance signal. 2, and the color difference signal memory circuit can be configured with a memory circuit having the same number of pixels as the luminance signal memory.

As described above, according to the present invention, economic efficiency can be improved by reducing the number of pixels for color difference signals by half that of brightness signals and by making the memory circuit configurations for brightness signals and color difference signals the same.

In addition, since the clock period for alternately and time-selectively switching and storing two color difference signals in the color difference signal memory circuit is set to be sufficiently short compared to one horizontal period, color difference signals at almost the same time can be stored in the color difference signal memory circuit. can be used to prevent image quality deterioration.

[Brief explanation of drawings]

Figure 1 is a conceptual diagram of P in P, Figure 2 is a diagram showing an example of a raster for inserting a child screen, Figure 3 is a diagram explaining the conventional method of inserting a child screen, and Figure 4 is the same as that shown in Figure 3. A block diagram of a conventional device for realizing the method,
FIG. 5 is a block diagram of another conventional device, FIG. 6 is a block diagram of an embodiment of the present invention, FIG. 7 is a timing diagram of FIG. 6, and FIG. 8 is a block diagram of another embodiment of the present invention. 9 is a timing diagram of FIG. 8. 31...Sub screen tuner, 32...IF video detection circuit, 33...Synchronization separation circuit, 34...Color signal processing circuit, 35...Video amplification circuit, 36...G
-Y signal matrix circuit, 411, 414...
Memory, 42...Writing clock generation circuit, 43
... Read clock generation circuit, 51 ... Switch circuit, 52 ... Phase shift circuit, 53, 54 ... Flip-flop, 61 ... 1-picture element delay line, 62, 63
...Switch circuit.

Claims (1)

[Claims] 1 Luminance signal memory circuit where luminance signals are written and read, and color difference signal writing;
In a color two-screen display device that includes a memory circuit for color difference signals that is read out, and that compresses a second video screen at a predetermined reduction rate and inserts it as a child screen in a part of the first video screen. , said second
writing a first color difference signal and a second color difference signal of a video screen in the color difference signal memory circuit by alternately selecting the time using a first clock signal having a cycle sufficiently shorter than one horizontal scanning period; The first color difference signal and the second color difference signal written in the color difference signal memory circuit are clocked by a second clock signal having a period equal to the period of the first clock signal multiplied by the reduction rate of the sub-screen; The read out first color difference signal and second color difference signal are alternately selected, each signal is held for a time corresponding to one cycle of the second clock signal, and the first and second color difference signals are read out. A color two-screen display device characterized by obtaining signals simultaneously.