JPH0690414A - Picture in picture circuit - Google Patents

Abstract

PURPOSE:To eliminate the degradation of the picture quality due to erroneous discrimination of a field and to easily and accurately correct the display position at the time of the correction of an aspect ratio in this circuit. CONSTITUTION:The circuit is provided with a means for switching among plural RCK frequencies, a first horizontal delay circuit 1 for which at least a horizontal synchronizing signal is inputted, a second horizontal delay circuit 2 for which a vertical synchronizing signal is inputted, and a vertical delay circuit 3 for which the output of the second horizontal delay circuit 2 is applied and first and second horizontal delay circuits 1 and 2 are controlled in common and have the same delay time, and the maximum value of this delay time is set to about one horizontal period, and the delay time of the vertical delay circuit 3 is set to the integer multiple of one horizontal period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a picture-in-picture system built in a video device such as a color television receiver (hereinafter referred to as a television) or a video tape recorder (hereinafter referred to as a VTR). The present invention relates to a circuit hereinafter referred to as PIP), and particularly to a picture-in-picture circuit suitable for obtaining two or more types of PIPs having different aspect ratios.

[0002]

2. Description of the Related Art Generally, a PIP displays a child image which is different from the parent image on a part of the parent image, and the sync signal between the parent image and the child image is not synchronized. Since the child image size is generally smaller than the parent image size, at least the child screen is written into the image memory such as the field memory by the write clock synchronized with the child screen (writing clock is hereinafter referred to as WCK). Is realized by a digital technology in which a read clock is synchronized with the parent screen (a reading clock is hereinafter referred to as RCK) to read and display the image on the parent screen.

As a method of controlling the aspect ratio of the sub-screen, (1) the vertical (hereinafter vertical is represented by V) size is controlled. (2) The horizontal (hereinafter, horizontal is represented as H) size is controlled. (3) Control both vertical and horizontal sizes. There are three means. The aspect ratio is 4: 3 in the main screen
NTSC sub-screen or aspect ratio of 16:
When displaying the sub-screen of the HDTV system of No. 9, it is desirable to change the H size without changing the V size in view of display quality. The most effective means of changing the H size is the RCK.
Is to switch the frequency of.

FIG. 2 is a block diagram of a conventional PIP circuit. In particular, a general PIP circuit having an aspect ratio switching function is provided.
It is a block diagram of an IP circuit. First, the writing of the child screen information into the image memory 27 will be described with reference to FIG. The composite video signal of the child screen (hereinafter referred to as the child signal) is separated into the luminance signal Y and the chroma signal C by the YC separation circuit 22, and the chroma signal C is demodulated into the color difference signals BY and RY. . These Y, BY, RY
The signal is input to the image memory 27 through an analog / digital converter (hereinafter referred to as A / D) 25. Child horizontal sync signal SH obtained by the child sync separation circuit 24,
The child vertical synchronizing signal SV is input to the WCK control circuit 26, and the child screen information is written in the image memory 27 by the WCK synchronized with the child screen.

Next, the reading of the child screen information from the image memory 27 will be described with reference to FIG. The total delay circuit C2 is mainly composed of an H delay circuit 35 and a V delay circuit 36. The horizontal sync signal (MH) of the parent screen and the vertical sync signal (MV) of the parent screen are PIP display positions on the parent screen. H delay circuit 35 and V delay circuit 3 for controlling
After being delayed by 6, each is input to the RCK control circuit 38 as the horizontal synchronizing signal MH1 and the vertical synchronizing signal MV1, and the child screen information accumulated in the image memory 27 is read out by the RCK synchronized with the parent screen, that is, RCKM, It is converted into an analog RGB signal through a digital / analog converter (hereinafter referred to as D / A) 28 and a matrix circuit 29, and is mixed with a parent RGB signal by a high-speed switch 30 to form a parent-child combined RGB signal. The switching of the high speed switch 30 is controlled by a signal from the terminal 66 of FIG. 3, which will be described later.

The main role of the total delay circuit C2 shown in FIG. 2 will be described. A display position control signal including an H delay control signal and a V delay control signal is applied to the terminals 33 and 34. Then, according to the H delay control signal applied to the terminal 33, the original horizontal synchronization signal M of the parent image is supplied to the H delay circuit 35.
A synchronizing signal MH1 delayed from H is generated and input to the RCK control circuit 38, and in the same manner, in accordance with the V delay control signal applied to the terminal 34, the V delay circuit 36 receives the original image of the parent image. Of the vertical synchronizing signal MV of the vertical synchronizing signal MV is generated, the synchronizing signal MV1 is input to the RCK control circuit 38, and the operation start time of the RCK control circuit 38 is applied to the terminals 33 and 34. The main function of the total delay circuit C2 is to arbitrarily change it according to the signal.

FIG. 3 is a general block diagram of the RCK control circuit 38. The synchronizing signal MH1 respectively delayed by the H delay circuit 35 and the V delay circuit 36 shown in FIG.
MV1 is the H delay circuit 53 and the V delay circuit 54 shown in FIG.
The H delay circuit 53 outputs the synchronizing signal MH2 with the RCK oscillator output as the clock, and the V delay circuit 54 outputs the synchronizing signal MV2 with the synchronizing signal MH2 as the clock. In this way, the synchronization signal MH
1 and MV1 are given respective predetermined delay amounts.

The synchronizing signal MH2 and the output signal MV2 of the V delay circuit 54 are input to a horizontal monostable multivibrator (H-MSM) 55 and a vertical monostable multivibrator (V-MSM) 56, respectively. It Output signals MH3 and MV3 of the H-MSM 55 and V-MSM 56 are both AND circuits (AND circuits).
Circuit 57, and the output signal thereof is output to the terminal 66 and serves as a control signal for the switch 60. That is, the signal at the terminal 66 turns on the output signal of the RCK oscillator 59.
This switch 60 controls the switch 60 that turns on / off.
Is the signal output to the terminal 62 and applied to the image memory 27, that is, RCKM. The H delay circuit 53 and the V delay circuit 54 shown in FIG.
Correct the time position of V1 to display the child screen (PI
The position of P) is fixed, and a fixed count value type counter is generally used.

The two monostable multivibrators 5
Reference numerals 5 and 56 operate by using the synchronization signals MH2 and MV2 as trigger signals, respectively, and generate pulses for setting the display width in the H direction and the V direction of the PIP, and the output of the RCK oscillator 59 and the The monostable multivibrator 5 using the synchronization signal MH2 as each clock.
The width of the output pulse of 5, 56 is determined, and P
The horizontal display period and the vertical display period of the IP are determined. Therefore, by controlling the frequency of the RCK oscillator 59, that is, by controlling the aspect ratio switching signal, the display period in the horizontal direction changes. On the other hand, the display period in the vertical direction does not change.

On the other hand, the RCK control circuit 38 performs field discrimination based on the relative phase of the synchronization signal MH1 and the synchronization signal MV1, and reads the child screen of the field that matches the current field of the parent screen. If the field discrimination is not performed correctly, the n-th horizontal line and the (n + 1) -th horizontal line of the sub-screen are turned upside down, and the image quality deteriorates. When the oscillation frequency of the RCK oscillator 59 is switched to switch the H size of the child image and the aspect ratio of the child screen is switched, the clock frequency applied to the H delay circuit 53 also changes according to the above principle, and the horizontal delay The display position also changes.

Therefore, it is necessary to correct the phase of the synchronizing signal MH1 by the H delay circuit 35 so that the horizontal position of the PIP screen does not change at any RCK frequency. However, if only the H delay circuit 35 is corrected here for position correction, the field determination circuit 58 in the RCK control circuit may malfunction. This will be described later with reference to FIGS. 4 and 5.

Further, by positively utilizing the H delay circuit 35 and the V delay circuit 36, P can be set at an arbitrary position on the main screen.
It is possible to display the IP, but the same problems as described above occur. In order to solve this, H shown in FIG.
Both the delay circuit 35 and the V delay circuit 36 may be changed simultaneously within the range of 0 to 262H so as not to cause the field determination circuit 58 in the RCK control circuit 38 to malfunction. However, according to this, since it is usual to configure the two delay circuits with a counter or a memory, a very large-scale counter circuit is required or a large memory capacity is required, which is very difficult to realize.

FIG. 4, FIG. 5, and FIG. 8 show the general P described above.
6 is a time chart for explaining the operation of the IP circuit. FIG. 4 is a diagram for explaining the operation of the field discrimination circuit 58. For example, when the rising edges of the vertical synchronizing signal MV1 and the horizontal synchronizing signal MH1 are substantially equal to each other, the current parent screen is in the first field, and the vertical synchronizing signal MV1 rises near an arbitrary horizontal synchronizing signal and the next horizontal synchronizing signal. If it has risen, it is determined to be the second field.

FIG. 5 is a diagram for explaining a malfunction of the field discrimination circuit 58. In FIG. 5, since the rising edges of the synchronizing signals MH and MV are substantially the same, this field is an odd field, for example, the first field. However, the synchronization signal MH1, which has passed through the delay circuit,
Comparing the rising edges of MV1, according to the principle described with reference to FIG. 4, there is an example in which the field discrimination circuit 58 makes an erroneous discrimination because there is a phase relationship as if it were an even field, for example, a second field.

FIG. 7 is a diagram showing an example of the PIP screen, in which a child screen is displayed at the lower right of the parent screen. Regarding the display position and the display period of the small screen, in the vertical direction, the small screen is displayed during the time TV after the time VP elapses from the time when the upper end is displayed. In the horizontal direction, the time is displayed for the time TH from the time when the time HP has passed since the left end display. That is, the shaded area in FIG. 7 is the sub-screen in PIP.

FIG. 8 is a diagram showing the phase relationship of each signal during the PIP operation. The time chart shown in FIG. 8 shows the phase relationship of each signal in the PIP screen shown in FIG. 7, and the sub-screen is displayed by the signal MV3.
Is at the H level within the period TV and the signal MH3
Is within the period of time TH when H becomes H level. That is, FIG.
The child screen is displayed when the logical product output output to the terminal 66 shown in FIG.

[0017]

SUMMARY OF THE INVENTION According to the present invention, the H of the child screen is displayed.
The present invention relates to a PIP system capable of changing a size by changing a frequency of RCK and displaying a small screen at an arbitrary position on a main screen, and particularly to a HIP system.
When the delay time and the V delay time are arbitrarily set and the child screen is displayed at an arbitrary position on the parent screen, the H delay circuit and the V delay circuit that easily prevent the image quality from being deteriorated due to field misjudgment can be easily provided. Aim to achieve.

[0018]

The PIP circuit of the present invention comprises:
It has means for writing a signal of the child screen to the image memory, and means for reading the child screen signal from the image memory in synchronization with the parent screen, and this reading means is for reading the clock (RCK) oscillation circuit and the parent screen. A field discriminating circuit for comparing the phases of horizontal and vertical synchronizing signals, a horizontal delay circuit and a vertical delay circuit are provided, and at least the horizontal delay circuit is a picture-in-picture (PIP) circuit which operates by a clock synchronized with the RCK. Wherein a means for switching a plurality of RCK frequencies, a first horizontal delay circuit to which at least a horizontal synchronizing signal of the parent screen is input, a second horizontal delay circuit to which a vertical synchronizing signal of the parent screen is input, A vertical delay circuit to which the output of the second horizontal delay circuit is applied, and the first and second horizontal delay circuits are controlled in common and Has one of the delay time, form a maximum value of the delay time to approximately one horizontal period, it is characterized in that an integral multiple of the delay time of one horizontal period of the vertical delay circuit.

[0019]

1 is a block diagram of an integrated delay circuit C1 in a PIP circuit of the present invention, which is mainly composed of two H delay circuits 1 and 2 and one V delay circuit 3. The two H delay circuits 1 and 2 have substantially the same electrical characteristics. The horizontal synchronizing signal MH of the main screen is one H
The signal is input to the delay circuit 1 via the terminal 31, and its output signal MH1 is output to the terminal 6. On the other hand, the vertical synchronizing signal MV of the parent screen is input to the other H delay circuit 2, its output signal MV0 is input to the V delay circuit 3, and its output signal M
V1 is output to the terminal 14. An H delay control signal common to the H delay circuit 1 and the H delay circuit 2 is applied to the terminal 12 to set a predetermined delay amount. Therefore, the H delay circuit 1 and the H delay circuit 2 have the same delay time, and the control range of this delay time is 1H at maximum (about 63.5 in the case of NTSC system).
μs).

In the V delay circuit 3, one horizontal period (1
H) as a unit step, maximum 262H (about 525/2
: In the case of the NTSC system), the delay amount can be arbitrarily set by the V delay control signal applied to the terminal 13. Therefore, the H delay circuit 1 and the H delay circuit 2 are delay circuits or memory circuits having the same structure, and the common horizontal synchronizing clock CLK1 is supplied to the terminals 4 and 8 of the H delay circuits 1 and 2 via the terminal 10, respectively. A common H delay control signal is applied to terminals 5 and 7 when applied. Further, the V delay circuit 3 is
It is a delay circuit that can obtain a delay amount of 1H step by the horizontal synchronizing clock CLK2 applied from the terminal 11, and can be realized by a delay circuit or a memory circuit like the H delay circuits 1 and 2.

FIG. 6 is a time chart of the PIP circuit of the present invention. Since the rising edges of the horizontal synchronizing signal MH and the vertical synchronizing signal MV of the parent screen are substantially the same, the current field is an odd field. Output MH of the H delay circuit 1
1, the output MV0 of the H delay circuit 2 is a signal delayed by the time T1 with respect to the synchronization signals MH and MV. The synchronization signal MV0 is a signal further delayed by the time T2 by the V delay circuit 3. Since this time T2 is an integral multiple of one horizontal period (1H), the rising edge of the synchronizing signal MV1 and the rising edge of the synchronizing signal MH1 are substantially the same, and according to the principle described with reference to FIG. An accurate determination is made that the field of the current screen is an odd field.

The H delay circuit 1 and the H delay circuit 2 are
If the clock frequency CLK1 is, for example, 64 times the horizontal frequency fh, the clock frequency CLK1 can be configured by a 64-ary counter, and the variable minimum step of the delay amount is about 1 μs (63.
5/64), which is a fine step in the horizontal direction, and when the V delay circuit 3 is a 262 counter that operates with a clock of fh, the variable step in the vertical delay amount is 1H unit, and the maximum delay time is Can be 262H.

As described in detail above, the PI of the present invention
The P circuit can achieve the intended purpose with a simple circuit configuration and is very advantageous in terms of cost. In the total delay circuit C1 shown in FIG. 1, the horizontal synchronization clock CLK1 and the vertical synchronization clock CLK2 are
Whether it's a common clock or different clocks,
There is no problem under the condition that it fully satisfies the variable step of horizontal position.

[0024]

According to the PIP circuit of the present invention, when the H delay time and the V delay time are arbitrarily set and the child screen is displayed at an arbitrary position on the parent screen, the image quality is deteriorated due to erroneous field discrimination. Therefore, the display position can be corrected easily and accurately when the RCK is controlled to correct the aspect ratio.

[Brief description of drawings]

FIG. 1 is a block diagram of an integrated delay circuit according to the present invention.

FIG. 2 is a block diagram of a conventional PIP circuit.

FIG. 3 is a block diagram of a conventional RCK control circuit.

FIG. 4 is a diagram illustrating an operation of a field determination circuit.

FIG. 5 is a diagram illustrating a malfunction of the field determination circuit.

FIG. 6 is a time chart of each signal in the PIP circuit of the present invention.

FIG. 7 is a diagram showing an example of a PIP screen.

FIG. 8 is a diagram showing a phase relationship of each signal during PIP operation.

[Explanation of symbols]

 1 H delay circuit 2 H delay circuit 3 V delay circuit 22 YC separation circuit 23 color demodulation circuit 24 child screen synchronization separation circuit 25 A / D converter 26 WCK control circuit 27 image memory 28 D / A converter 29 matrix circuit 30 high speed Switch 38 RCK control circuit 53 H delay circuit 54 V delay circuit 55 Horizontal monostable multivibrator 56 Vertical monostable multivibrator 57 Accumulator 58 Field discrimination circuit 59 RCK oscillator C1 Total delay circuit C2 Conventional total delay circuit MH Main screen Horizontal sync signal MV Vertical sync signal of main screen

Claims (1)

[Claims] 1. A means for writing a signal of a child screen to an image memory, and a means for reading the child screen signal from the image memory in synchronization with a parent screen, the reading means comprising:
Horizontal of read clock (RCK) oscillation circuit and main screen,
A field discrimination circuit by comparing the phase of the vertical synchronization signal,
In a picture-in-picture (PIP) circuit, which comprises a horizontal delay circuit and a vertical delay circuit, at least the horizontal delay circuit being operated by a clock synchronized with the RCK, a means for switching a plurality of RCK frequencies, and at least a parent circuit. A first horizontal delay circuit to which a horizontal sync signal of the screen is input, a second horizontal delay circuit to which a vertical sync signal of the parent screen is input, and a vertical to which an output of the second horizontal delay circuit is applied. A delay circuit, the first and second horizontal delay circuits are controlled in common and have substantially the same delay time,
A picture-in-picture circuit, wherein the maximum value of the delay time is set to approximately one horizontal period, and the delay time of the vertical delay circuit is set to an integral multiple of one horizontal period.